JPH0396997A - Scroll display device - Google Patents

Abstract

PURPOSE:To decrease the number of processes and to make a scroll display with small-sized constitution by controlling a CRT controller by a CPU, reading division data out of a video memory, and displaying time, line by line, on a display screen as specified. CONSTITUTION:When upward scrolling is indicated, the CPU executes an upward scrolling display program and the start address of the video memory 2 is set in the address counter 108 of the CRT controller 1. At the same time, the start addresses and the numbers of rasters of respective divided images on the memory 2 are set in display start address registers and display raster quantity registers 101a and 102a - 101h and 102h respectively. The divided image information desired is read out of the memory 2 according to those set values, the divided images are displayed, line by line, in order at the lowest-order address of a CRT to make an upward scroll display, and a downward scroll display is also made similarly to make the scroll displays with the small-sized constitution which decreases the number of processes without processing all the information on the memory 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scroll display device used in an information processing device or the like that can scroll and display a display screen by a predetermined number of display rasters.

[Prior Art] FIG. 6 is a block diagram showing an example of a conventional image display circuit in an information processing device.

Control commands and data are exchanged via address bus A and data bus B. Address bus A has a CPU
IO, main memory 20, and address selector 50 are connected, and data bus B is connected to CPUIO, main memory 20, and bus transceiver 60, respectively. CRTC/10 is a display controller 1 roll circuit for generating a display address J of CR'J'90.

Further, the address selector 50 performs an operation of switching the address C of the display memory 30 to the address path path or the display address D.

The bus transceiver 60 transmits and receives data between the data bus B and the display memory data E.

The data launcher 70 latches the data R output from the display memory 3o once, and then outputs it to the shift 1 to register 8o that performs parallel/serial conversion.

The shift 1 to register 80 convert the parallel data sent from the data latch 70 into serial data, generate a video signal, and send it to the CRT 90.

Here, the CRT 90 is a display cathode ray tube, and displays images in response to the video signal F. In such a configuration, while the screen is being displayed on the CRT90,
('l.R'T' C40 sequentially generates display addresses I to 1 and instructs the display memory 30 to display the display addresses via the address selector 5o.

The data in the display memory 30 corresponding to the display address is converted into a video signal F by the shift register 80 via the data latch 70 and displayed on the CRT 90.

In addition, when C I"U ].O directly accesses the display memory 30, the address selector 50 operates to supply the data from the data bus 71 to the address bus A to the display memory address C, and the bus 1 to the transceiver 60 By operating to supply data from B as display memory data E, the CPU 10 can read and write to the display memory 30.

[Problems to be Solved by the Invention] However, in the circuit having the above configuration, the display memory 30 is required to be faster than the main memory 20, which is disadvantageous in terms of cost and mounting area.

Therefore, in conventional devices, a memory having a storage capacity for one picture display is often used as the display memory 30.

In such a device, when an image of C R l' 9 0 is displayed with X vertical lines and Y bytes horizontally, and you try to scroll this display, C I] U 1.
Since data stored in the display memory 30 must be rewritten for the entire screen, the display memo 34 must be accessed xXy times.

Therefore, the higher the display device ii"+: of the high-fit image, the more the CPU
The number of accesses to cpu i. There was a problem in that the size of the screen became large, it took a long time to scroll, and it was not possible to scroll smoothly.

According to the present invention, when scrolling, the higher the resolution becomes, the higher the resolution becomes.
This was done in order to solve the problem of time consuming, and to reduce the number of accesses to the display memory from the scroll Ik\C T}tJ and provide a scroll display device that can perform high-speed scrolling. purpose.

[Means for Solving the Problems] The present invention provides a means for specifying an area of a display memory in which display data to be deleted from the display screen is stored when scrolling is specified, and a means for specifying an area on the display screen in accordance with scroll execution in a scroll display device F1l. means for displaying new display data to be displayed in the area, and display data written in the above line so that it is displayed on the bottom line of the display screen when scrolling up, and on the top line when scrolling down. The controller 1 is provided with means for controlling the controller 1 to the roll circuit.

[Operation] The present invention specifies the area of the display memory that stores the image data of the number of display rasters specified for scrolling in the divided screen, and displays a new display in this specified area as the scroll is executed. The overwritten display data is displayed on the bottom line or the top line of the display screen.

Therefore, scrolling can be performed simply by accessing the display memory that stores only a portion of the split screen.

[Example 1] Hereinafter, a practical example of the present invention will be explained in detail based on the drawings.

First, before explaining the embodiments of the present invention, we will first explain a display control circuit (CRTC) that sequentially generates display addresses for dividing and displaying a plurality of screens by a predetermined number of display rasters on a display screen. explain.

Figure 3 is from JP-A-60-22-1. FIG. 8 is a circuit diagram of a CRTC shown in Publication No. 8'1. ■ is C
2 is a video memory that stores display data, and 3 is a parallel/serial converter that converts the parallel display data read from the video memory 2 into serial data and generates a video signal. P-S). /1 indicates a 1-1-1/Y lock generation circuit that generates the sending timing of this video signal.

Display data “A” is stored in the video memory 2 as shown in FIG.
, II B I+, ... "H" is stored, C RT
The screen will be split into two. N, ,N? ,...N. is the display start address, nl. n,,,...n. a indicates the number of displayed rasters, and y indicates the number of addresses per raster. To write to the video memory 2 (drawing mode), a microprocessor (hereinafter referred to as CPU) (not shown) sets the mode 1 to register 1]O to the cat drawing mode, and writes the address counter 108 to the first storage address 1 to address of the video memory 2. Seso 1
The output of the address counter 108 is applied to the address bus 6 of the video memory 2 via the address selector 109, and a write signal is sent to the control bus 7 from a control circuit (not shown) of the CRT controller 1-roller 1. This is executed by supplying display data to the data bus 8.

The CPU also determines display start addresses N, . N, ,...N. of,
Corresponding display start address register 101a, 10
]. b, ...-101h, the number of displayed rasters nl
．． n2,...n. to the corresponding display raster storage register 102a. 102b, . . . 102h.

Display data from video memory 2 it A ++, II B
II... In the so-called display mode in which "I-1" is read out and displayed on the C scale T screen, the split screen counter 105 is reset from 1 to 1, and the display start 71 to response selector 103 and display raster selector 1. 04 to display start address register 10]. a. Display raster storage register]. 0 2 a is selected and set in the display address counter 106 and raster counter 107 8 7, respectively. The output of the display address counter 106 is sent to the address bus 6 via the address selector 109, and when a read signal is given to the controller 1 to roll bus 7, Display data is read out onto the data bus 8 from the data bus 8.

The read data is outputted as a video signal via the parallel/serial converter 3. At this time, mode register 1 1. 0 is set to display mode by CPU 1
~ has been done, and 71~ response selector 109 is displayed 71~
It operates to select and output the output of the response counter 106. When the display data of one address is output as a video signal,
Pulse to clock 6 to dot 1 (71-reschronok)
A pulse is output from the frequency divider circuit 1 1 1 that generates
The display counter 106 increments by 1.

This address chronograph is 71-res y per raster
When 1. is counted, a pulse (raster clock) is output from the frequency dividing circuit 112, and the raster counter 1. 0
7 goes down by 1. When the count 1 to value of the raster counter 107 becomes uOr+, the split screen counter]. 0 5 is counted 1 ~ amplified, display starts 71 ~
The address selector 103 and raster selector 104 select the output of the display start address register 10lb and display raster storage register 102b of the next split screen, respectively, and send these outputs to the display address counter 106 and raster counter 107 in the same manner as described above. cent, and perform the same process below.

Thereafter, each time the count value of the raster counter 107 reaches "O", the divided screen counter 105 is incremented by 1, and the same processing is continued. When display data for one screen is read out from the video memory 2, the split screen counter 10
5 is initialized and displays the display start address register 101 again.
a. The output of the display raster storage register 102a is set to the display address counter 106 and raster counter 107.
be done.

Next, a method of controlling access to the video memory and the C length 'I''C during scrolling according to the present invention will be explained.

FIG. 5 shows the initial settings of the display screen. ]
Display start 71 Helles register J O]. tr is the first display address of the video memory (hereinafter this address will be referred to as Nm)
jn), 1st-display raster storage register 1 0
2a is set to the number of displayable rasters (hereinafter referred to as X) determined by the specifications of the display device. Figure 5 shows the data rr written by the CPU to the video memory 2.
y. This shows that r+ to LL 8 I+ are displayed as they are on the display screen.

Although the display is not affected at this stage, initial settings are made to set the display start address register 101b of the next screen to Nmin and the display raster storage register 102b of the next screen to ○.

FIG. 1 shows a C for implementing scrolling according to the present invention.
I) This shows the flowchart 1 of the U program. In FIG. 1, y:] video memory per raster 31kn. : J line scroll special, number of rasters to move Ns: 1 line scroll l
l+f video memory area I-res change amount=nsXy Nmax: Area 1/res of the final display raster of the video memory W: Variables used for program control of the CPU, and are respectively defined.

The control method is based on the direction of scroll movement (step 101).
It is divided into two depending on the In the case of scrolling up, the process moves to step 102.

Note that scrolling means that the entire CRT display moves up and the new next line of data is displayed on the bottom line, and scrolling down means that the entire CRT display moves downwards. This means that the new next row of data is displayed on the top row.

For scrolling up, start display address register 1
01a and the address Nma of the final display raster in the video memory
x-Ns, and the first display address register 101
When a is smaller than the value of address Nmax - Ns, the process moves to step 1 0 3 and address register 1. 0
1 Save the value of a in variable W.

1 1 - 1 2 address register 1 0 1. Update the value of a by adding the change in video memory address N8 (step 10/I) - I1 of raster register J O 2 a
Subtract and update 1L by the number of rasters moved during scrolling, 08, and then update the value of raster register 102b on the next screen.
Add and update the number of rasters n8 (step 106)
. Next, from the video memory's W ai-res to W ten Ntq-
171.' By the time of reply, the data of the next line newly displayed by scrolling up will be corrupted (step 107
). As a result, the display moves up by n8 rasters and scrolls up.

FIG. 2A shows the relationship between the video memory and the display surfaces at this time. A new digit of data is written by the CPU into the video memory corresponding to the address indicated by diagonal lines in the figure, and is displayed on the bottom line by scrolling.

Next, the value of address register 101a is address N + n
If ax − N g is greater than address register 1 0 1 . The first display address Nmin of the video memory is set in a (step 108), and the number of displayable lines X is set in the raster register 102a (step 10).
9). Set the value of the start address register 102b on the next screen to O.
(step 110), and saves the value of the final display raster address Nmax N s + y in variable W (step 111).

Thereafter, the stepper 107 writes data for scrolling up, and scrolling is executed.

FIG. 2B shows the relationship between the video memory and the display screen at this time. Scroll data is rewritten in the display data G portion indicated by diagonal lines in the figure, and is displayed after scrolling.

Next, the process when scrolling down will be explained. When scrolling down, the stenoop 112 compares the value of the address register 101a with the display address Nmin at the beginning of the video memory. If this value is greater than Nmjn, proceed to step 117; if equal, proceed to step 113.
Proceed to. Here, steps 113-1. 1 to 6, respectively, and change the values of the registers in the CRTC according to steps 1 to 6, and in accordance with the value in the variable W set in step 116, in step 121, from the W address of the video memory to W+N.
] Write the newly displayed data by scrolling down to the address.

This scrolls down and displays the updated display data in the top row.

FIG. 2C shows the relationship between the video memory and the display screen at this time. As shown in the figure, the corresponding y
The data of the part marked 1 is replaced by 71F and displayed on the top line after scrolling down.

Next, if the value of the 71-res register 101a is larger than Nmin, the C R i'' C register is updated according to steps 117 to 1-20, and the image is updated according to step 12. It corrupts the memory and scrolls down the appearance.

FIG. 2D shows the relationship between the video memory and the display screen at this time. The data in the shaded X area in the figure is rewritten and displayed on the top line when scrolling down.

Note that the present invention is not limited to CRT displays;
Needless to say, it can also be used for display devices that perform raster scanning.

[Effects of the Invention] As described above in detail based on the embodiments, the present invention uses a CRTC that performs split display control.
By controlling C according to the above-described algorithm, the amount of data to be rewritten in the video memory when the screen is scrolled is greatly reduced from the entire screen to the amount of data whose display is newly changed due to scrolling.

Therefore, it has the great advantage of reducing the load on the CPU and enabling high-speed processing.

[Brief explanation of drawings]

FIG. 1 shows a flowchart 1 to 2 for scrolling according to an embodiment of the present invention, and FIGS. 2A to 2D show the relationship between the video memory and the display screen when processing is performed according to the flowchart in FIG. FIG. 3 is a circuit diagram showing an example of a display control circuit that performs split display, FIG. 4 is an explanatory diagram of the operation of FIG. 3, and FIG. FIG. 6, which is a diagram showing the initial settings of the screen, is a block diagram of a conventional image display circuit. 101a, 101b--Start display of each divided screen 71-res register,]. 0 2
a, 102b... Display raster storage register for each split screen, n q. ... Number of rasters moved when scrolling one line, N3 ... Change in video memory I-res when scrolling one line, Nmax ... Address of the last displayed raster in the video memory, W- -Variables used for CPU program control.

Claims (1)

[Claims] A display control circuit (CRTC) that sequentially generates display addresses for dividing and displaying a plurality of screens by a predetermined number of display rasters on a display screen; In a scroll display device comprising a display memory for reading and outputting image data to be displayed on a display screen using a scroll display device, a first step for specifying an area of the display memory in which display data to be deleted from the display screen is stored when scrolling is specified.
a second means for overwriting the area with new display data on the display screen as the scroll is executed; and a second means for overwriting the overwritten display data on the bottom line of the display screen when scrolling up and on the top line when scrolling down. and third means for controlling the display control circuit to display.