[go: up one dir, main page]

JPH0387934A - Program monitor - Google Patents

Program monitor

Info

Publication number
JPH0387934A
JPH0387934A JP22611989A JP22611989A JPH0387934A JP H0387934 A JPH0387934 A JP H0387934A JP 22611989 A JP22611989 A JP 22611989A JP 22611989 A JP22611989 A JP 22611989A JP H0387934 A JPH0387934 A JP H0387934A
Authority
JP
Japan
Prior art keywords
task
address
monitor
program
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22611989A
Other languages
Japanese (ja)
Inventor
Hiroyuki Endo
遠藤 弘行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Computertechno Ltd
Original Assignee
NEC Computertechno Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Computertechno Ltd filed Critical NEC Computertechno Ltd
Priority to JP22611989A priority Critical patent/JPH0387934A/en
Publication of JPH0387934A publication Critical patent/JPH0387934A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the development efficiency of a task program of large capacity by securing such a constitution where a program monitor switches a task to an address bank which stores the task program by reference to a table of address banks storing the task programs. CONSTITUTION:When a monitor acquires the executing right of a CPU, the monitor calculates a task to be started next and transfers the executing right of the CPU to this task to perform a task switching process. Then the monitor calculates the ID number of the task to be started next and acquires an address bank and an execution address via a table consisting of the address banks 2, 5 and 8 and the task execution addresses 3, 6 and 9. The monitor switches the address banks based on the acquired address bank, opens the register and the work area necessary for the task to be started to the due task, and transfers the executing right of the CPU to the task based on the acquired execution address. As a result, a task program of large capacity easily is developed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はモニタに関し、特に各タスクに対応するアドレ
スバンクを示すテーブルとタスクを起動する際に該タス
クのプログラムを内蔵するアドレスバンクに切り替える
機能を含むモニタに関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a monitor, and in particular, a table showing address banks corresponding to each task and a function to switch to an address bank containing a program for the task when starting a task. Regarding monitors including

〔従来の技術〕[Conventional technology]

従来、この種のモニタは、タスク切り替えを行なう際に
、アドレスバンクを切り替える機能が無かった。
Conventionally, this type of monitor has not had a function to switch address banks when switching tasks.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のモニタは、タスク切り替えの際にアドレ
スバンクを切り替える機能が無かったため、アドレス空
間の狭いCPUを使用する時、タスクのプログラム容量
が大きくなると、タスクプログラム自身でバンク切り替
え等の作業を行なわなければならず、作業量が増え、タ
スクプログラム製造上の間違いが発生し易くなるという
欠点がある。
The conventional monitors mentioned above did not have a function to switch address banks when switching tasks, so when using a CPU with a narrow address space or when the program capacity of a task becomes large, the task program itself has to perform tasks such as switching banks. This has the disadvantage that the amount of work increases and errors in task program production are more likely to occur.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のプログラムモニタは、各タスクに対応するアド
レスバンクを示すテーブルと、タスク切り替えを行なう
際、各タスクに対応するアドレスバンクに切り替える手
段を有している。
The program monitor of the present invention has a table showing address banks corresponding to each task, and means for switching to the address bank corresponding to each task when switching tasks.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は、各タスク単位に持ち、タスクiD番号1・4
・7とタスクのアドレスバンク2・5・8とタスクの実
行アドレス3・6・9から成る。
In Figure 1, each task has task ID numbers 1 and 4.
7, task address banks 2, 5, and 8, and task execution addresses 3, 6, and 9.

第2図はモニタのタスク切り替え処理のフローチャート
である。
FIG. 2 is a flowchart of the monitor task switching process.

モニタがCPUの実行権を入手した時、次に起動するべ
きタスクを算出し、そのタスクにCPUの実行権を渡す
When the monitor obtains the right to execute the CPU, it calculates the task to be started next and gives the right to execute the CPU to that task.

この時タスクの切り替え処理を行う(第2図参照〉。At this time, task switching processing is performed (see Figure 2).

モニタは、次に起動すべきタスクのiD番号を算出し、
アドレスバンク2・5・8とタスク実行アドレス3・6
・9から戒るテーブルより、アドレスバンクと実行アド
レスを入手する。
The monitor calculates the ID number of the task to be started next,
Address banks 2, 5, 8 and task execution addresses 3, 6
・Obtain the address bank and execution address from the table from 9.

入手したアドレスバンクに従いアドレスバンクを切り替
え、起動するタスクに必要なレジスタ及びワークエリア
をタスクに開放し、入手した実行アドレスを基にCPU
の実行権をタスクに渡す。
Switches the address bank according to the obtained address bank, releases the registers and work area necessary for the task to be started, and executes the CPU based on the obtained execution address.
Pass execution rights to the task.

〔発明の効果〕 以上説明したように本発′明は、プログラムモニタがタ
スクを切り替える際に、タスクプログラムが格納されて
いるアドレスバンクのテーブルを参照し、前記タスクの
プログラムが格納されるアドレスバンクに切り替えるこ
とにより、容量の大きいタスクプログラムの開発を効率
的にかつ製造上の間違いを減少させることができる効果
がある。
[Effects of the Invention] As explained above, the present invention provides that when a program monitor switches a task, it refers to a table of address banks in which task programs are stored, and selects an address bank in which a task program is stored. By switching to , it is possible to efficiently develop large-capacity task programs and reduce manufacturing errors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す模式図、第2図はタス
ク切り替えの際に行なうアドレスバンク切り替えのフロ
ーチャートである。 l・・・タスク1のiD番号、2・・・タスク1のアド
レスバンク、3・・・タスク1の実行アドレス、4・・
・タスク2のiD番号、5・・・タスク2のアドレスバ
ンク、6・・・タスク2の実行アドレス、7・・・タス
クrtのLD番号、8・・・タスクnのアドレスバンク
、1−−一 タスクlθ1I)kう 2−−一 タスクlのアトLスノV>73−−一タズ7
1の実行アF’Lス 4−− クス7ZのiD許号 S −−一 タスクZカア)′Lス八へり1 −−一 
タスクz/)実fデアト°゛1ス7−一一 クス7πの
iDkう θ −一一タズ74tのア1−Lズハ”二7ダ −−−
タズフサしl紀行アトLス 猶1■ 弔2図
FIG. 1 is a schematic diagram showing an embodiment of the present invention, and FIG. 2 is a flowchart of address bank switching performed when switching tasks. l... ID number of task 1, 2... address bank of task 1, 3... execution address of task 1, 4...
- ID number of task 2, 5... address bank of task 2, 6... execution address of task 2, 7... LD number of task rt, 8... address bank of task n, 1-- 1 Task lθ1I)kU2--1 Task l's at L Suno V>73--1 Taz7
1 Execution Axis 4-- Task 7Z's iD permission S--1 Task Z Kaa)'L'S Eighth 1--1
Task z/) Actual f deat°゛1st 7-11 iDk u θ −11 Taz74t A1-Lzha”27da ---
Tazufusa Travelogue AtoLS 1 ■ Funeral 2

Claims (1)

【特許請求の範囲】[Claims] ROMシステムのプログラムモニタ(以下モニタとする
)によるタスク切り替えにおいて、該タスクのプログラ
ムが格納されているアドレスバンクを示すテーブルを持
ち、該タスクを起動する際に、上記のアドレスバンクを
示すテーブルを参照し、該タスクのプログラムを内蔵す
るアドレスバンクに切り替える手段を含むことを特徴と
するプログラムモニタ。
When switching tasks using the ROM system's program monitor (hereinafter referred to as the monitor), it has a table that shows the address bank where the program for the task is stored, and when starting the task, refers to the table that shows the address bank mentioned above. A program monitor comprising means for switching to an address bank containing a program for the task.
JP22611989A 1989-08-30 1989-08-30 Program monitor Pending JPH0387934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22611989A JPH0387934A (en) 1989-08-30 1989-08-30 Program monitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22611989A JPH0387934A (en) 1989-08-30 1989-08-30 Program monitor

Publications (1)

Publication Number Publication Date
JPH0387934A true JPH0387934A (en) 1991-04-12

Family

ID=16840138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22611989A Pending JPH0387934A (en) 1989-08-30 1989-08-30 Program monitor

Country Status (1)

Country Link
JP (1) JPH0387934A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8000627B2 (en) 2004-03-11 2011-08-16 Ricoh Company, Ltd. Charging device, process cartridge, image forming apparatus, and toner

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8000627B2 (en) 2004-03-11 2011-08-16 Ricoh Company, Ltd. Charging device, process cartridge, image forming apparatus, and toner

Similar Documents

Publication Publication Date Title
JPH02201653A (en) Application program interface method
CA2082070A1 (en) Branch resolution via backward symbolic execution
Kolaskar et al. Sequence alignment approach to pick up conformationally similar protein fragments
JP2005322232A (en) System and method about transfer of task
JPH0387934A (en) Program monitor
JPH01273136A (en) System for converting operating system to firmware
JPH06222916A (en) On-line real-time processor
KR970007277B1 (en) Communication apparatus and its method between multiprocessors which are in master-slave relationship
JPH01259430A (en) Subtracting method for interval timer value
JPH02110739A (en) Central processing unit for multi-task
JPS59180744A (en) System for managing working area of reentrant program
JPH0398128A (en) Serial number control system
JPH05216649A (en) Dynamic changing system for system program
JPS63276655A (en) Increasing system for peripheral equipment of non-stop computer system
JPH03231334A (en) Task switching control system
JPS601657B2 (en) Address conversion method
CN114334008A (en) FPGA-based gene sequencing accelerated comparison method and device
JPH02257232A (en) Interruption processing program managing method
JPH01188957A (en) Program exception processing system
JPH0194469A (en) Parallel processing system
JPH01263728A (en) Microprocessor equipped with relative instructable register group
JPH04172551A (en) Information processor
JPH02253337A (en) Memory control system for internal table of linkage editor
JPH01123357A (en) Interruption control system
JPH0210436A (en) Save processing system