JPH01123357A - Interruption control system - Google Patents

Abstract

PURPOSE:To shorten a time required for an interruption processing by generating interruption after saving the interruption until a sub CPU is operated by an interruption control circuit, or after starting up the sub CPU by the interruption control circuit in case of taking place the interruption of the sub CPU. CONSTITUTION:In the interruption processed by a main CPU101, the sub CPU102 in operating accepts the interruption, and the main CPU101 is started up by hardware which controls the interruption, and also, an interruption signal is generated again, and the interruption is applied again on the main CPU101 which executes the interruption processing via an interruption controller 103. In the interruption processed by the sub CPU102, the sub CPU102 is started up by the hardware which controls the interruption, and also (the operation of the main CPU101 is interrupted), the interruption signal is generated, and the interruption is applied again on the CPU102 which executes the interruption processing. In such a way, it is possible to shorten the time required for the interruption processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt processing method in a system having a dual CPU configuration.

[Conventional technology]

Conventionally, in dual-CPU systems where the main CPU and sub-CPU did not operate at the same time and CPU switching was possible from either CPU, it was possible to switch between CPUs while one CPU was operating. When an interrupt occurs, the CPU that accepted the interrupt processes the interrupt in the following way:
It informed U that an interrupt had occurred and executed the interrupt processing. Here, the main CPU and sub CPU do not operate at the same time because they share memory, Ilo, peripheral controllers, etc.

FIG. 4 is a block diagram of this system.

In FIG. 4, 401 is a main CPU (hereinafter abbreviated as CPU (MAIN)), 402 is a sub CPU (hereinafter abbreviated as CPU (SUB)), 403 is an interrupt controller 404, main memory 405 is a system bus (hereinafter abbreviated as CPU (SUB)), (abbreviated as 5BUS) 406 is a signal in which the interrupt controller accepts an interrupt from the outside. 407 is a signal to the CPU (MAIN) indicating that an interrupt has occurred.
401 is a signal to notify the CPU (SUB) that an interrupt has occurred (hereinafter abbreviated as INTRI).
A signal to inform the interrupt controller 403 that 401 has accepted an interrupt (hereinafter abbreviated as INTAI) 410 is the CPU (MAIN)
B) A signal (hereinafter abbreviated as INTAn) that notifies the interrupt controller 403 that the interrupt controller 402 has accepted an interrupt.

In FIG. 4, interrupts controlled by an interrupt controller 403 are handled by a CPU (MAIN) 401 and interrupts handled by a CPU (S
OB) 402, so the interrupt types are: ■ CPU (MAIN
) 401 is operating, an interrupt request that is processed by the CPU (MAIN) 401 occurs ■ CPU (SUB) 402
An interrupt request to be processed by the CPU (SOB) 402 occurs while the CPU (SOB) 402 is operating.
IN) An interrupt request handled by 401 occurs ■ CP
CPU (SUB) while U (MAIN) 401 is operating
There are 45 ways in which interrupt requests can be generated to be processed by 402.

If an interrupt request to be processed by the running CPU occurs (■ or ■), the running CPU will accept the interrupt and promptly process the interrupt.

On the other hand, in the case of (1) or (2) where the CPU that accepts interrupts during operation and the CPU that processes the generated interrupts are different, the interrupt processing is performed in the following manner. ■
Since the processing methods for and ■ are the same, only ■ will be explained here. CPU (MAIN) 401
OB) 402, CPU (SOB) 402 to CPU
(MAIN) By replacing it with 401, the process of ■ becomes possible.

When an interrupt occurs during the operation of the CPU (SOB) 402, the interrupt controller 403 sends lNTRI407 and lNTRI407 signals.

CPU (SOB) 402 is operating, so CP
U(SUB) 402 receives signal lNTR11408 and interrupts the process being executed.

When the CPU (SUB) 402 accepts an interrupt, it
The NTA II 410 notifies the interrupt controller 403 that the interrupt has been accepted.

The separation controller 403 is a system bus 405 which is a general term for address bus, data bus, and control bus.
The interrupt number is sent to the CPU through.

CPU (SOB) that accepted the interrupt 402 is 5B
It obtains the interrupt number through US 405, transfers control to the interrupt handler, and stores information regarding the interrupt in main memory 404. Then, control is transferred to the CPU (MAIN) 401, which should actually process the interrupt. At this time, the CPU (SOB) 402 is in the middle of an interrupt handler.

The CPU (MAIN) 401 to which control has been transferred reads information regarding the interrupt from the main memory 404 and issues an internal interrupt using software.

When the interrupt processing by the CPU (MAIN) 401 is completed, the CPU (MAIN) 401 writes in the main memory 404 that the interrupt processing has been completed, and returns control to the CPU (SOB) 402.

The CPU (SOB) 402 that has returned control returns to the program that was interrupted by the interrupt handler and resumes execution of the interrupted program.

FIG. 5 shows the operation at this time.

This figure shows that the execution path from accepting an interrupt to the end of the actual interrupt processing is long, and that the maximum execution speed is not achieved because information about the interrupt is passed through software.

[Problem that the invention seeks to solve]

The above method has the following drawbacks.

In addition to the long bus from interrupt acceptance to the actual completion of interrupt processing, processing such as storing and reading interrupt information and generating interrupts is performed by software.
Execution time becomes longer.

In addition, information regarding interrupts can be sent to the main CPU and sub CPU.
Since it is stored in memory shared by U, it is also necessary to protect that memory part.

[Differences between the invention and the prior art]

Conventionally, in a system with a dual CPU configuration that shares memory, Ilo, and peripheral controllers, when the CPU that accepted the interrupt and the CPU that executed the interrupt processing were different, the CPU that accepted the interrupt
The U transmits interrupt information via shared memory to the CPU that executes the interrupt, and the CPU that executes the interrupt process generates an internal interrupt and executes the interrupt process.

In the present invention, if the CPU5 in operation when an interrupt occurs is different from the CPU that executes the interrupt processing, the main CPU
If the interrupt is handled by
Wakes up the PU and generates an interrupt signal again,
An interrupt is issued again to the main CPU that executes the interrupt processing via the interrupt controller 1=-, and if the interrupt is handled by the sub CPU, the interrupt is evacuated by the interrupt control circuit until the sub CPU starts operating. Another difference from the conventional method is that after the sub CPU is started up by the interrupt control circuit, an interrupt signal is generated, and the sub CPU that executes the interrupt processing is again interrupted via the interrupt controller.

[Means for solving problems]

Dual C, where two CPUs do not work at the same time
A system having a PU configuration includes a circuit that controls an interrupt by inputting an interrupt signal from an external factor and outputting an interrupt signal to an interrupt controller.

At this time, if the CPU that is operating when the interrupt occurs and the CPU that executes the interrupt processing are different, the following processing is performed respectively.

CPU that executes interrupt processing while the sub CPU is running
If it is the main CPU, the interrupt control circuit sends an interrupt signal to the interrupt controller. The operating sub-CPU accepts the interrupt via the interrupt controller, notifies the interrupt control circuit of the acceptance of the interrupt and the interrupt number, and ends the interrupt processing. The interrupt control circuit obtains the interrupt number, sends the same interrupt signal again to the interrupt controller, and wakes up the main CPU that executes the interrupt. The main CPU, which executes the interrupt, receives the interrupt generated by the interrupt generation circuit via the interrupt controller, and processes the interrupt.

CPU that executes interrupt processing while the main CPU is running
If U is a sub CPU, the interrupt control circuit saves the interrupt number in an internal storage area.

After that, when the sub CPU starts operating, the interrupt control circuit obtains the interrupt number saved in the internal storage area and sends the same interrupt signal to the interrupt controller again. The sub CPU receives interrupts generated during the operation of the main CPU via an interrupt controller, and processes the interrupts.

〔Example〕

The present invention will be explained using the drawings.

FIG. 1 is a block diagram showing a system with a dual CPU configuration in an embodiment of the present invention.

In FIG. 1, 101 is a main CPU (hereinafter abbreviated as CPU (MAIN)), 102 is a sub CPU (hereinafter abbreviated as CPU (SOB)), and 103 is an interrupt controller 104 that is a system bus (hereinafter abbreviated as 5BUS). ) 105 indicates that an interrupt has occurred to the CPU (MAIN).
101 is a signal that informs the CPU (SOB) that an interrupt has occurred (hereinafter abbreviated as INTRI).
A signal that informs the interrupt controller 103 that I01 has accepted an interrupt (hereinafter abbreviated as INTRn) 107 is a signal that informs the interrupt controller 103 that l01 has accepted an interrupt (hereinafter abbreviated as INTAI);
A signal (hereinafter referred to as INTAI) that informs the interrupt controller 103 that OB) 102 has accepted an interrupt.
Abbreviated as I. ) 109 is a signal that informs INTHWI 11 of the status of CPU (MAIN) 101 (hereinafter referred to as
It is abbreviated as STI. ) 110 is the CPU (SUB).
THWI l 1 (hereinafter abbreviated as ST■) 111 is an interrupt signal 114 from an external factor as an input.
・CPU (MAIIIF) 101 and CPU (SUB)
Signal 5T1109 indicating the status of 102 and STI
[110・C indicating that the CPU (SOB) 102 has accepted the interrupt processed by the CPU (MAIN) 101
A signal 116 from the P U (SUB) 102 and the CPU (SO
B) bus 117 from 102, as output a signal 115.C which causes an interrupt to be generated to the interrupt controller.
Hardware (hereinafter referred to as I
It is abbreviated as NTHW. ) 112 indicates that the CPU that executes interrupt processing is CPU (MA
IN) 101 or CPU (SUB) 102, as many flags as there are interrupt numbers.
A flag 113 in NTHWI 11 stores the interrupt number. A storage area inside INTHW (hereinafter abbreviated as INTNO). A signal 114 indicates that INTHWII accepts an interrupt from an external interrupt source. A signal 115 indicates an interrupt generated by INTHWI 11. The signal 116 conveyed to the interrupt controller is
B) 102 is the interrupt controller 103 to CP
U (MAIN) A signal that informs INTHWLII that 101 has accepted an interrupt to be processed (hereinafter referred to as R
It is abbreviated as INT. ) 117 is the CPU (SOB) CP accepted by 102
U (MAYN) 101 informs INTHWI 11 of the interrupt number of the interrupt to be processed. Bus 118 is connected from INTHWI 11 to CPU (MAIN)
This is a signal to wake up 101.

First, the configuration of the system in this embodiment will be shown using FIG. This embodiment employs a dual CPU configuration that shares memory, Ilo, and peripheral controllers, with CPU (MAIN) 101 and CPU (SOB) 1.
02 never operate at the same time. In addition, CPU (MA
IN) 101 and CPU (SOB) 102 can be switched from either CPU using an external signal.

Interrupts generated by the interrupt signal 114 from an external factor can be classified into interrupts processed by the CPU (MAIN) 101 and interrupts processed by the CPU (SUB) 102. Therefore, there are the following four types of interrupts.

■ CPU (MAIN) During operation of 101, CPU' (
MAIN) An interrupt request to be processed by 101 occurs.■
CPU (SOB) 102 in operation E CPU (S
An interrupt request to be processed by the CPU (SUB) 102 occurs.
AIN) l An interrupt request is generated to be handled by O1■
While the CPU (MAIN) 101 is operating, the CPU (SO
B) When an interrupt request is processed by 102, the process of interrupt processing will be explained using FIG.

In the case of ■ or ■ where an interrupt request to be processed by the operating CPU occurs, when the interrupt signal 114 from an external factor is input to INTHWI 11, INTHWI 1
1 is CPU (MAIN) 101 and CPU (SOB)
It obtains the status of 102 from signals 109 and 110, refers to flag 112, and determines that the operating CPU and the CPU processing the interrupt are the same. After that, a signal indicating the same interrupt provision as the interrupt signal 114 is sent to the signal 115.
to the interrupt controller. After that, interrupt processing is performed using the normal bus.

This embodiment differs from the conventional example when the operating CPU and the CPU that processes the generated interrupt are different, as in (1) and (2).

First, the processing process in case (2) will be explained.

Assume that an interrupt due to an external factor occurs while the CPU (SUB) 102 is operating. Interrupt signal is INT
It is input to HWI 11. INTHWllll is CPU
Obtain the status of (MAIN) 101 and CPU (SOB) 102 from signal 109 and signal 110, and set flag 1.
12, the operating CPU is CPU (SOB)
102, and the CPU that processes the interrupt is the CPU (M
AIN) is determined to be 101.

INTHWI 11 inputs a signal through signal 115 indicating the same interrupt as interrupt signal 114 to the interrupt controller.

Interrupt controller 103 connects lNTR1105 and IN
CP indicates that an interrupt has occurred through TRn106.
U (MAIN) 101 and CPU C3lJB) 10
Let 2 know.

Since the CPU (SOB) 102 is in operation, the CPU (SOB)
) 102 accepts the interrupt. The CPU (SUB) 102 that accepted the interrupt notifies the interrupt controller 103 of the acceptance of the interrupt through the confirmation signal INTAI[108.

Interrupt controller 103 receives INTA■108
is a generic name for address bus, data bus, and control bus.
Inform U (SOB) 102.

The CPU (SOB) 102 transfers control to the interrupt handler corresponding to the interrupt number.

The interrupt handler notifies CPU (SOB) 102 that it has accepted the interrupt through RINT 116, and also sends the interrupt number through bus 117 to INTHWIII.
and finishes interrupt processing.

INTHWI 11 receives a signal 116 indicating acceptance of an interrupt from CPU (SOB) 102 and an interrupt number from bus 117, and stores the interrupt number in INTNO 113. After that, TNO11 with 1
A signal 115 indicating the same interrupt as the interrupt number stored in 3 is sent to the interrupt controller 103, and
A signal 118 that causes CPU (MAIN) 101 is sent to the CPU.
Send to (MAIN) 101.

When control is transferred to CPU (MAIN) 101, INTH
An interrupt sent by W through signal 115 occurs and CP
U(MAIN) 101 receives the interrupt and sends a confirmation signal INTHW 107 to the interrupt controller. The controller 103 receives the signal and transmits the interrupt number to the CPU (MAIN) 1 through the 5BUS 104.
Tell 01. The CPU (MAIN) 101 transfers control to the interrupt handler corresponding to the interrupt number and performs interrupt processing.

After completing the interrupt processing, the CPU (MAIN) 101
Return from the interrupt handler and transfer control to the CPU if necessary.
(StlB) Move to 102.

Next, the process for case (2) will be explained.

It is assumed that an interrupt due to an external factor occurs during the operation of the CPU (MAIN) 101. Interrupt signal is INTH
Input to WI 11. INTHWllll is CPU (
The status of MAIN) 101 and CPU (SOB) 102 is obtained from signal 109 and signal 110, and flag 11 is
2, the operating CPU is CPU (MAIN) 1
01, and the CPU that handles the interrupt is the CPU (SO
B) It is determined that it is 102. These interrupts are necessary only for controlling the CPU (SOB) 102 and do not affect the control of the CPU (MAIN) 101, so until the CPU (SUB) 102 starts operating,
does not process.

INTHWI 11 saves the interrupt number corresponding to signal 114 in internal storage area INTNOI 13. Then, if the signal 110 indicating the status of the CPU (SOB) 102 indicates that the CPU (SUB) 102 is in operation, a signal 115 indicating the interrupt saved in the internal storage area is input to the interrupt controller. .

The interrupt controller 103 has lNTR1105 and lN
TR1105 The CPU (
MAIN) 101 and CPU (SUB) 102 are notified.

Since CPU (SUB) 102 is in operation, CPU (SUB)
OB) l O2 accepts the interrupt. The CPU (SOB) 102 that has accepted the interrupt notifies the interrupt controller 103 through the INTA II 108 that the interrupt has been accepted.

Interrupt controller 10 receives INTAI[108
3 is address bus, data bus, control bus Q
The interrupt number is transmitted through the generic name 5BUS 104.
Inform PU (SOB) 102.

The CPU (SUB) 102 transfers control to the interrupt handler corresponding to the interrupt number and performs interrupt processing.

After completing the interrupt processing, the CPU (SOB) 102 returns from the interrupt handler.

Interrupt processing is performed through the process described above. Figures 2 (A) and 2 (B) show how the system operates at this time. Figure 2 (A) shows the CP
CPU (MAIN) during operation of U (StlB) 102
In the case of ■ when an interrupt request to be processed by the CPU 101 occurs, FIG.
(SUB) The operation in the case (2) in which an interrupt request to be processed by 102 occurs is shown. As can be seen from these figures, in this embodiment, when the operating CPU when an interrupt occurs and the CPU that executes the interrupt processing are different, when the interrupt is handled by the main CPU, the sub CPU that is operating handles the interrupt. The hardware that accepts and controls interrupts wakes up the main CPU, generates an interrupt signal again, sends an interrupt to the main CPU that executes the interrupt processing again via the interrupt controller, and when the interrupt is handled by the sub CPU, ,
The hardware that controls the interrupt saves the interrupt number in an internal storage area until the sub CPU starts operating. Once the sub CPU starts operating, the hardware that controls the interrupt generates an interrupt signal and sends it to the sub CPU that executes the interrupt processing via the interrupt controller. By using a method of interrupting the CPU again, the time required to execute interrupt processing can be shortened.

[Example 2] Next, a second embodiment of the present invention will be described.

In the first embodiment described above, in a dual-configuration system in which two CPUs do not operate at the same time, when an interrupt occurs, the CPU that is currently operating and the CPU that processes the interrupt are connected to each other.
One method of interrupt control when PUs are different has been described.

The present invention also relates to the following method of interrupt control in a system with a dual CPU configuration in which two CPUs do not operate at the same time, when the CPU that is operating when an interrupt occurs and the CPU that processes the interrupt are different. Applicable.

A second embodiment will be described using the drawings.

FIG. 3 is a block diagram showing a system with a dual CPU configuration in an embodiment of the present invention.

In Fig. 3, 301 is the main CPU (hereinafter abbreviated as CPU (MAIN)), 302 is a sub CPU (hereinafter abbreviated as CPU (SOB)), 303 is an interrupt controller 304 is a system bus (hereinafter abbreviated as 5BUS). ) 305 indicates that an interrupt has occurred to the CPU (MAjN).
316 is a signal that informs the CPU (SOB) that an interrupt has occurred.
302 is a signal to inform the interrupt controller 303 (hereinafter abbreviated as INTRII) 307 is a CPU (MAIN) signal that informs the interrupt controller 303 that 301 has accepted an interrupt (hereinafter abbreviated as INTAI) 308 is a CPU (S
A signal (hereinafter referred to as INTAI) that informs the interrupt controller 303 that the interrupt controller 302 has accepted the interrupt.
Abbreviated as I. )309 is a signal that informs INTHW311 of the status of CPUQfAIN)301 (hereinafter referred to as S
It is abbreviated as TI. ) 310 is the CPU (SUB) 302 status is IN
A signal that informs the THW 311 (hereinafter abbreviated as ST■) 311 receives an interrupt signal 314 from an external factor as an input.
・CPU (MAIN) 301 and CPU (SOB) 3
Signal 5TI309 indicating the status of 02 and STI[3
10・CP indicating that the CPU (SOB) 302 accepts the interrupt processed by the CPU (MAIN) 301
CPU (SOB) for notifying the signal 316 from U (SOB) 302 and the interrupt number of the interrupt.
Bus 317 from 302, as output a signal 315.CP which generates an interrupt to the interrupt controller.
U (MAIN) Signal 318・C to wake up 301
Hardware (hereinafter referred to as INT
It is abbreviated as HW. ) 312 is a CPU that executes interrupt processing. J'-
CPU (MAIN) Is it 301?
B) The flag 313 in INTHW311, which is a flag indicating whether the interrupt number is 302, is the flag 313 in INTHW311 that stores the interrupt number.
1 internal storage area (hereinafter abbreviated as INTNO) 314 is a signal in which INTHW 311 accepts an interrupt from an external interrupt source 315 is INT, signal 316) which transmits an interrupt generated by HW 311 to the interrupt controller
UB) 302 from interrupt controller 5303 to CP
U (MAIN) 301 has accepted an interrupt that should be handled and CPU (SOB) 302 has received an interrupt that should be handled by CPU (SOB).
MAIN) 301 (7) A signal that informs the INTHW 311 that the interrupt processing for an interrupt that occurred during operation has been completed (hereinafter abbreviated as RINT) 317 is the CPU (SOB) 302 receives the signal
A bus 318 that informs the INTHW 311 of the interrupt number of the interrupt to be processed by the (MAIN) 301 is connected to the CPU (MAIN) 3 from the INTHW 311.
The signal 319 to wake up 01 is sent from the INTHW 311 to the CPU (SOB)
This is a signal to wake up 302.

First, the configuration of the system in this embodiment will be shown using FIG. This embodiment employs a dual CPU configuration that shares the memory I10 and peripheral controller, and the CPU (MAIN) and CPU (SUB) 302 do not operate at the same time. Also, CPU (MAIN)
301 and CPU (SOB) 302 can be switched from either CPU using an external signal.

Interrupts generated by interrupt signals 314 from external factors can be classified into interrupts processed by the CPU (MAIN) 301 and interrupts processed by the CPU (SOB) 302. Therefore, there are the following four types of interrupts.

■ CPU (MAIN) While the 301 is operating, the CPU (MAIN)
AIN) An interrupt request to be processed by 301 occurs ■ C
While the CPU (SOB) 302 is operating, the CPU (SOB)
) 302 occurs. ■ CPU (SOB) While the CPU (SOB) 302 is operating, the CPU (MA
IN) An interrupt request to be processed by 301 occurs ■ CP
CPU (SOB) while U (MAIN) 301 is operating
The process of interrupt processing will be explained using FIG. 3 for how the interrupt request processed by 302 is generated.

In the case of ■ or ■ where an interrupt request to be processed by the operating CPU occurs, when an interrupt signal 314 from an external factor is input to the INTHW 311, the INTHW 311 interrupts the CPU (MAIN) 301 and the CPU (SOB) 30.
It obtains the status of 2 from the signals 309 and 310, refers to the flag 312, and determines that the operating CPU and the CPU processing the interrupt are the same. Thereafter, a signal indicating the same interrupt as the interrupt signal 314 is input to the interrupt controller through a signal 315. After that, interrupt processing is performed using the normal bus.

This embodiment differs from the conventional example when the operating CPU and the CPU that processes the generated interrupt are different, as in (1) and (2).

First, the processing process in case (2) will be explained.

Assume that an interrupt due to an external factor occurs while the CPU (SUB) 302 is operating. Interrupt signal is INTH
It is input to W311. INTHW311 is CPU (M
The status of AIN) 301 and CP'U (SUB) 302 is obtained from the signal 309 and signal 310, and the flag 312 is
Refer to , the operating CPU is CPU (SOB) 302
, and the CPU that handles the interrupt is the CPU (MAI
N) It is determined that it is 301.

INTHW 311 inputs a signal indicating the same interrupt as interrupt signal 314 to the interrupt controller through signal 315.

Interrupt controller 303 is connected to I NTRl 305 and I
The CPU (MAIN) 301 and CPU (SOB) 30 indicate that an interrupt has occurred through the NTRII 306.
Let 2 know.

Since CPU (SOB) 302 is in operation, CPU (SOB)
B) 302 accepts the interrupt. The CPU (SOB) 302 that has accepted the interrupt notifies the interrupt controller 303 through a confirmation signal INTA II 308 that it has accepted the interrupt.

Interrupt controller 3 that accepted INTΔ■308
03 transmits interrupt numbers to C through 5BUS304, which is a generic name for address bus, data bus, and control bus.
Inform PU (SOB) 302.

The CPU (SOB) 302 transfers control to the interrupt handler corresponding to that interrupt number.

The interrupt handler notifies the CPU (SOB) 302 that the interrupt has been accepted through the RINT 316, and also sends the interrupt number to the INTHW 311 through the bus 317.
and finishes interrupt processing.

INTHW 311 receives a signal 316 indicating that it has accepted an interrupt from CPU (SOB) 302 and bus 3.
Receive the interrupt number from 17 and enter the interrupt number as I.
Store in NTNO313. After that, INTN○313
Signal 3 indicating the same interrupt as the interrupt number stored in
15 to the interrupt controller 303, and also sends C
The signal 318 that wakes up the PU (MAIN) 301 is sent to the CPU (
MAIN) 301.

When control is transferred to CPU (MAIN) 301, INTH
An interrupt sent by W311 through signal 315 occurs, CPU (MAIN) 301 receives the interrupt, and sends a confirmation signal to the interrupt controller.
Send 7. The interrupt controller 303 receives the signal and sends the interrupt number to the CPU (
MAIN) Tell 301. CPU (MAIN) 3
01 transfers control to the interrupt handler corresponding to that interrupt number and performs interrupt processing.

After completing the interrupt processing, the CPU (MAIN) 301
Return from the interrupt handler and transfer control to the CPU (
SUB) Move to 302.

Next, the process for case (2) will be explained.

Assume that an interrupt due to an external factor occurs while the CPU (MAIN) 301 is operating. Interrupt signal is INT
It is input to HW311. INTHW311 is CPU (
The status of MAIN) 301 and CPU (SUB) 302 is obtained from the signal 309 and signal 310, and the flag 31 is
2, the operating CPU is CPU (MAIN) 3
01, and the CPU that handles the interrupt is CPU (SU
B) It is determined that it is 302. These interrupts are
It is necessary only for controlling the CPU (SOB) 302 and does not affect the control of the CPU (MAIN) 301.

INTHW 311 saves the interrupt number corresponding to signal 314 in internal storage area NTNO 313. after that,
A signal 315 indicating the same interrupt as the interrupt number stored in the INTNO 313 is sent to the interrupt controller 303, and a signal 319 to wake up the CPU (SOB) 302 is sent to the CPU (SOB) 302. CPU (S
When UB) 302 operates, CPU (MAIN) 3
01 interrupts the process being executed.

When control is transferred to the CPU (SOB) 302, I NTE
An interrupt sent by IW311 through signal 315 occurs, CPU (StlB) 302 receives the interrupt, and sends a confirmation signal INTA113 to the interrupt controller.
Send 08. The interrupt controller 303 receives the signal and sends the interrupt number to the CPU through the 5BUS 304.
(SUB) Tell 302. CPU (SOB) 30
2 transfers control to the interrupt handler corresponding to the interrupt number and performs interrupt processing.

After completing the interrupt processing, the CPU (StlB) 302
Upon returning from the interrupt handler, a signal 316 indicates that the CPU (MAIN) that occurred during the operation of the CPU (MAIN) 301
(SOB) Notifies the INTHW 311 that the interrupt processing for the interrupt handled by the 302 has finished.

Upon receiving the signal 316, the INTHW 311 executes the CPU (
The signal 318 that causes MAIN) 3 o 1 is sent to the CPU (
MAIN) Send to 301. CPU (MAIN) 30
1 receives the signal 301 and resumes the interrupted process.

Interrupt processing is performed through the process described above. In this embodiment, if the operating CPU when an interrupt occurs and the CPU that executes the interrupt processing are different, when the interrupt is handled by the main CPU, the sub CPU in operation accepts the interrupt, and the interrupt is processed by the hardware that controls the interrupt. Wake up the main CPU, generate an interrupt signal again, and issue another interrupt to the main CPU that executes the interrupt processing via the interrupt controller.If the interrupt is handled by the sub CPU,
Depending on the hardware that controls interrupts, the sub-CPU
At the same time as starting up (main CPU operation is suspended),
By generating an interrupt signal and re-interrupting the sub-CPU that executes the interrupt process via the interrupt controller, the time required to execute the interrupt process can be reduced.

〔Effect of the invention〕

As explained above, in a system with a dual CPU configuration in which two CPUs do not operate at the same time, when the CPU operating at the time of an interrupt and the CPU executing interrupt processing are different, (A
), as can be seen from the system operation diagram shown in Figure 2(B), interrupts are not passed by software immediately after the interrupt occurs, but are transferred to the main CPU.
If U is an interrupt that should be handled, the interrupt control circuit will generate an interrupt again,
In the case of an interrupt to the sub CPU, the time required for interrupt processing can be reduced by generating an interrupt after the interrupt control circuit has evacuated the interrupt until the sub CPU is activated, or after the interrupt control circuit has started up the sub CPU. Can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a system with a dual CPU configuration in an embodiment of the present invention. FIG. 2 is a diagram showing the operation of the system in the embodiment of the present invention. Figure 2 (A) shows that when an interrupt request to be processed by the main CPU occurs while the sub CPU is operating, Figure 2 (B) shows that the interrupt request to be processed by the main CPU occurs while the sub CPU is operating. The diagram shows the operation when an interrupt request occurs. FIG. 3 shows a dual CP in a second embodiment of the present invention.
FIG. 1 is a block diagram showing a system with a U configuration. FIG. 4 is a block diagram showing a conventional system with a dual CPU configuration. FIG. 5 is a diagram showing the operation of the system in the conventional example. Agent Patent Attorney Susumu Uchihara $3 41! I

Claims (1)

[Claims] In an information processing device with a dual CPU configuration, there are two processors, a first processor and a second processor, which are switchable and do not operate simultaneously, an interrupt controller that controls interrupts from the outside, and an interrupt controller that controls interrupts generated from the outside. an interrupt control circuit having an internal storage area for storing a flag and an interrupt number indicating which of the first processor and the second processor handles the interrupt; When an interrupt handled by the first processor occurs, the interrupt control circuit refers to the internal flag and sends an interrupt signal to the interrupt controller, and the second processor receives the interrupt signal from the interrupt controller. The processor transmits a signal indicating that the interrupt has been accepted and an interrupt number to the interrupt control circuit, and upon receiving them, the interrupt control circuit transmits an interrupt signal indicating the same interrupt as the interrupt accepted from the outside by the second processor. The interrupt controller sends the interrupt to the interrupt controller and transfers control to the first processor, and the interrupt controller generates the same interrupt as the interrupt accepted by the second processor to the first processor that issues the interrupt, and If an interrupt to be processed by the second processor occurs while the first processor is operating, the interrupt control circuit refers to the internal flag. , after the interrupt is evacuated until the sub-CPU is activated or after the sub-CPU is started up, the second CPU sends an interrupt signal to the interrupt controller, and receives the interrupt signal from the interrupt controller. An interrupt control method characterized by having a processor handle interrupt processing.