JPH0382055A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make finer element regions, improve withstand voltage of a gate oxide film, improve carrier life and obtain higher speed by forming an element separating region from a first insulating film provided selectively, an electrically conductive film provided directly above it to which a fixed voltage is applied, and a second insulating film provided on their side surfaces. CONSTITUTION:An element separating region is formed from a first insulating film 4 provided selectively, an electrically conductive film 5 provided directly above it to which a fixed voltage is applied, and a second insulating film 6 provided on the side surfaces of the first insulating film 4 and the conductive film 5. For example, the first insulating film 4 and the conductive film 5 are selectively provided on a p-type silicon substrate 1, and the second insulating film 6 is provided on the side surfaces of the first insulating film 4 and the conductive film 5 by RIE process in self-aligning manner to form the element separating region from the first insulating film 4, the conductive film 5 and the second insulating film 6. The fixed voltage, which does not provide field inversion, is applied to the conductible film 5 and a channel stopper region is not formed.

Description

[Detailed Description of the Invention] [Summary] An element isolation region provided on a semiconductor substrate includes a first insulating film selectively provided, and a fixed voltage provided directly above the first insulating film. The conductive film has a structure formed by a given conductive film, the first insulating film, and a second insulating film provided in a self-line by an RIE (reactive ion etching) method on the sidewall of the conductive film. Therefore, miniaturization of the device area, improvement of gate oxide film breakdown voltage, and improvement of carrier life by forming a structure without bird's beak can be achieved by forming a second insulating film on the sidewall of the step between the first insulating film and the conductive film. It is possible to form wiring bodies with good step coverage by reducing the stress, increase speed by reducing the junction capacitance by not forming a channel stopper region or forming it separated from the source and drain regions, and improve functionality by increasing the junction breakdown voltage. The semiconductor device that made this possible.

[Industrial Application Field] The present invention relates to an MIS type semiconductor device, and more particularly to a semiconductor device that enables the formation of a highly integrated semiconductor integrated circuit having an element isolation region with reduced leakage and no bird's beak.

Conventionally, the formation of element isolation regions in semiconductor integrated circuits has been carried out using LOC.
This has been done by forming a field oxide film using the O8 method and forming a channel stopper region using a self-line under the field oxide film, but in today's world where the degree of integration is increasing significantly, the LOCOS method inevitably induces stress. Bird's beaks make it difficult to miniaturize the device formation region, deteriorate the withstand voltage of a thinned gate oxide film, shorten the lifespan due to easy trapping of electrons or holes, or cause problems in the highly concentrated channel stopper region and source/drain region. Problems such as an increase in junction capacitance due to contact and a deterioration of junction breakdown voltage are becoming more prominent, and these problems are becoming a hindrance to higher integration. Therefore, there is a need for a means that can realize highly integrated device isolation without bird's beak and without deterioration of device characteristics.

[Prior Art] FIG. 5 is a schematic side sectional view of a conventional semiconductor device. 51
52 is a p-type silicon (Si) substrate, 52 is a p-type well region, 53 is a p-type channel stopper region, 54 is a field oxide film, 55 is an n-type source drain region, 56 is a gate oxide film, and 57 is a gate electrode. , 58 is a block oxide film, 59 is a phosphosilicate glass (PSG) film, and 60 is an A1 wiring.

In the figure, a p-type well region 52 is selectively provided on a p-type silicon (Si) substrate 51, and an N-channel transistor is selectively formed in the p-type well region 52. The element isolation region is constructed by forming a field oxide film by selective oxidation using a nitride film, the so-called LOCO8 method, and forming a channel stopper region by self-alignment under the field oxide film, and there is a bird's beak with inherent stress. are doing. The LOCO8 method has the advantage that the step difference in the element isolation region can be alleviated by the bird's beak, and a wiring body with good step coverage can be formed.However, the existence of the bird's beak makes it difficult to miniaturize the element forming region.
There are disadvantages such as the breakdown voltage of the thinned gate oxide film deteriorates and the lifetime deteriorates due to easy trapping of electrons or holes. In addition, due to the formation of the channel stopper region by self-alignment under the field oxide film, the source/drain region is always in contact with the channel stopper region, which increases the junction capacitance, making it difficult to increase the speed, and reducing the junction breakdown voltage. There are also drawbacks, such as the fact that it is difficult to improve functionality to enable high-voltage driving because of deterioration.

[Problems to be Solved by the Invention] The problems to be solved by the present invention are that, as shown in the conventional example, it is difficult to miniaturize the element formation region due to the presence of bird's beaks in the LOCO8 method, and it is difficult to reduce the thickness of the film. It was not possible to improve the problems such as deterioration of the withstand voltage of the gate oxide film, deterioration of the lifetime due to easy trapping of electrons or holes, and increase in junction capacitance due to contact between the source drain region and the channel stopper region. This made it difficult to increase the speed, but it was difficult to increase the functionality to enable high voltage drive because the junction breakdown voltage deteriorated.

[Means for solving the problem] The above problem is solved by a first insulating film selectively provided on a semiconductor substrate, and a conductive film provided directly above the first insulating film to which a fixed voltage is applied. The problem is solved by the semiconductor device of the present invention, in which an element isolation region is formed by a film, the first insulating film, and a second insulating film provided on the sidewall of the conductive film.

[Function] That is, in the semiconductor device of the present invention, the element isolation region provided on the semiconductor substrate includes a selectively provided first insulating film and a fixed region provided directly above the first insulating film. The conductive film has a structure formed by a conductive film to which a voltage is applied, the first insulating film, and a second insulating film provided in a self-line by RIE (reactive ion etching) method on the sidewall of the conductive film. ing. Therefore, since the element isolation region can be formed without using the so-called LOCO9 method by selective oxidation, that is, it can be formed in a structure without bird's beaks that cause stress, high integration can be achieved by forming fine element regions. High performance can be achieved by improving the breakdown voltage of the gate oxide film, and high reliability can be achieved by making it difficult for electrons or holes to be trapped and improving carrier life.

Further, since the step difference between the first insulating film and the conductive film can be alleviated by the second insulating film formed on the sidewall, it is possible to form a wiring body with good step coverage. Furthermore, since the channel stopper region is not formed or the channel stopper region is formed as a self-line only under the first insulating film, the source/drain region and the channel stopper region can be formed separately by the second insulating film, reducing the junction capacitance. In other words, extremely high performance, high reliability, high functionality, high speed, and highly integrated semiconductor integrated circuits can be realized. It is possible to obtain a semiconductor device that enables the formation of.

[Examples] The present invention will be specifically described below with reference to illustrated examples. FIG. 1 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention, FIG. 2 is a schematic side sectional view of the second embodiment of the semiconductor device of the present invention, and FIG. 3 is a schematic side sectional view of the semiconductor device of the present invention. A schematic side sectional view of the third embodiment of the device, FIGS. 4(a) to (
d) is a process sectional view of an embodiment of the manufacturing method of the present invention.

Identical objects are indicated by the same reference numerals throughout the figures.

FIG. 1 is a schematic side sectional view of the first embodiment of the semiconductor device of the present invention when a p-type silicon substrate is used, and 1 is 10
cm p-type silicon (Si) substrate, 2 is a p-type well region of about 10" cs-3, 3 is 1020
N-type source drain region of about C13, 4 is 0.4/
The first insulating film (field oxide film) is about I1m, 5 is 0. The field oxidized conductive film has a width of 0.
Second insulating film (side wall insulating film) of about 3I-, 7 is 20n
8 is a gate oxide film of about 300 nm, 9 is a block oxide film of about 50 nm, 10 is 0
．． A phosphosilicate glass (PSG) film of approximately 8/All, and 11 an A1 wiring of approximately 1/AI are shown.

In the figure, a p-type silicon (Si) substrate 1 is selectively provided with first insulators M, 4 and a conductive film 5.
RIE on the side walls of the first insulating WA4 and conductive 1i5
A second insulating film 6 is provided on the self-line by a (reactive ion etching) method, and the first insulating film 4
, the conductive film 5 and the second insulating film 6 form an element isolation region. A fixed voltage that does not cause field reversal is applied to the conductive film 5, and no channel stopper region is formed. An N-channel transistor is formed in the element formation region, and its threshold voltage is controlled by a lightly doped p-type well region. Therefore, since the element isolation region can be formed without using the so-called LOCO8 method using selective oxidation, in other words, it can be formed in a structure without bird's beak that causes stress, and high integration can be achieved by forming fine element regions. High performance can be achieved by improving the breakdown voltage of the gate oxide film, and high reliability can be achieved by making it difficult for electrons or holes to be trapped and improving carrier life. Further, since the step difference between the first insulating film and the conductive film can be alleviated by the second insulating film formed on the sidewall, it is possible to form a wiring body with good step coverage. Furthermore, by not forming a channel stopper region and applying a fixed voltage that does not cause field reversal to the conductive film formed on the field oxide top, it is possible to suppress the formation of a parasitic MO8 field effect transistor and prevent field leakage. Therefore, it is possible to increase the speed by reducing the source-train junction capacitance, and to increase the functionality by enabling high-voltage driving by increasing the source-drain junction breakdown voltage.

FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention, and 1 to 3.5 to 11 are the same as in FIG.
4a is an impurity-through oxide film, 4b is a borosilicate glass (BS
G) Membrane, 12 indicates the p-type channel stopper region.

In the figure, the first insulating film is an impurity-through oxide film 4.
Except for the fact that it has a laminated structure of a and a borosilicate glass (BSG) film 4b, and that boron is diffused from the borosilicate glass (BSG) film 4b through impurity through oxidation Baa to form a p-type channel stopper region 12. 40 In this example, in addition to the effect shown in Fig. 1, a p-type channel stopper region separated from the source/drain region is formed, although the manufacturing process is slightly more complicated than in Fig. 1. This makes it possible to further prevent field leaks.

FIG. 3 is a schematic side sectional view of a third embodiment of the semiconductor device of the present invention, where 1 to 11 are the same as in FIG. 1, and 13 is n.
14 indicates a p-type source/drain region.

This figure shows an embodiment in which the present invention is applied to a C-MO8 type semiconductor device, in which N-channel transistors and P-channel transistors and P-channel transistors and P-channel transistors and P-channel transistors and P-channel transistors and P-channel transistors and It shows the same structure as in Fig. 1, except that the transistors are fixed, the conductive films in each element isolation region are separated, and different fixed voltages that do not cause field reversal are applied. The same effect as shown in FIG. 1 can be obtained also in the MO3 type semiconductor device.

Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 4(a) to 4(d) and FIG. 3.

FIG. 4(a) A thin oxide film (not shown) for ion implantation is grown on the p-type silicon substrate 1 by applying a conventional technique, and then by using a conventional photolithography technique,
Using a resist (not shown) as a mask layer, boron ions are implanted to define the p-type well region 2, and phosphorus ions are implanted to selectively define the n-type well region 13. Next, by running at a high temperature, the thin oxide film for ion implantation, which forms the p-type well region 2 and the n-type well region 13 having desired depths, is removed by etching.

FIG. 4(b) Next, an oxide film and a polycrystalline silicon film are sequentially grown. Next, using a normal photolithography technique, the polycrystalline silicon film and the oxide film are sequentially etched using a resist (not shown) as a mask layer, and a field oxide film (first insulating film) forming a part of the element isolation region is etched. 4 and the conductive film 5 on the field oxide film. Next, an oxide film is grown by chemical vapor deposition. Next, the chemical vapor grown oxide film is anisotropically dry etched, and the field oxide film (first A chemical vapor grown oxide film (a second insulating film serving as a sidewall insulating film) 6 is left on the sidewalls of the field oxide film (insulating film) 4 and the conductive film 5 on the field oxide film to form an element isolation region.

FIG. 4(C) Next, a gate oxide film 7 and a polycrystalline silicon film are sequentially grown, and then the polycrystalline silicon film is patterned using a normal photolithography technique to form a gate electrode 8.

FIG. 4(d) Next, using a normal photolithography technique, a resist (not shown) and a conductive film 5 are laminated to form a first insulating layer M4.
, using the second insulation M (side wall insulation M) 6 and the gate electrode 8 as mask layers, arsenic ions are implanted to form n-type source/drain regions 3, and boron ions are implanted to form p-type source/drain regions 14. Each is selectively defined in turn.

FIG. 3 Next, unnecessary portions of the gate oxide film 8 are removed by etching.
Next, a blocking oxide film 9 and a phosphosilicate glass (PSG) film 10 are sequentially grown.Next, a slightly high temperature treatment is performed to form n-type source drain regions 3 and p-type source drain regions 14 with desired depths. Next, by applying conventional techniques, electrode contact windows, A1 wiring 11, etc. are formed, and the semiconductor device is completed.

Note that the element isolation structure of the semiconductor device of the present invention is extremely effective in manufacturing semiconductor integrated circuits for CCD imaging devices and space-related devices with enhanced radiation resistance.

As shown in the embodiments above, according to the semiconductor device of the present invention, the element isolation region is formed by selective oxidation, so-called LOCO.
, because it can be formed without using the S method, that is, it can be formed into a structure without bird's beaks that cause stress, and it is possible to achieve high integration by forming fine device regions, and by improving the breakdown voltage of the gate oxide film. Performance can be improved, and high reliability can be achieved because electrons or holes are less likely to be trapped and carrier life can be improved. Further, since the step difference between the first insulating film and the conductive film can be alleviated by the second insulating film formed on the sidewall, it is possible to form a wiring body with good step coverage. Furthermore, since the channel stopper region is not formed or the channel stopper region is formed as a self-line only under the first insulating film, the source/drain region and the channel stopper region can be formed separately by the second insulating film, reducing the junction capacitance. It is possible to increase the speed by increasing the junction voltage, and also to increase the functionality by enabling high-voltage driving by increasing the junction breakdown voltage.

[Effects of the Invention] As described above, according to the present invention, in the MIS type semiconductor device, the element isolation region provided on the semiconductor substrate is
a selectively provided first insulating film, a conductive film provided directly above the first insulating film to which a fixed voltage is applied, and a conductive film provided on sidewalls of the first insulating film and the conductive film. Since it has a structure formed by a second insulating film, it can be formed into a structure without bird's beaks, thereby achieving miniaturization of the element region, improvement of gate oxide film breakdown voltage, and improvement of carrier life. It is possible to form a wiring body with good step coverage by reducing the film step difference with the second insulating film formed on the sidewall, and to reduce the junction capacitance by not forming a channel stopper region or forming it separately from the source and drain regions. By increasing the junction breakdown voltage, high-voltage driving and high functionality can be achieved. That is, it is possible to obtain a semiconductor device that enables the formation of extremely high-performance, highly reliable, highly functional, high-speed, and highly integrated semiconductor integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention, and FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention.
FIG. 3 is a schematic side sectional view of the third embodiment of the semiconductor device of the present invention, and FIGS.
(d) is a process cross-sectional view of an embodiment of the manufacturing method of the present invention, and FIG. 5 is a schematic side cross-sectional view of a conventional semiconductor device. In the figure, 1 is a p-type silicon (Si) substrate, 2 is a p-type well region, 3 is an n-type source/drain region, 4 is a first insulating film (field oxide film), 4a is an impurity through oxide film, 4b is a borosilicate glass (BSG) film, 5 is a conductive film on the field oxide film, 6 is a second insulating film (sidewall insulating film), 7 is a gate oxide film, 8 is a gate electrode, 9 is a block oxide film, 10 is a phosphosilicate glass (PSG) film, 11 is an A1 wiring, 12 is a p-type channel stopper region, 13 is an n-type well region, and 14 is a p-type source/drain region.

Claims (3)

[Claims] (1) A first insulating film selectively provided on a semiconductor substrate, a conductive film provided directly above the first insulating film to which a fixed voltage is applied, the first insulating film, and the conductive film. A semiconductor device characterized in that an element isolation region is formed by a second insulating film provided on a side wall of the film. (2) The first insulating film has a laminated structure of an insulating film containing impurities and an insulating film not containing impurities, and
2. The semiconductor device according to claim 1, further comprising a channel stopper region provided directly under the insulating film. (3) The semiconductor device according to claim 1, wherein the conductive film is separated into islands on the n-type semiconductor substrate and on the p-type semiconductor substrate, and is applied with different fixed voltages. .