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JPH0380356B2 - - Google Patents

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Publication number
JPH0380356B2
JPH0380356B2 JP58250002A JP25000283A JPH0380356B2 JP H0380356 B2 JPH0380356 B2 JP H0380356B2 JP 58250002 A JP58250002 A JP 58250002A JP 25000283 A JP25000283 A JP 25000283A JP H0380356 B2 JPH0380356 B2 JP H0380356B2
Authority
JP
Japan
Prior art keywords
chip
voltage
temperature
land
curve
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58250002A
Other languages
Japanese (ja)
Other versions
JPS60140894A (en
Inventor
Mineo Yamagishi
Kinjiro Enomoto
Masaji Saiki
Kazuo Ozawa
Yamatake Komya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP25000283A priority Critical patent/JPS60140894A/en
Publication of JPS60140894A publication Critical patent/JPS60140894A/en
Publication of JPH0380356B2 publication Critical patent/JPH0380356B2/ja
Granted legal-status Critical Current

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】 (1) 発明の技術分野 本発明はプリント基板の表面に設けたランドと
ランド間のデイスクリートワイヤーによる接続に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a connection using discrete wires between lands provided on the surface of a printed circuit board.

(2) 技術の背景 高集積の部品を搭載する多層プリント基板の信
号の伝送のクロストークを改善し、遅延時間を調
整するために電送路線としてプリント基板の導体
パターンを用いず、所望のランド間をデイスクリ
ートワイヤーで接続するが、プリント基板のパタ
ーンの基準グリツトが50ミルである時、ランドは
0.6mm×0.6mmでランド間が約0.67mmの間隔である
ため、ランドとデイスクリートワイヤーとの接続
は、ランドの表面にメツキされた30μm厚程度の
半田層上に80μmφの銅の導線に10μm厚程度のポ
リウレタン被膜を施したデイスクリートワイヤー
を載置し、ボンダーのチツプをデイスクリートワ
イヤーの上面より接触加圧し、チツプに電圧を約
100ms間印加して加熱しポリウレタン被膜を溶融
して露出した導線と溶融した半田とを接続する。
(2) Background of the technology In order to improve signal transmission crosstalk and adjust delay time on multilayer printed circuit boards that are equipped with highly integrated components, the conductor pattern of the printed circuit board is not used as a power transmission line, and the desired distance between lands is improved. are connected with discrete wires, but when the standard grit of the printed circuit board pattern is 50 mil, the land is
Since the distance between the lands is 0.6mm x 0.6mm, the distance between the lands is approximately 0.67mm, so the connection between the lands and the discrete wires is made using a 10μm thick copper conductor wire of 80μmφ on a solder layer approximately 30μm thick plated on the surface of the land. A discrete wire coated with a thick polyurethane film is placed on the wire, and the bonder chip is contacted and pressed from the top of the discrete wire to apply approximately a voltage to the chip.
Heat is applied for 100 ms to melt the polyurethane film and connect the exposed conductive wire to the molten solder.

(3) 従来技術と問題点 第1図はプリント基板のランドと細線との接続
方法を示し、第2図は電圧の印加されたチツプの
温度上昇の曲線を示す。
(3) Prior art and problems Figure 1 shows a method of connecting a land on a printed circuit board and a thin wire, and Figure 2 shows a curve of temperature rise of a chip to which a voltage is applied.

図に於いて1はプリント基板、2はランド、3
は半田メツキ層、4はフラツクス、5は細線、6
はチツプ、7は電源をそれぞれ示す。
In the figure, 1 is a printed circuit board, 2 is a land, and 3 is a printed circuit board.
is solder plating layer, 4 is flux, 5 is thin line, 6
7 indicates a chip, and 7 indicates a power supply.

第1図に示す如く、プリント基板1の表面の50
ミルの基準グリツト上に設けられた表面積が0.6
mm×0.6mmで約30μm厚の銅箔のランド2の上面に
約30μm厚のメツキによつて半田層が形成され、
当該メツキ層の上面にフラツクス4を塗布し、導
体の直径が約80μmの銅線に約10μm厚のポリウレ
タンの被膜を施した細線5を載置し、チツプ6を
降下装置(特に図示せず)によつて接続すべきラ
ンド2と細線5の上部に接触加圧せしめたる後、
チツプ6の発熱導体(特に図示せず)に電源7よ
り約100ms間所望値の電圧を印加し、チツプ6の
接触端面の温度を約350℃に加熱せしめ、細線5
の表面のポリウレタン層を熱溶融して導体を露出
せしめたる後、加熱されたチツプ6の接触により
露出した導体を介して半田メツキ層3を熱溶融
し、フラツクス4を用いた導体とランド2とを半
田接続をなすが、この時のチツプ6の接続端の温
度上昇曲線は、チツプ6による加熱時間が約
100msと極めて短時間であるため、チツプ6を構
成する発熱体をカバーし、ランド2と細線5との
接続部に熱チツプ6の発熱を伝導する筐体は、加
熱接触をなす底面の面積が0.35mm×0.6mmで、高
さが約2mmの体積を持つ耐熱金属性で、熱容量が
小さく外気の熱影響を受けやすく、ランド2と細
線5も又微小形状であるため、周囲の温度に容易
に依存するためその相乗効果により略第2図に示
す如くY軸に温度℃、X軸に時間msをとる時、
チツプ6への通電時間に対しチツプ6の接触端の
温度は図示するA曲線の如く、常温より350℃に
上昇し、細線5のポリウレタンを上昇曲線の過程
で熱容融したる後350℃の温度領域で半田付をな
すが、周囲温度がより低温である時、チツプ6の
接触端の温度上昇はB曲線となり、温度の上昇点
は350℃に達せず、ランド2と細線5の導体の半
田接続時の温度が低温となり、半田接続が不充分
となり、周囲温度がより高温である時、チツプ6
の接触端の温度上昇はC曲線となり、温度の上昇
点は350℃以上となり、細線5のポリウレタン層
が所望長より長く熱溶融し、導体の露出長がより
長くなり約0.67mmで隣接するパターンと電気的に
接触する事故を生ずる惧れがある。
As shown in FIG.
The surface area provided on the mill reference grit is 0.6
A solder layer is formed on the top surface of the copper foil land 2 of mm×0.6 mm and approximately 30 μm thick by plating approximately 30 μm thick.
Flux 4 is applied to the top surface of the plating layer, a thin wire 5 made of a copper wire with a conductor diameter of about 80 μm coated with polyurethane about 10 μm thick is placed, and the chip 6 is placed on a lowering device (not particularly shown). After contacting and pressurizing the upper part of the land 2 and the thin wire 5 to be connected by
A voltage of a desired value is applied from the power supply 7 to the heating conductor (not particularly shown) of the chip 6 for about 100 ms to heat the contact end surface of the chip 6 to about 350°C.
After the polyurethane layer on the surface of the solder plate is thermally melted to expose the conductor, the solder plating layer 3 is thermally melted through the exposed conductor by contact with the heated chip 6, and the conductor using the flux 4 and the land 2 are bonded together. A solder connection is made, but the temperature rise curve at the connection end of chip 6 at this time shows that the heating time by chip 6 is approximately
Since the time is extremely short (100 ms), the casing that covers the heating element constituting the chip 6 and conducts the heat of the thermal chip 6 to the connection between the land 2 and the thin wire 5 has a bottom area that makes heating contact. It is made of heat-resistant metal with a volume of 0.35mm x 0.6mm and a height of approximately 2mm, and has a small heat capacity and is easily affected by the heat of the outside air.The land 2 and thin wire 5 are also minute in shape, so they are easily affected by the surrounding temperature. Due to the synergistic effect, when the Y axis is the temperature °C and the X axis is the time ms, as shown in Figure 2,
The temperature at the contact end of the chip 6 rises from room temperature to 350°C with respect to the time of energization to the chip 6, as shown by curve A shown in the figure, and after melting the polyurethane of the thin wire 5 during the rising curve, Soldering is performed in the temperature range, but when the ambient temperature is lower, the temperature rise at the contact end of the chip 6 becomes curve B, and the temperature rise point does not reach 350°C, and the temperature rise between the land 2 and the conductor of the thin wire 5 When the solder connection temperature is low, the solder connection is insufficient, and the ambient temperature is higher, chip 6
The temperature rise at the contact end becomes curve C, and the temperature rise point is 350°C or higher, and the polyurethane layer of the thin wire 5 is thermally melted for a longer length than the desired length, and the exposed length of the conductor becomes longer, and the adjacent pattern is approximately 0.67 mm apart. There is a risk of an accident resulting in electrical contact.

(4) 発明の目的 本発明は上記従来の欠点に鑑み、プリント基板
のランドとポリウレタンで被膜された細線をボン
ダーのチツプで加熱接続する時、接続作業の周囲
温度に影響されることなく確実な半田付と、ポリ
ウレタン被膜の所望の熱溶融長を得る如きボンダ
ーのチツプの加熱方法の提供を目的とするもので
ある。
(4) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention provides a method for reliably bonding the land of a printed circuit board and a thin wire coated with polyurethane using a bonder chip without being affected by the ambient temperature of the bonding operation. The object of the present invention is to provide a method for soldering and heating a bonder chip to obtain a desired thermal melting length of a polyurethane coating.

(5) 発明の構成 そしてこの目的は本発明によれば、プリント基
板の半田メツキされたランドと、ポリウレタン被
膜の施された細線の加熱圧線のためのボンダーの
チツプに対し、加熱圧接時に加熱圧接位置におい
て、電圧の印加頭初に於いて電圧を大ならしめ、
次いで、経時的に印加電圧を所定値まで降下せし
め、該所定値を一定時間保持することを特徴とす
る細線の接続方法によつて達成される。
(5) Structure of the Invention According to the present invention, the solder plated land of the printed circuit board and the chip of the bonder for the heat pressure wire of the fine wire coated with polyurethane are heated during heat pressure welding. At the pressure welding position, increase the voltage at the beginning of voltage application,
This is achieved by a thin wire connection method characterized in that the applied voltage is then lowered over time to a predetermined value and the predetermined value is maintained for a predetermined period of time.

(6) 発明の実施例 以下本発明の実施例を図面によつて詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

第3図は本発明によるボンダーの加熱チツプの
温度上昇を示し、第4図は本発明によるボンダー
の加熱チツプの温度上昇方法を示す。プリント基
板1のランド2にデイスクリートの細線5を半田
接続する時、ボンダーの加熱チツプ6の形状が小
型であり、熱容量が小さく、周囲温度の温度依存
性が大であることにより、接続の半田性と細線5
のポリウレタン被膜の過剰な熱溶融による障害を
生ずるため本発明に於いてはチツプ6の温度上昇
曲線を従来のA曲線に示す如く、チツプ6の接触
面の飽和温度の350℃の持続時間が10ms程度に対
し、D曲線に示す如く、飽和温度の持続時間を
50ms以上に保持する如くなし、実効的にチツプ
6の見掛上の熱容量を大ならしめて、チツプ6を
囲撓する外気の温度によりチツプ6の温度依存を
小ならしめ、安定な半田接続とポリウレタン被膜
の熱容融による剥離の所望長を得る如くなすもの
で、このためチツプ6の加熱体に電圧を印加する
100msの時間帯に於いて第4図に示す如く、Y軸
に印加電圧V、X軸に電圧の印加時間msをとり
チツプ6への従来の電圧の印加曲線をEとし本発
明による電圧の印加曲線をFとした時、従来電圧
の印加時帯に於いてE曲線が同一値であつたのに
対し、本発明に於いては印加の当初に於いてF曲
線が同一値であつたのに対し、F曲線の如く、電
圧値を従来の値に対し大ならしめ、経時的に電圧
を降下して従来値に至らしめることにより、第3
図のD曲線に示す如く、温度上昇を急上昇とな
し、電圧を印加してより50ms以内で飽和温度に
達しせめる。
FIG. 3 shows the temperature increase of the heated chip of the bonder according to the present invention, and FIG. 4 shows the method of increasing the temperature of the heated chip of the bonder according to the present invention. When connecting the thin wire 5 of the discrete to the land 2 of the printed circuit board 1 by soldering, the shape of the heating chip 6 of the bonder is small, the heat capacity is small, and the temperature dependence of the ambient temperature is large, so it is difficult to solder the connection. Sex and thin lines 5
To avoid problems due to excessive heat melting of the polyurethane coating, in the present invention, the temperature rise curve of the chip 6 is shown in the conventional curve A, and the duration of the saturation temperature of 350°C on the contact surface of the chip 6 is 10 ms. As shown in the D curve, the duration of the saturation temperature is
This effectively increases the apparent heat capacity of the chip 6, reduces the temperature dependence of the chip 6 on the temperature of the outside air surrounding the chip 6, and ensures stable soldering and polyurethane connections. This is done to obtain the desired length of peeling by thermal melting of the coating, and for this purpose a voltage is applied to the heating element of the chip 6.
As shown in FIG. 4 in a time period of 100 ms, the Y-axis is the applied voltage V, the X-axis is the voltage application time ms, and the conventional voltage application curve to the chip 6 is E, and the voltage application according to the present invention is applied. When the curve is F, the E curve has the same value during the conventional voltage application period, whereas in the present invention, the F curve has the same value at the beginning of voltage application. On the other hand, as shown in the F curve, by increasing the voltage value compared to the conventional value and decreasing the voltage over time to reach the conventional value, the third
As shown by curve D in the figure, the temperature rise is assumed to be rapid and the voltage is applied to reach the saturation temperature within 50 ms.

この電圧の印加をチヨツピングした電圧で供給
することにより所望の温度上昇曲線を容易に行な
わしめることが可能である。
By applying this voltage with a stepped voltage, it is possible to easily obtain a desired temperature rise curve.

(7) 発明の効果 以上詳細に説明した如く、本発明のプリント基
板のランドとデイスクリート細線とを接続するボ
ンダーの加熱チツプの温度上昇の飽和温度の持続
時間をより長時間となすことにより、ランドと細
線との半田接続を確実になし、かつ細線のポリウ
レタン被膜の過剰な剥離を防除し得ることにより
半田接続の信頼性を確保し、かつ隣接ランドとポ
リウレタン被膜の剥離された細線による電気的接
触を防止するのに多大な効果を得た。
(7) Effects of the invention As explained in detail above, by making the duration of the saturation temperature of the temperature rise of the heating chip of the bonder that connects the land of the printed circuit board and the discrete thin wire for a longer time, By ensuring the solder connection between the land and the thin wire and by preventing excessive peeling of the polyurethane coating on the thin wire, the reliability of the solder connection is ensured. This has been very effective in preventing contact.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はプリント基板のランドと細線との接続
方法を示し、第2図は電圧印加されたチツプの温
度上昇と曲線を示し、第3図は本発明によるホン
ダーの加熱チツプの温度上昇を示し、第4図は本
発明によるボンダーの加熱チツプの温度上昇方法
を示す。 図に於いて2はランド、3は半田メツキ層、5
は細線、6はチツプをそれぞれ示す。
Fig. 1 shows the connection method between the land of the printed circuit board and the thin wire, Fig. 2 shows the temperature rise and curve of the chip to which voltage is applied, and Fig. 3 shows the temperature rise of the heated chip of Honda according to the present invention. , FIG. 4 shows a method of increasing the temperature of a heated chip of a bonder according to the present invention. In the figure, 2 is the land, 3 is the solder plating layer, and 5
6 indicates a thin line, and 6 indicates a chip.

Claims (1)

【特許請求の範囲】[Claims] 1 プリント基板の半田メツキされたランドと、
ポリウレタン被膜の施された細線の加熱圧接のた
めのボンダーのチツプに対し、加熱圧接時に加熱
圧接位置において、電圧の印加頭初に於いて電圧
を大ならしめ、次いで、経時的に印加電圧を所定
値まで降下せしめ、該所定値を一定時間保持する
ことを特徴とする細線の接続方法。
1 The soldered land of the printed circuit board,
During heat pressure welding, the voltage is increased at the beginning of the voltage application to the bonder chip for heat pressure welding of thin wires coated with polyurethane at the heat pressure welding position, and then the applied voltage is increased to a predetermined value over time. A method for connecting thin wires, characterized by lowering the wire to a certain value and maintaining the predetermined value for a certain period of time.
JP25000283A 1983-12-28 1983-12-28 How to connect thin wires Granted JPS60140894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25000283A JPS60140894A (en) 1983-12-28 1983-12-28 How to connect thin wires

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25000283A JPS60140894A (en) 1983-12-28 1983-12-28 How to connect thin wires

Publications (2)

Publication Number Publication Date
JPS60140894A JPS60140894A (en) 1985-07-25
JPH0380356B2 true JPH0380356B2 (en) 1991-12-24

Family

ID=17201382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25000283A Granted JPS60140894A (en) 1983-12-28 1983-12-28 How to connect thin wires

Country Status (1)

Country Link
JP (1) JPS60140894A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS555822A (en) * 1978-06-27 1980-01-17 Kubota Ltd Mold for rubber ring fitting socket
JPS5835936A (en) * 1981-08-28 1983-03-02 Fujitsu Ltd Processing of bonding chip

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58162670U (en) * 1982-04-23 1983-10-29 株式会社日立製作所 Wire-welding tip

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS555822A (en) * 1978-06-27 1980-01-17 Kubota Ltd Mold for rubber ring fitting socket
JPS5835936A (en) * 1981-08-28 1983-03-02 Fujitsu Ltd Processing of bonding chip

Also Published As

Publication number Publication date
JPS60140894A (en) 1985-07-25

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