JPH036685A - Article discriminating system - Google Patents

Abstract

PURPOSE:To reduce an influence of data destruction by enabling each ID controller to access only a prescribed area of a data carrier. CONSTITUTION:A data carrier 4 attached to an article as the discrimination object and a read/write control unit 7 including plural ID controllers 6 having data transmitting means 5 which transmit data to the data carrier 4 and receive transmitted data are provided. Each ID controller 6 can access only the area of a memory 1 of the data carrier 4 which is set by an access area setting means 8. Thus, data in the other areas of the data carrier 4 is not destroyed even at the time of the occurrence of transmission error between ID controllers 6 and a higher-order computer connected to it, and the safety of the system is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an identification system for tools for machine tools, parts in factories, products used in product management, distribution systems, and the like.

[Conventional technology]

In order to mechanize the tool management of conventional machine tools and the identification of parts and products on assembly lines in factories, tools 1
A system is needed to identify and manage various items such as parts and products. Therefore, as disclosed in Japanese Patent Application Laid-Open No. 63-221950, a data carrier having a memory is provided in the object to be identified, and the necessary information is written in such memory by external data transmission, and the information is read as necessary. An article identification system has been proposed in which the article is displayed on the screen.

[Problem to be solved by the invention]

In such conventional identification systems, the write/read control unit is configured to be able to access data at any address in the memory provided on the data carrier. However, in cases where the memory area of the data carrier is divided for each process, data in other processes may be destroyed due to a communication error between the host computer between the write/read control unit and the ID controller. However, this method has the disadvantage that it may affect the entire system.

The present invention was made in view of the problems of the conventional article identification system, and in an article identification system having a plurality of ID controllers, each ID controller can only access a specified area of the data carrier. The technical challenge is to reduce the impact of data destruction in this way.

[Means to solve the problem]

The present invention includes a memory 1 that holds data, a memory control means 2 that controls writing and reading of data into the memory, and a memory control means 2 that demodulates commands and data given from the outside and supplies them to the memory control means to transmit the read data. A document including a plurality of ID controllers 6 having a data carrier 4 attached to an article to be identified, and a data transmitting means 5 transmitting data to the data carrier and receiving the transmitted data. An article identification system comprising: an input/readout control unit 7;
The controller includes access area setting means 8 in which an address area for accessing the memory of the data carrier is set.
The device is characterized in that it is configured so that data can be written or read only in a predetermined access area.

[Effect]

According to the present invention having such characteristics, each ID controller can access only the area of the memory of the data carrier set by the respective access area setting means.

〔Effect of the invention〕

Therefore, according to the present invention, even if a transmission error occurs with the host computer connected to the ID controller, incorrect data will not be written to other areas of the data carrier or the data will not be destroyed. The effect is that the safety of the system can be improved.

[Explanation of Examples]

FIG. 2 is a block diagram showing the structure of an article identification system according to an embodiment of the present invention. In this figure, the article identification system is a bar (10a) that holds the article to be identified.
, 10b-...- are configured to be transported on the transport path ll, and each pallet 10a, 10b-
Data carriers 12a, 12b are directly attached to -------, respectively. Also, read/write heads (hereinafter referred to as RW heads) 13a, 13b that write and successively write data in positions facing the data carriers 12a, 12b, and ID controllers 14a, 14b connected to the RW heads 13a, 13b to control their operations. will be provided. I
The D controllers 14a, 14b are connected to a host computer, and constitute the write/read control unit 7 together with the RW heads 13a, 13b and the ID controllers 14a, 14b. Connected to the host computer 15 are a processing device 16 that performs predetermined processing on the article located on the pallet 10a, and a processing device 17 that performs predetermined processing on the article located on the barrel l-10b.

Now, as shown in the block diagram in FIG. 3, the ID controller 14 includes a microprocessor (CPU) 21 that controls writing and reading of data to and from the data carrier 12, and a memory 22 that holds the system program and data.
An input/output interface 23 for inputting and outputting father values to and from the computer 15 is provided. Also CPU
21 is connected to a DIP switch 24 which is a setting means for setting an access area of memory that can be accessed by this ID controller. In this embodiment, DIP switch 2
Assume that a page 4, which is a specific accessible area of the data carrier, is set for each ID controller as described later. RW head 13 is CPU2
It has a modulation circuit 25 to which an output is given from 1 and modulates data to be transmitted to the data carrier 12, and a transmitter 26 driven by the output. The transmitter 26 transmits data to the data carrier 12 by outputting an FSX-modulated signal from a coil, for example.

In addition, the received signal obtained from the data carrier 12 is transmitted to the receiving section 2.
7 to the demodulation circuit 28. The demodulation circuit 28 demodulates this signal and provides it to the CPU 21.

Next, the configuration of the data carrier 12 will be explained with reference to FIG. 4. In FIG. 4, a transmitting/receiving section 31 receives and transmits a frequency signal emitted from the RW head 13, and its reception output is given to a demodulation circuit 32. The demodulation circuit 32 demodulates this signal, converts the data into the original signal, and supplies the signal to the control section 33. The control unit 33 is connected to a memory 34 via a bus, such as static RAM or E2FR backed up by a battery 35.
A memory 34 configured by OM is connected. The control unit 33 is a memory control means 2 that controls writing or reading of data according to commands and data given from the ID controller 14, and the read data is converted into a serial signal and transmitted/received via the modulation circuit 36. Section 31. The transmitting/receiving section 31 provides a signal to the RW head 13 by changing the resonance frequency of a resonant circuit, for example, as in the conventional example. Here, the transmitting/receiving section 31. The demodulation circuit 32 and the modulation circuit 38 constitute a data transmission means 3 that demodulates command data given from the ID controller and gives it to the memory control means and transmits the read data.

FIG. 5 is a memory map showing the memory contents of the data carrier 12. As shown in this figure, the memory 34 of the data carrier is divided into a plurality of pages, for example, page 0 is set to address ro000J to [0OFFJ, and page 1 is set to an area of 256 bytes each, such as ro100J to roIFFJ. ing.

Each page is made up of a data area for processing N (N=1.2...) and a processing N result data area showing the processing results. Then, the ID controller 14a uses the DI so that it can access only the O page, for example.
The P switch 24 sets the upper byte of the address, ie, "00", and the ID controller 14b sets the D so that it can access only one page.
The IP switch has the upper 1 byte of the address, that is, “01
” is set. And O base is the second
The data processed by the processing tool 16 and the resulting data shown in the figure are sequentially configured in one page, which stores the processed data by the processing tool 17 and the data resulting from the processing. In this way, it is assumed that the ID controllers 14a and 14b have access areas of θ page and 1 page, respectively.

Now, the operation of such an article identification system will be explained with reference to the flowchart shown in FIG. When it starts working,
First, the host computer 15 sends a read command to the ID controller 14a to read the processed data at a predetermined address "XXJ" on page 0. Then, when the ID controller 14a receives the command in step 41, it sends the page data from the DIP switch 24. Import (
Step 42). The process then proceeds to step 43, where a lower processing address is created from the page data and the processing address. In this case, the upper 1 byte "00" of page O is added to data carrier 1 as address data roOXXJ.
2 and read the data.

Then, in step 44, command processing is executed, and in step 45, the execution result is returned to the host computer, and the processing is ended. After that, when processing is performed by the processing device 16, the host computer 15 sends write data for writing the data into the processing result area rXXJ of the 0 page. Then, the ID controller 14a adds the upper 1 byte "00" of page O, accesses the data carrier 12 as address data r00XXJ, and writes predetermined data.

Then, the articles loaded on the bullet 10a are transferred to the conveyance path 1.
1 to reach the second processing position shown at Paleso +-1ob in FIG. Then the upper computer 1
5 similarly sends the lower address of the memory 34 of the data carrier 12 and a read command to the ID controller 14b. The ID controller adds the upper address "01" to this address and reads the processing 2 data at a predetermined address from the data carrier 12 as address roIXXJ, and when the processing is completed, similarly writes the processing 2 result data to the predetermined address. Write. By setting accessible pages in the DIP switch 24 of each ID controller 14 in advance in this way, the amount of address information sent from the higher-level controller can be reduced, and even if an error occurs, the data carrier The data at the address will not be disturbed.

In this embodiment, pages accessible to the ID controller are set in advance using a DIP switch, etc., but page data is set in each ID controller from the host computer, and each ID controller stores the contents in memory. may be set. In this case as well, when a command is received from the host computer, an address is added to the page data to create an address to access the data carrier, and a predetermined command is executed.

Further, in the first embodiment described above, the memory of the data carrier is divided into a plurality of pages and access is made for each page, but the memory of the data carrier may be divided arbitrarily. In this case as well, the configuration shown in the block diagram is the same as that of the first embodiment described above. In this example, DI
P switch to two different addresses of data memory,
For example, upper and lower accessible addresses such as 0010 to 0IPF are set using DIP switches.

Also, instead of setting with the DIP switch, an accessible address may be set in the memory in the ID controller. It is assumed that the data carrier is accessed and a write or read command is executed only when a command to access this accessible area is given from the host computer.

FIG. 7 is a flowchart showing the processing of such an ID controller. When a command is received in step 51, the process proceeds to step 52, and the host computer 15
Checks whether the processing address given from is within the address range set by the ID controller. If it is within this address range, the process advances to step 53 and the command is executed.

The process then proceeds to step 54, where the processing results are sent to the host computer. If the processing address is not within the set address range in step 52, the process proceeds to step 55 and an error response is returned to the host computer.

In this way, an incorrect address will be recognized by a higher-ranking convenience store as an ID.
When given to the controller, if the command is not within the set address range, the command will not be executed and an error response will be returned, which greatly reduces the possibility of data carrier data being destroyed due to communication errors. I can do it.

[Brief explanation of the drawing]

Figure 1 is a functional block diagram showing the overall configuration of the present invention, Figure 2 is a functional block diagram showing the overall configuration of the present invention.
The figure is a perspective view showing the overall configuration of the article identification system, Figure 3 is a block diagram showing the configuration of the ID controller, Figure 4 is a block diagram showing the configuration of the data carrier, and Figure 5 is the ID controller.
FIG. 6 is a flowchart showing the processing of the 10 controllers according to the first embodiment;
The figure is a flowchart showing the processing of the ID controller of the article identification system according to the second embodiment of the present application. 1.34---1--Memory 2--Memory control means 3.5--Data transmission means 4,1
2.12a.

Claims (1)

[Claims] (1) A memory that holds data, a memory control means that controls writing and reading of data to the memory, demodulating commands and data given from the outside, and transmitting the read data to the memory control means. a data carrier that is attached to an article to be identified; and a plurality of ID controllers that transmit data to the data carrier and receive the transmitted data. An article identification system comprising: a control unit; each of the ID controllers has access area setting means in which an address area for accessing the memory of the data carrier is set; An article identification system characterized in that it is configured to write or read.