JP3007926B2 - Data carrier and identification system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data carrier and an identification system used for a tool of a machine tool, management of parts and products in a factory, a distribution system, and the like.

[Conventional technology]

2. Description of the Related Art Conventionally, a system for identifying and managing various articles such as tools, parts, products, and the like is required to mechanize the management of tools of machine tools and the identification of parts and products on an assembly and transfer line in a factory. Therefore, a data carrier having a memory is provided in the object to be identified as disclosed in Japanese Patent Application Laid-Open No. 1-163991, information necessary for the data carrier is written from outside by data transmission, and the information is read as necessary. A proposed article identification system has been proposed. Such a data carrier is used by being attached to a pallet or the like, and is configured to write or read data necessary for the data carrier from a write / read control unit arranged on the side of the pallet transport path. In such a conventional article identification system, data is transmitted from the write / read control unit without attaching a check code of the transmission data to the data carrier, or with a simple horizontal parity bit.

[Problems to be solved by the invention]

As described above, when data is transmitted from the data carrier to the read / write head side, the data and the parity bit are added to the data in addition to the synchronization code and the status. However, since the status information has already been transmitted even if the data in the memory changes (memory corruption), the memory corruption information cannot be transmitted to the write / read control unit.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem of the conventional article identification system, and enables a write / read control unit to reliably recognize such a state even if a memory corruption occurs. This is a technical issue.

[Means for solving the problem]

As shown in FIG. 1, the invention of claim 1 of the present application has a memory 1 for holding data, a data transmission means 2 for demodulating a command and data given from the outside, and transmitting the data read from the memory. A data carrier attached to an article to be identified, the data writing means 3 writing the same data in different areas of the memory when writing data on the data carrier, and a plurality of data writing means corresponding to a designated address when reading data. The memory corruption detecting means 4 for judging the coincidence of the written data by reading the data in the area, and the CRC check code or the CRC check code according to the presence or absence of the memory corruption by the memory corruption detecting means after the data reading is completed. And a CRC check code transmitting means 5 for transmitting the inverted code.

The invention according to claim 2 of the present application has a memory for holding data, a data transmission means for demodulating a command and data given from the outside, and transmitting the data read from the memory. Data carrier, and data and commands transmitted to the data carrier,
An identification system comprising: a write / read control unit for receiving transmitted data; wherein the data carrier is a data write means for writing the same data to different areas of the memory when writing data on the data carrier; A memory garble detecting means for judging the coincidence of written data by reading data in a plurality of areas corresponding to a designated address when reading data, and a memory garble detecting means for detecting the memory garble after the data reading is completed. C to send CRC check code as it is or invert according to presence / absence
RC check code transmission means, wherein the write / read control unit transmits a read command and data to the data carrier and receives data transmitted from the data carrier; An error discriminating means for discriminating the presence or absence of an error and the presence or absence of memory corruption from a CRC code and its inverted code when data is read.

[Action]

According to the present invention having such features, when data is written to the data carrier, the data is written to a different area of the memory. When a read command is given from the write / read control unit, data is read from a plurality of areas corresponding to the written address by the memory corruption detection means, and the coincidence between them is determined to detect the memory corruption. Is going. If memory corruption is not detected, the CRC check code is directly appended to the read data, and if memory corruption is detected, the CRC is used.
The check code is inverted and sent to the write / read control unit.

According to the invention of claim 2 of the present application, the write / read control unit sends a write command or a read command to the data carrier, and after sending the read command, a CRC check code attached to the data carrier or an inverted check code thereof. The presence or absence of an error and the presence or absence of memory corruption are determined by a code.

〔Example〕

FIG. 2 is a block diagram showing a configuration of an article identification system according to one embodiment of the present invention. In this figure, an article identification system is a pallet 11 on which components to be identified are transported.
And a read / write head 1 for writing and reading data to and from the data carrier 12
3, and an ID controller 14 connected to the read / write head 13 and controlling its operation. The read / write head 13 and the ID controller 14 constitute a write / read control unit. The ID controller 14 is connected to a host computer 15.

As shown in the block diagram of FIG. 3, the ID controller 14 is provided with a microprocessor (CPU) 21 for controlling writing and reading of data to and from the data carrier 12 and a memory 22 for holding the system program and data. Further, an input / output interface 23 for inputting / outputting with the host computer 15 is provided. Read / write head 13
Has a modulation circuit 24, which receives an output from the CPU 21 and modulates data to be transmitted to the data carrier 12, and a transmission unit 25 driven by the output. The transmission unit 25 transmits data to the data carrier 12 by outputting, for example, an FSK-modulated signal from a coil. Further, a reception signal obtained from the data carrier 12 is provided to a demodulation circuit 27 via a reception unit 26. The demodulation circuit 27 demodulates this signal and provides it to the CPU 21. Here, the read / write head 13 constitutes a data transmission means for transmitting a command and data to the data carrier and receiving the transmitted data, and the CPU 21 determines an error by a received CRC code or its inverted code as described later. It has the function of an error determining means for determining the presence or absence and the presence or absence of memory corruption.

Next, the configuration of the data carrier 12 will be described with reference to FIG. In FIG. 4, a transmission / reception unit 31 receives and transmits a signal of a frequency emitted from the read / write head 13, and its reception output is given to a demodulation circuit 32. The demodulation circuit 32 demodulates this signal, converts the data into the original signal, and supplies the original signal to the control unit 33. A memory 34 is connected to the control unit 33 via a bus. The control unit 33 includes a data write unit 3 for controlling writing or reading of data in accordance with a command and data given from the ID controller 14, a memory corruption detection unit 4, and a CRC check code for transmitting a CRC check code, as described later. The transmission means 5 is constituted. Then, the data read from the memory 34 is converted into a serial signal and supplied to the transmission / reception unit 31 via the modulation circuit 35. The transmission / reception unit 31 gives a signal to the read / write head 14 by changing the resonance frequency of the resonance circuit as in the conventional example. Here, the transmission / reception unit 31, the demodulation circuit 32, and the modulation circuit 35 demodulate the data of the command given from the ID controller,
It constitutes data transmission means 2 for transmitting the read data.

FIG. 5 is a diagram showing a memory map of the memory 34. As shown in the figure, assuming that write data 1 is “00111100” and write data 2 is “11111111”, those write data are written to addresses “0000” and “0002”. The odd addresses “0001” and “0003” show states in which write data 1 and 2 are inverted data, respectively. As described above, when the data to be written is given by the data write means 3, the memory is used so that the data is written into the even addresses and the inverted data is written into the odd addresses. In this case, the capacity of the memory is halved compared to the normal case, and when reading, it is necessary to read even and odd addresses at the same time, so the number of access circuits is doubled. Reliability can be improved.

Next, the corresponding operation of the write / read control unit will be described with reference to the flowcharts of FIGS. First, in step 41, a read command for reading data from the read / write head side is sent to the data carrier 12. If this command is sent, the process proceeds to step 42 and waits for a response from the data carrier 12. On the other hand, the data carrier 12 waits for the reception of the command as shown in FIG. 7A (step 51), and if there is a read command, the process proceeds to the routine 52 to detect data read and memory corruption. The routine 52 is shown in FIG.
In steps 53 and 54, data of even addresses and odd addresses are read in steps 53 and 54. Then, the process proceeds to a step 55, wherein the data of the odd address is inverted, and this data is compared with the data of the even address. If the data match, it is determined that there is no garbled data in the memory (step 56). If the data do not match, it is determined that there is garbled memory (step 57), and this routine ends.
Then, proceed to step 58, determine whether there is a memory corruption,
If the memory is corrupted, the process proceeds to step 59, where the data whose CRC is inverted is sent to the read / write head side of the write / read control unit following the status and read data. On the other hand, if the memory is not corrupted, the process proceeds from step 58 to step 60, where CRC data is added to the status and read data, and the response to the read command is completed. On the other hand, if there is a response from the data carrier 12, the read / write head proceeds to step 43 to check for a CRC error. If there is no CRC error, the process is terminated without any error (step 44), and if there is a CRC error, the process proceeds to step 45 to check whether or not there is a CRC error when the CRC is inverted. If there is an error due to the inversion of the CRC, it is determined that the error occurred during communication (step 46). So the steps
Returning to step 41, the command is transmitted again and the same processing is repeated. Then, if there is no error when the CRC is inverted, it is determined that the memory 34 in the data carrier in which the data is changed is corrupted (step 47). In this case, since it is not necessary to read the data again, the process ends. Here, the write / read control unit achieves the function of an error discriminating means for discriminating the presence / absence of an error and the presence / absence of a garbled memory based on the CRC code and its inverted code after transmitting the read command in steps 41 to 47. Here, the control unit 33 of the data carrier executes a routine 52
When the data is read out, the data in a plurality of areas corresponding to the designated address is read out, and the function of the memory corruption detection means 4 for determining the coincidence of the written data is achieved. The function of the CRC check code sending means 5 for sending the CRC check code as it is or inverting it according to the presence or absence of the memory corruption by the detecting means is achieved.

〔The invention's effect〕

As described in detail above, in the present invention, when data is written to a data carrier and data is read, it is determined whether or not the memory is corrupted, and if the memory is corrupted, the CRC check code is inverted and transmitted. I have. Therefore write /
The read control unit can determine that data in the memory is garbled, and this can be reported. Therefore, the reliability of the entire system can be improved. In addition, it has the commonality with the conventional communication protocol, and has an effect that an area for indicating the garbled information is not required.

[Brief description of the drawings]

1 is a block diagram showing a functional configuration of the present invention, FIG. 2 is a block diagram showing an overall configuration of an article identification system used in the present invention, and FIG. 3 is a block diagram showing a configuration of an ID controller and a read / write head. FIG. 4 is a block diagram showing the configuration of the data carrier, FIG. 5 is a memory map of the memory 34, FIG. 6 is a flowchart showing the operation of the ID controller according to the present embodiment, and FIGS. b) is a flowchart showing the operation of the data carrier of the present invention. 1, 34: memory 2, data transmission means 3, data writing means 4, memory corruption detection means 5, CRC check code transmission means 12, data carrier 13, ...
Read / write head, 14 ID controller, 15 host computer, 21 CPU, 33 control unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04B 5/00 G06F 13/00 H04L 1/00

Claims (2)

(57) [Claims] 1. A data carrier attached to an article to be identified, comprising a memory for holding data, a data transmission means for demodulating an externally applied command and data, and transmitting data read from the memory. Data write means for writing the same data to different areas of the memory when writing data on the data carrier; and data written by reading data from a plurality of areas corresponding to a specified address when reading data. Memory corruption detection means for determining the coincidence of, and a CRC check code transmission means for transmitting the CRC check code as it is or inverting according to the presence or absence of memory corruption by the memory corruption detection means after the data reading is completed, A data carrier comprising: 2. A data carrier attached to an article to be identified, comprising: a memory for holding data; a data transmission means for demodulating an externally applied command and data and transmitting data read from the memory; A write / read control unit for transmitting data and commands to the data carrier and receiving the transmitted data;
An identification system comprising: a data carrier that writes the same data to different areas of a memory when data is written to a data carrier; and data in a plurality of areas corresponding to a specified address when reading data. Garbled detecting means for judging the coincidence of the written data by reading the data, and after the completion of the reading of the data, the CRC check code is directly or inverted depending on whether or not the garbled memory is detected by the memory garbled detecting means. Data transmission means for transmitting a read command and data to the data carrier, and receiving the data transmitted from the data carrier. A CRC code and its inverted code when data is read from the data carrier. And an error determining means for determining whether or not there is an error and whether or not the memory is garbled from the memory.