JPH0366234U

JPH0366234U -

Info

Publication number: JPH0366234U
Application number: JP12395589U
Authority: JP
Priority date: 1989-10-25
Filing date: 1989-10-25
Publication date: 1991-06-27

Description

【図面の簡単な説明】第１図は、本考案の一実施例を示すブロツク図
、第２図および第３図は、第１図の実施例のタイ
ミング図、第４図は、無線システムを示す図、第
５図および第６図は、従来の伝搬遅延補償回路を
示すブロツク図である。１〜２……インバータ、３〜６……データセレ
クタ、７……位相測定回路、８……遅延補償回路
、８Ａ_１〜８ＡＮ……シフトレジスタ、８Ｂ_１〜
８ＢＮ……データセレクタ、８Ｃ……遅延量設定
スイツチ、８Ｄ……論理積否定回路、９……選択
スイツチ。[Brief Description of the Drawings] Figure 1 is a block diagram showing an embodiment of the present invention, Figures 2 and 3 are timing diagrams of the embodiment of Figure 1, and Figure 4 shows a wireless system. 5 and 6 are block diagrams showing conventional propagation delay compensation circuits. 1-2...Inverter, 3-6...Data selector, 7...Phase measurement circuit, 8...Delay compensation circuit, _8A1-8AN ...Shift register, _8B1-
8BN...Data selector, 8C...Delay amount setting switch, 8D...NAND circuit, 9...Selection switch.

Claims

[Claims for Utility Model Registration] (1) A delay unit that delays one demodulated signal of each of two demodulated signals received from an adjacent base station, demodulated and reproduced, using a clock for delaying this one demodulated signal; In a propagation delay compensation circuit comprising a measuring section that measures the phase difference between the other demodulated signal and the demodulated signal delayed by the delay section, a first selection selects two demodulated signals and outputs them to the delay section. a second selection section that receives the clock for delaying the demodulated signal as input and outputs the clock for delaying the demodulation signal selected by the first selection section to the delay section; and the first selection section. A propagation delay compensation circuit comprising: a third selection section that outputs a demodulation signal different from the demodulation signal selected in step 1 and a demodulation signal delayed by the delay section to the measurement section. (2) a delay unit that delays one demodulated signal of each of the two demodulated signals received from an adjacent base station, demodulated and reproduced, using a clock for delaying one of the demodulated signals; and the other demodulated signal and the delay unit. A propagation delay compensation circuit comprising: a measurement section that measures a phase difference with a demodulated signal delayed by a switch; and a switch that instructs switching, and selects two demodulated signals and outputs them to the delay section according to instructions from the switch. a first 2-input 1-selection data selector that inputs a clock for delaying the two demodulated signals; a second 2-input 1-selection data selector that outputs 2-input 1-selection data to the delay section; and a second 2-input 1-selection data selector that receives one of the demodulated signals and the demodulated signal from the delay section, and outputs the first 2-input 1-selection data according to an instruction from the switch. a third 2-input 1-select data selector that outputs the demodulated signal selected by the selector to the measuring section; the other demodulated signal and the demodulated signal from the delay section are input; A propagation delay compensation circuit comprising: a fourth two-input one-select data selector that outputs a demodulated signal different from the demodulated signal selected by the two-input one-select data selector to the measuring section.