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JPS5840862B2 - Synchronous signal transmission method - Google Patents

Synchronous signal transmission method

Info

Publication number
JPS5840862B2
JPS5840862B2 JP52005463A JP546377A JPS5840862B2 JP S5840862 B2 JPS5840862 B2 JP S5840862B2 JP 52005463 A JP52005463 A JP 52005463A JP 546377 A JP546377 A JP 546377A JP S5840862 B2 JPS5840862 B2 JP S5840862B2
Authority
JP
Japan
Prior art keywords
signal
synchronization
pulse
synchronization signal
sync signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52005463A
Other languages
Japanese (ja)
Other versions
JPS5390708A (en
Inventor
健 荒川
昇 山崎
国夫 秋場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP52005463A priority Critical patent/JPS5840862B2/en
Publication of JPS5390708A publication Critical patent/JPS5390708A/en
Publication of JPS5840862B2 publication Critical patent/JPS5840862B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0602Systems characterised by the synchronising information used

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Description

【発明の詳細な説明】 本発明は正確に同期信号を伝送することのできる同期信
号伝送方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization signal transmission system that can accurately transmit synchronization signals.

PSKを同期信号として用いる場合、回線途中に時間的
に断続、位相づれが発生すると一同期誤動作となる。
When PSK is used as a synchronization signal, if temporal discontinuity or phase shift occurs in the middle of the line, a single synchronization malfunction will occur.

たとえば同一電波を二つ以上の複数の場所で受信して、
回線を通して中央に集め、S/Nの最もよい信号を選択
して切替えるようなシステムの場合、受信地から中央ま
での間の遅延量に差がある場合は、切替え時に見かけ上
位相変化が発生し、同期誤動作となってしまう。
For example, if the same radio wave is received at two or more locations,
In the case of a system in which the signal is collected centrally through a line and the signal with the best S/N is selected and switched, if there is a difference in the amount of delay between the receiving location and the center, an apparent phase change may occur when switching. , resulting in synchronization malfunction.

本発明はこのような欠点が除くもので正規の同期信号の
ほかに擬似同期信号を時分割で加え、受信側では逆に信
号の時系列を検定することにより正規の同期信号を検出
するようにしたものである。
The present invention eliminates this drawback by adding a pseudo synchronization signal in addition to the regular synchronization signal in a time-division manner, and conversely detecting the regular synchronization signal by verifying the time series of the signal on the receiving side. This is what I did.

以下にその実施例について説明する。Examples thereof will be described below.

第1図において11は正規の同期信号を発生する信号源
、12は擬似同期信号を発生する信号源、13はその2
つの同期信号を選択制御する信号を発生する信号源、1
4はその制御信号で2つの同期信号を選択合成するマル
チプレックス、15はPSK変調器である。
In FIG. 1, 11 is a signal source that generates a regular synchronization signal, 12 is a signal source that generates a pseudo synchronization signal, and 13 is the second one.
a signal source that generates a signal for selectively controlling two synchronization signals; 1;
Numeral 4 is a multiplex that selectively combines two synchronization signals using its control signal, and 15 is a PSK modulator.

16はPSK復調器、18はタイミング信号の発生回路
、17は同期信号の検定回路である。
16 is a PSK demodulator, 18 is a timing signal generation circuit, and 17 is a synchronization signal verification circuit.

11〜15で送信機が構成され、16〜17で受信機が
構成されている。
11 to 15 constitute a transmitter, and 16 to 17 constitute a receiver.

次に動作を説明する。Next, the operation will be explained.

同期信号源11から第2図イに示す本来の同期信号が発
生し、同期信号源12から第2図口に示す擬似同期信号
が発生する。
The synchronization signal source 11 generates the original synchronization signal shown in FIG. 2A, and the synchronization signal source 12 generates the pseudo synchronization signal shown in FIG.

この2つの同期信号は信号源13の制御信号(第2図ハ
に示す)により選択される。
These two synchronization signals are selected by a control signal of the signal source 13 (shown in FIG. 2C).

制御信号のHレベルでは正規の同期信号が、またLレベ
ルでは擬似同期信号がマルチプレックス14で選択され
、第2図二に示す合成信号が作成される。
When the control signal is at H level, a regular synchronization signal is selected, and when it is at L level, a pseudo synchronization signal is selected by multiplex 14, and a composite signal shown in FIG. 2B is created.

この合成信号はPSK変調器15で変調され、伝送路に
送出される。
This composite signal is modulated by the PSK modulator 15 and sent to the transmission path.

また受信機側では伝送された信号をPSK復調器16で
復調し、その受信信号に位相変化が生じている場合にそ
の前後の位相変化を検定回路1Tで検定する。
On the receiver side, the transmitted signal is demodulated by a PSK demodulator 16, and if a phase change occurs in the received signal, a test circuit 1T tests the phase change before and after the phase change.

すなわち今、仮に検定の時間巾を発生回路18の出力を
もとに±t2とし、擬似位相変化巾を11としてt2>
2tlと設定する。
That is, now, let us assume that the verification time width is ±t2 based on the output of the generation circuit 18, and the pseudo phase change width is 11, so that t2>
Set it to 2tl.

この場合第2図ハに示した制御信号の′l′H“区間を
t2よりも大とする。
In this case, the `l'H'' section of the control signal shown in FIG. 2C is made larger than t2.

こうして検定回路17を「位相の変化があった時にその
前後±t2の量変化がないならば正規の同期信号とみな
して目的の時間にパルスを発生させる」ようにする。
In this way, the verification circuit 17 is configured to ``if there is no change in the amount of ±t2 before and after the phase change, it is regarded as a regular synchronization signal and a pulse is generated at the desired time.''

こうすれば、仮に擬似同期区間に回線変化が発生し、第
2図へのように位相変化が発生した場合、または第2図
トのように擬似位相変化が1回欠けた場合にも誤動作に
はならない。
This way, even if a line change occurs in the pseudo synchronization section and a phase change occurs as shown in Figure 2, or if one pseudo phase change is missing as shown in Figure 2, malfunctions will not occur. Must not be.

−万、正規の同期区間に回線変化が発生した時は当然正
規の同期信号は検出されないが、上記のような合成信号
を時間的に繰り返し送出すれば、一度同期整合したあと
は再び同期検出するまで自走させておけばよい。
- Of course, when a line change occurs during a regular synchronization interval, the regular synchronization signal will not be detected, but if the above composite signal is sent repeatedly in time, synchronization will be detected again after synchronization is achieved. All you have to do is let it run on its own.

なお第2図チは従来の伝送方式における回線変化の例を
示したもので矢印のところで誤動作をおこしている。
Note that FIG. 2H shows an example of line changes in a conventional transmission system, where a malfunction occurs at the arrow.

第3図は第1図における検定回路17の具体的構成を示
したもので、入力信号の位相変化があった時にその前後
±t2間に位相変化がなかったどうかを検定するもので
、なかった時に出力を発生する。
Figure 3 shows the specific configuration of the verification circuit 17 in Figure 1, which verifies whether or not there is a phase change before and after ±t2 when there is a phase change in the input signal. Generates output at times.

まず入力信号aはt2よりも若干長い時間だけシフトレ
ジスタ21を用いて遅延させる。
First, the input signal a is delayed using the shift register 21 for a time slightly longer than t2.

この遅延出力すと入力信号aをゲート22でエクスクル
−シブオアをとると両方の位相が異なる時にパルスcが
発生する。
With this delayed output, when an exclusive OR is performed on the input signal a at the gate 22, a pulse c is generated when both phases are different.

即ちこのパルスCのパルス巾がt2以上であるかどうか
を検定することにより±12時間位相変化がなかったか
どうかを検定できる。
That is, by verifying whether the pulse width of this pulse C is greater than or equal to t2, it is possible to verify whether there is no phase change within ±12 hours.

デコーダ23の出力dはパルスの立上り後t2時間にパ
ルスを発生するもので、これでR−8フリツプフロツプ
24をセットする。
The output d of the decoder 23 generates a pulse at time t2 after the rise of the pulse, and this sets the R-8 flip-flop 24.

もしパルスCのパルス巾が12以上なら信号dを発生し
て出力eが11“になりゲート26を通じてバイナルカ
ウンター25のリセット機能をとめ、目的の時間にデコ
ーダ27を通じて出力gを発生しR−8フリツプフロツ
プ24をリセットしてもとにもどる。
If the pulse width of the pulse C is 12 or more, a signal d is generated, the output e becomes 11'', the reset function of the vinyl counter 25 is stopped through the gate 26, and the output g is generated through the decoder 27 at the desired time. Reset the flip-flop 24 and return to the original state.

また、パルスCのパルス巾がt2以下ならただちにカウ
ンター25をリセットしてしまう。
Further, if the pulse width of pulse C is less than t2, the counter 25 is immediately reset.

従って擬似同期信号では出力が発生しないが、正規の同
期信号では出力が発生する。
Therefore, no output is generated with a pseudo synchronous signal, but an output is generated with a regular synchronous signal.

また第4図は第3図の要部の信号波形を示すもので、対
応する部分には同符号a−gを付している。
Further, FIG. 4 shows signal waveforms of main parts of FIG. 3, and corresponding parts are given the same symbols a to g.

上記実施例より明らかなように本発明によれば正規の同
期信号と擬似同期信号を時分割して加えた信号を送信側
より送出し、受信側でその信号の時間的変化を検出して
同期信号を検出するようにしているため、伝送路におけ
る位相変化があっても同期信号の検出を精度よく行なう
ことができる。
As is clear from the above embodiments, according to the present invention, a signal obtained by time-divisionally adding a regular synchronization signal and a pseudo synchronization signal is sent from the transmitting side, and the receiving side detects the temporal change in the signal and synchronizes. Since the signal is detected, the synchronization signal can be detected accurately even if there is a phase change in the transmission path.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の同期信号伝送方式を具体化した実施例
のブロック図、第2図はその信号波形図、第3図は要部
の詳細な構成を示すブロック図、第4図はその信号波形
図である。 11・・・・・・同期信号源、12・・・・・・擬似同
期信号源、14・・・・・・マルチプレックス、17・
・・・・・検定回路。
Fig. 1 is a block diagram of an embodiment embodying the synchronization signal transmission method of the present invention, Fig. 2 is a signal waveform diagram thereof, Fig. 3 is a block diagram showing the detailed configuration of the main part, and Fig. 4 is its signal waveform diagram. It is a signal waveform diagram. 11... Synchronous signal source, 12... Pseudo synchronous signal source, 14... Multiplex, 17.
... Verification circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 正規の同期信号と擬似同期信号とを時分割で加えた
合成同期信号を送出し、受信した合成同期信号を遅延し
た遅延合成同期信号と上記合成同期信号との排他論理和
をとってパルス信号を得、このパルス信号のパルス幅が
所定値以上か否かを検定して正規の同期信号を検出する
ことを特徴とする同期信号伝送方式。
1. Sends a composite sync signal that is obtained by time-divisionally adding a regular sync signal and a pseudo sync signal, and performs an exclusive OR of the delayed composite sync signal obtained by delaying the received composite sync signal and the composite sync signal to generate a pulse signal. A synchronization signal transmission system characterized in that a regular synchronization signal is detected by determining whether the pulse width of this pulse signal is equal to or greater than a predetermined value.
JP52005463A 1977-01-20 1977-01-20 Synchronous signal transmission method Expired JPS5840862B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52005463A JPS5840862B2 (en) 1977-01-20 1977-01-20 Synchronous signal transmission method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52005463A JPS5840862B2 (en) 1977-01-20 1977-01-20 Synchronous signal transmission method

Publications (2)

Publication Number Publication Date
JPS5390708A JPS5390708A (en) 1978-08-09
JPS5840862B2 true JPS5840862B2 (en) 1983-09-08

Family

ID=11611914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52005463A Expired JPS5840862B2 (en) 1977-01-20 1977-01-20 Synchronous signal transmission method

Country Status (1)

Country Link
JP (1) JPS5840862B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3707760C1 (en) * 1987-03-11 1988-06-23 Ant Nachrichtentech Clock synchronization method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49114308A (en) * 1973-02-12 1974-10-31

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49114308A (en) * 1973-02-12 1974-10-31

Also Published As

Publication number Publication date
JPS5390708A (en) 1978-08-09

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