JPH0364141A - Outgoing line buffer priority control system for packet switchboard - Google Patents

Abstract

PURPOSE:To attain priority control as a hardware switch with a small memory quantity by providing the buffer memory of a fixed length packet signal corresponding to the outgoing line of the hardware switch. CONSTITUTION:The packet signal 1 of a fixed length has a call identification number and priority display as label information. A hardware switch 2 having nXn incoming lines from (IN-11)-(1n) to (IN-n1)-(nn) is of multi-stage switch constitution constituting unit switches having nXm (n<=m) input and outgoing lines as multi-stage, and each unit switch has a buffer memory B. Then a multi- stage switch connection constitution means is adopted to decrease the operating efficiency in the link of a multi-stage and the probability stored in the prescribed buffer memory B with the collision of the packet signals of fixed length is decreased. Thus, the priority control as the hardware switch is attained with less memory quantity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a packet switching line buffer priority control system for switching connections using fixed length packet signals having switch connection information as label information.

[Conventional technology]

Conventionally, the switching connection of a packet switch has been configured such that software reads the label information of the packet signal, deciphers the connection destination, and performs software switching connection.

In recent years, high-speed packet switches have been developed that implement packet switches using hardware switch circuits, add call identification numbers to the label information of packet signals, and perform switching connections based on the label numbers. It is necessary to display the priority and connect high-priority fixed-length packet signals preferentially through the hardware switch. A specific priority control method for this purpose is to install a buffer memory in each unit switch that makes up the hardware switch, and display the priority in the label of the fixed-length packet signal when controlling the readout of the buffer memory. Accordingly, the configuration is such that priority control is performed by preferentially reading out high-priority fixed-length packet signals.

[Problem to be solved by the invention]

FIG. 2 is a pull diagram showing an example of a conventional packet switch connected by hardware switching.

In FIG. 2, IA is a fixed-length packet signal having a call identification number as a label, and 2 is a hardware switch having nXm input lines from IN-11 to 1n to IN-n1 to nn. In Fig. 2, the hardware switch 2 has a three-stage configuration, and each stage has a switch of nXm (n2m
), and each unit switch has a buffer memory B. A plurality of packet calls are input to each contact line of a packet switch using a hardware switch, and fixed-length packet signals are asynchronously input from each packet call to the hardware switch. A collision phenomenon may occur in which fixed-length packet signals asynchronously input from a plurality of incoming lines of one unit switch constituting the hardware switch 2 attempt to be connected to one outgoing line of that unit switch. In this case, multiple fixed-length packet signals cannot be simultaneously output to one outgoing line. For this reason, it is common practice to install a buffer memory B in each unit switch, and to store fixed-length packet signals that have temporarily caused collisions in this buffer memory B. On the other hand, there is an upper limit to the memory amount of such buffer memory B, and if the number of fixed-length packet signals that are accumulated over time exceeds the upper limit of the memory amount of buffer memory B, a new fixed-length packet signal is input. will be discarded. Discarding this fixed length packet signal causes a deterioration in communication quality. By analyzing the characteristics of the collision phenomenon of fixed-length packet signals on the outgoing line in various generation patterns of fixed-length packet signals, we determined the amount of buffer memory required for unit switches to reduce the discarding of fixed-length packet signals to a predetermined probability or less. is known to be large in quantity.

Figure 3 shows the probability that fixed-length packet signals will collide on one output line and a predetermined number of packet signals will be stored in buffer memory B when the input line and output line efficiencies are changed in each unit switch in Figure 2. It is a diagram.

Furthermore, packet calls have various requirements, such as services with strict real-time characteristics in terms of connection time characteristics and services with very strict requirements on the discard probability of fixed-length packet signals. For this reason, it is necessary to provide a priority indication in the label of the fixed-length packet signal for each call, and to perform priority control to give priority to the fixed-length packet signal with a high priority indication in the read control of the buffer memory. If this priority control is executed for each buffer memory B corresponding to each unit switch, control becomes complicated.

In this way, priority control in conventional hardware switch configurations requires a large amount of buffer memory for each unit switch, and priority read control needs to be performed in the buffer memory of each unit switch. There are, etc.
There are many problems.

The control system includes a packet switch that exchanges and connects fixed-length packet signals having a call identification number and priority indication as label information using a hardware switch, and a buffer memory corresponding to each of the unit switches, and a buffer memory corresponding to each unit switch. As for the connection configuration, the internal operating speed of the door switch is V l l + input linear speed ■, and the number of links connecting the connected multi-stage switches is set as the number of links between the connected multi-stage switches of the hardware switch. a buffer memory, and using at least one multistage switch connection configuration means of the multistage switch connection configuration means, a buffer memory for a fixed length packet signal is installed corresponding to an outgoing line of the hardware switch, and the signal is stored in the buffer memory. The present invention is characterized in that priority control is executed by priority read control according to the priority indication in the label of the fixed-length packet signal.

do.

〔Example〕

Next, the present invention will be explained with reference to FIG.

be.

In FIG. 1, 1 is a fixed length packet signal having a call identification number and priority indication as label information. 2 is l
It is a hardware switch with nXn input lines from N-11 to 1n to IN-n1 to nn, and nXm (
This is a multi-stage switch configuration in which unit switches each having an incoming line and an outgoing line (n2m) are arranged in multiple stages, and in FIG. 1, there are three stages of switches. Each unit switch has a buffer memory B. 0UT-11~0UT-1n to 0U
There are nXn outgoing lines from T-nl to nn, and 3-11
3-1n to 3-n1 to 3-nn are buffer memories installed corresponding to each outgoing line. Here, the speed of the line entering the software switch 20 is V;. The operating speed of each stage switch of the multistage switch and the link speed connecting each stage switch are 11flk. As for the connection configuration of the multi-stage switch, the speed vllfik is V. There are two multistage switch connection configuration means, a first multistage switch that sets the speed higher, and a second multistage switch connection configuration means that makes the number of links connecting the connected multistage switches larger than the number of input lines of the hardware switch. Either only one of the two multi-stage switch connection configuration means is employed, or both are employed.

1″F The operation of this embodiment configured as described above is as follows.

A fixed length packet signal 1 is asynchronously input to a plurality of incoming lines of a hardware switch 2. No. 1 - Multiple input lines of each unit switch configuring the hardware switch 2,
A plurality of fixed length packet signals are asynchronously input from a plurality of packet calls. Therefore, a collision phenomenon occurs in which a plurality of fixed-length packet signals attempt to be simultaneously connected to one outgoing line of each unit switch. Here, if the first or second multi-stage switch connection configuration means or both multi-stage switch connection configuration means are employed, the usage efficiency with respect to the link speed of the fixed-length packet signal is determined for each input line of the hardware switch 2. The usage efficiency is lower than the usage efficiency for the input line speed of fixed-length packet signals. By the way, as mentioned above, FIG. 3 shows the amount of data accumulated in a predetermined buffer memory B due to the collision of fixed-length packet signals on one outgoing line of the unit switch when the incoming line and outgoing line efficiencies of the unit switch are changed. It shows the probability that it will happen. On the other hand, by employing the first or second multi-stage switch connection configuration means, it is possible to reduce the usage efficiency of the multi-stage switch link, and as shown in FIG. This makes it possible to reduce the probability that In other words, compared to the amount of buffer memory required for each unit switch in the case of a conventional hardware switch configuration,
This can be achieved with a very small amount of buffer memory, less than a few tenths of the amount. Therefore, each unit switch can read the fixed-length packet signal stored in the buffer memory on the priority side without having to control the readout of the fixed-length packet signal stored in the buffer memory according to the priority display in the label of the fixed-length packet signal. The fluctuations in the connection time will be very small. Buffer memories 3-11 to 3-1n to 3-nl to nn installed corresponding to the outgoing lines of the hardware switch 2 are connected to the outgoing lines of each unit switch at the final stage of the hardware switch 2. If the first multi-stage switch connection configuration means are employed, the internal speed V at the multi-stage switch
llnk was fast, but the speed at the output line of hardware switch 2 was as fast as vl, .
The utilization efficiency of the fixed length Paget signal with respect to the output line speed of the hardware switch 2 is a high value. In addition, if the second multi-stage switch connection configuration means is adopted, the number of links in the hardware switch
Since the number of outgoing lines is set to be small, the usage efficiency of the fixed-length packet signal with respect to the outgoing line speed of the hardware switch 2 is a high value.

Therefore, if the characteristics shown in FIG. 3 are followed, the probability that a predetermined number of fixed-length packet signals will be accumulated in the buffer memory corresponding to the outgoing line installed at each outgoing line of the hardware switch increases. For this reason, a large amount of buffer memory is installed for each outgoing line of the hardware switch. This buffer memory corresponding to the outgoing line is used to control the reading of the fixed-length packet signal stored in the buffer memory according to the priority indication in the label of the fixed-length packet signal.

〔Effect of the invention〕

As explained above, by using the present invention, there is an effect that the buffer memory corresponding to the unit switch required for each unit switch constituting the hardware switch can be made with a small memory amount. Since a large number of unit switches are used in one hardware switch, the configuration of the present invention, in which the amount of buffer memory corresponding to the unit switches is small, is advantageous compared to the conventional system.

In addition, in the present invention, there is no need to perform readout control according to the priority indication in the label of the fixed-length packet signal in the buffer memory of each unit switch, and the data is stored in the buffer memory installed corresponding to the outgoing line of the hardware switch. Priority control as a hardware switch is possible by controlling the reading of fixed-length packet signals. The method of the present invention, which significantly reduces the number of places where conventional forces are applied, is advantageous in that it simplifies control.

Furthermore, determining the usage efficiency of fixed-length packet signals in relation to the outgoing line speed on the outgoing line is a major issue for communication network operators who operate packet networks. may be operated with different values. In the conventional method, in order to set the above-mentioned outgoing line usage efficiency to a different value depending on the communication network operator, it is necessary to change the read control of the buffer memory corresponding to each unit switch. It is difficult to use a wear switch. In contrast, the method of the present invention can be achieved by simply changing the read control in the buffer memory corresponding to the outgoing line of the hardware switch, and has the advantage of being highly flexible.

It is a figure showing the probability that only the quantity is accumulated.

1. IA...Fixed length packet signal, 2...
・Hardware switch, 3-11 to 3-1 n,
3-n1 to 3-n n...Buffer memory.

Claims (1)

[Claims] In a packet switch that exchanges and connects fixed-length packet signals with call identification numbers and priority indications as label information using hardware switches, the hardware has a multi-stage switch configuration in which n×m (n≦m) unit switches are connected in multiple stages. A hardware switch and a buffer memory corresponding to each of the unit switches are provided, and the connection configuration of the multi-stage switch is based on the internal operating speed V_l_i_ of the hardware switch.
at least a first multi-stage switch connection configuration means for making n_k faster than the input linear velocity V_i_n, and a second multi-stage switch connection configuration means for increasing the number of links connecting each stage switch than the number of input lines of the hardware switch. A fixed-length packet signal buffer memory is installed corresponding to the outgoing line of the hardware switch using one of the multi-stage switch connection configuration means, and the priority is displayed in the label of the fixed-length packet signal stored in this buffer memory. An outgoing buffer priority control method for a packet switch, characterized in that priority control is performed by priority read control according to the following.