JP3581052B2 - ATM switch - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an ATM switch.
[0002]
[Prior art]
ATM switches are classified into input buffer type switches, output buffer type switches, common buffer type switches, and cross point buffer type switches according to the arrangement method of the buffers. Among them, the input buffer type switch and the cross point buffer type switch are suitable for large-capacity switches because the required memory speed is low and there is no need to increase the internal speed compared to the input line speed. It has a good performance. However, there are the following problems.
[0003]
Numerous transmission cell determination algorithms such as iSLIP (see N. McKeown et al., “The TinyTera: A Packet Switch Core”, IEEE Micro., Jan / Feb 1997) have been proposed for input buffer type switches. . An input buffer type switch using such an algorithm has to repeat the transmission cell determination algorithm several times within one cell time in order to obtain high switch throughput. However, since the one-cell time becomes shorter as the speed becomes higher, in the future ultra-high-speed switching network, the algorithm can be repeated only several times per one-cell time, and there is a problem that the throughput is significantly reduced.
[0004]
Further, the cross point buffer type switch requires an extremely large number of buffers. That is, since the cross point buffer type switch has a buffer for each cross point, if the number of ports is N, N × N buffers having a predetermined buffer size are required. It is clear that the number of ports N will be extremely large in future ultra-high-speed switches, and in such a case, there will be a problem that the number of necessary buffers will be extremely large, resulting in an increase in cost.
[0005]
Therefore, a configuration method combining an input buffer type switch and a cross point buffer type switch has been proposed (Y. Doi et al., "A High-Speed ATM Switch with Input and Cross-Point Buffers", IEEE Trans. Comm., March 1993). However, this switch has a problem that 100% throughput cannot be achieved because the input buffer section is constituted by a single FIFO buffer.
[0006]
[Problems to be solved by the invention]
An object of the present invention is that the required memory speed is low, unlike the conventional input buffer type switch and cross point buffer type switch, and that there is no need to increase the internal speed as compared with the input line speed. With the performance suitable for a large-capacity switch, and it is not necessary to repeat the cell transmission decision algorithm several times within one cell time unlike the conventional input buffer type switch, and a large number of switches like the conventional cross-point buffer type switch. It is an object of the present invention to provide an improved ATM switch which does not require any buffer.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, an ATM switch according to the present invention includes a plurality of output ports, a plurality of input ports each having a logical buffer corresponding to each of the output ports, and a logical buffer for each of the plurality of input ports. A cross-point section having a cross-point buffer provided at a cross-point position between the output port and the output port; storing cells input to the input port in a logical buffer; An ATM switch for reading out to a buffer and outputting from a cross point buffer via an output port, wherein the cross point unit has means for notifying the input port of queue length information of the cross point buffer; Based on the queue length information notified from the crosspoint section, the queue If it is determined that there is one shortest cross point buffer, the logical buffer corresponding to the cross point buffer is set as the logical buffer to be read, and if it is determined that there are a plurality of cross points with the shortest queue length. Means for setting a logical buffer having the longest wait time of a cell stored in the logical buffer among a plurality of logical buffers corresponding to the cross point buffer as a logical buffer to be read; and Means for reading a cell into a cross point buffer corresponding to the logical buffer.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a main part in an embodiment of an ATM switch according to the present invention. In the figure, 1 is an input port, 2 is an input buffer section, 3 is a cross point section, 4 is a cross point buffer section, and 5 is an output port.
[0012]
In the input buffer unit 2, the time counting unit 21 outputs the current time to the time information adding unit 22, and the time information adding unit 22 outputs the current time output from the time counting unit to the cell arriving at the input port 1. , The cell identification unit 23 identifies the destination output port of the arriving cell, and inputs the cell to the corresponding logical buffer 24. The time reading unit 25 reads the time information given to the first cell of each logical buffer 24. The judging unit 26 determines the logical buffer 24 that sends out the cell from the information sent from the cross point unit 3 (Step 11 in FIG. 2). The control unit 27 extracts cells to be transmitted from the logical buffer 24 according to the determination of the determination unit 26.
[0013]
An example of the procedure in this case will be described with reference to FIG. FIG. 2 is a diagram showing an example of a procedure for reading cells from an input buffer to a cross point buffer. First, the vacant cross point buffer notifies the corresponding input port of the current queue length (step 11). The input port that has received the notification selects the cross-point part having the shortest queue length among the notified notification (step 12), and outputs cells from the input buffer corresponding to the selected cross-point part (step 15). If there are a plurality of cross-point portions having the shortest queue length (step 13), cells are output from the input buffer having the longest waiting time of the first cell among the input buffers corresponding to those cross-point portions (step 14). ).
[0014]
In the cross point buffer section 4, the queue length reading section 41 reads the queue length, and sends out queue length information to the input buffer section 2 when there is a free space in the cross point buffer 43 (step 11 in FIG. 2). The time reading unit 42 reads the time information of the first cell of the cross point buffer 43 and sends the information to the output port 5 (Step 16 in FIG. 3). In the output port 5, the determination unit 51 determines the next cross point to transmit the cell based on the information sent from the cross point buffer unit 4. The control unit 52 extracts cells to be transmitted from the cross point buffer 43 according to the determination of the determination unit 51.
[0015]
An example of the procedure in this case will be described with reference to FIG. FIG. 3 is a diagram showing an example of a procedure for reading a cell from a crosspoint buffer to an output port. First, the cross point buffer unit having cells in the cross point buffer notifies the corresponding output port of the waiting time of the first cell of the buffer (step 16). The output port selects the crosspoint portion having the longest waiting time among the notified crosspoint portions (step 17), and outputs cells from the selected crosspoint buffer portion (step 20). If there are a plurality of cross point portions having the longest waiting time (step 18), the cell is output from the buffer of the cross point portion having the smallest input port number among these cross point portions (step 19). .
[0016]
Next, a specific example of cell processing in the ATM switch of the present invention will be described with reference to FIGS. 4 (a), 4 (b) and 4 (c). In the figure, an input buffer (i, j) is a logical buffer for an output port j at an input port i, and a cross point buffer (i, j) is a cross point buffer at a cross point between an input port i and an output port j. It is. The input buffer (i, j) and the crosspoint buffer (i, j) correspond to each other. The number given to each cell indicates the time at which the cell arrived. The smaller the number, the longer the waiting time.
[0017]
[First time: in the case of FIG. 4 (a)]
The cross point buffers (1, 1) and (2, 1) notify the output port 1 of the waiting time of the first cell (step 16). In this example, the notification contents are 1 and 2, respectively. The output port 1 selects the cross point part having the longest waiting time from the notified ones. In the case of this example, the cross point buffer (1, 1) is selected (steps 17, 18). As a result, cells are transmitted from the cross point buffer (1, 1) (step 20). At the output port 2, cells are transmitted from the cross point buffer (2, 2) by the same procedure.
[0018]
Thereafter, the cross point buffers (1, 1) and (1, 2) notify the input port 1 of the current queue length (step 11). In this example, the notification contents are 0 and 1, respectively. The input port 1 selects the cross point part having the shortest queue length among the notified ones. In the case of this example, the cross point buffer (1, 1) is selected (steps 12, 13). As a result, cells are transmitted from the input buffer (1, 1) (step 15). At the input port 2, cells are transmitted from the input buffer (2, 2) by the same procedure. At this point, the states of the input buffer and the cross point buffer are as shown in FIG.
[0019]
[Second time: in the case of FIG. 4 (b)]
The cross point buffers (1, 1) and (2, 1) notify the output port 1 of the waiting time of the first cell (step 16). In this example, the notification contents are 3 and 2, respectively. The output port 1 selects the cross point part having the longest waiting time from the notified ones. In the case of this example, the cross point buffer (2, 1) is selected (steps 17, 18). As a result, cells are transmitted from the cross point buffer (2, 1) (step 20). At the output port 2, cells are transmitted from the cross point buffer (1, 2) by the same procedure.
[0020]
Thereafter, the cross point buffers (1, 1) and (1, 2) notify the input port 1 of the current queue length (step 11). In the case of this example, the notification contents are 1 and 0, respectively. The input port 1 selects the cross point part having the shortest queue length among the notified ones. In the case of this example, the cross point buffer (1, 2) is selected (steps 12, 13). As a result, cells are transmitted from the input buffer (1, 2) (step 15). At the input port 2, cells are transmitted from the input buffer (2, 1) by the same procedure. At this point, the states of the input buffer and the cross point buffer are as shown in FIG.
[0021]
[Third time: in the case of FIG. 4 (c)]
The cross point buffers (1, 1) and (2, 1) notify the output port 1 of the waiting time of the first cell (step 16). In this example, the notification contents are 3 and 3, respectively. The output port 1 selects the cross point part having the longest waiting time from the notified ones. In the case of this example, the cross point buffers (1, 1) and (2, 1) are selected (step 17). In this case, since there are a plurality of selected cross point portions (step 18), the cross point buffer (1, 1) having the smallest input port number is selected. As a result, cells are transmitted from the cross point buffer (1, 1) (step 19). At the output port 2, cells are transmitted from the cross point buffer (2, 2) by the same procedure.
[0022]
Thereafter, the cross point buffers (1, 1) and (1, 2) notify the input port 1 of the current queue length (step 11). In this example, the notification contents are 0 and 1, respectively. The input port 1 selects the cross point part having the shortest queue length among the notified ones. In the case of this example, the cross point buffer (1, 1) is selected (steps 12, 13). As a result, cells are transmitted from the input buffer (1, 1) (step 15). At the input port 2, cells are transmitted from the input buffer (2, 2) by the same procedure. Thereafter, cells are sequentially transmitted in the same procedure.
[0023]
【The invention's effect】
As described above, according to the present invention, as in the conventional input buffer type switch and cross point type switch, the required memory speed is low, and the internal speed is increased compared to the input line speed. It has the performance suitable for a large capacity switch, such as no need for it. On the other hand, the execution of the cell transmission decision algorithm within one cell time does not need to be repeated many times as in an input buffer type switch, and is performed only once. In addition, an improved ATM switch which does not require a large capacity unlike the cross point buffer type switch can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a main part in an embodiment of an ATM switch of the present invention.
FIG. 2 is a diagram showing an example of a procedure for reading a cell from an input buffer to a cross point buffer.
FIG. 3 is a diagram showing an example of a procedure for reading a cell from a cross point buffer to an output port.
FIG. 4 is a diagram illustrating a specific example of cell processing in the ATM switch according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Input port 2 Input buffer part 3 Cross point part 4 Cross point buffer part 5 Output port 21 Time count part 22 Time information giving part 23 Cell identification part 24 Logical buffer 25 Time reading part 26 Judgment part 27 Control part 41 Queue length reading part 43 Cross Point Buffer 42 Time Reading Unit 51 Judgment Unit 52 Control Unit

Claims (1)

A plurality of output ports, a plurality of input ports each having a logical buffer corresponding to each output port, and a crosspoint provided at a crosspoint position between each logical buffer and the output port of the plurality of input ports. And a cross point unit having a buffer. The cell input to the input port is stored in a logical buffer, read from the logical buffer to a cross point buffer in the cross point unit, and output from the cross point buffer via an output port. An ATM switch,
The cross point unit has means for notifying queue length information of a cross point buffer to the input port,
If the input port determines that one cross point buffer having the shortest queue length exists based on the queue length information notified from the cross point section, the input port reads the logical buffer corresponding to the cross point buffer as a read target. If it is determined that there are a plurality of cross points having the shortest queue lengths, of the plurality of logical buffers corresponding to the cross point buffer, the waiting time of the cell stored in the logical buffer is the longest. An ATM switch comprising: means for setting a logical buffer as a logical buffer to be read; and means for reading cells from the logical buffer to be read to a crosspoint buffer corresponding to the logical buffer.

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