JPH0358230B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image reading device, and more particularly to an image reading device having means for accumulating information on incident light.

The present invention is applied to an image reading unit of a facsimile machine or the like.

[Prior Art] FIG. 5 is a circuit diagram of a conventional image reading device.
However, here, the case of a photosensor array having nine photosensors will be taken as an example.

In the figure, three optical sensors E1 to E9 constitute one block, and three blocks constitute an optical sensor array. The same applies to the capacitors C1 to C9 and the switching transistors T1 to T9 corresponding to the optical sensors E1 to E9, respectively.

One electrode (common electrode) of each of the optical sensors E1 to E9 is connected to the power source 101, and the other electrode (individual electrode) is grounded via capacitors C1 to C9, respectively.

Further, individual electrodes having the same order within each block of photosensors E1 to E9 are connected to common lines 102 to 102 through switching transistors T1 to T9, respectively.
104.

In detail, the first switching transistors T1, T4, T7 of each block are connected to the common line 102.
Then, the second switching transistors T2, T5, T8 of each block are connected to the common line 103, and the third switching transistors T of each block are connected to the common line 103.
3, T6, and T9 are connected to the common line 104, respectively.

Common lines 102-104 are connected to amplifier 105 via switching transistors ST1-ST3, respectively.
It is connected to the.

Furthermore, the gate electrodes of the switching transistors T1 to T9 are connected in common for each block, and are connected to the parallel output terminals of the shift register 106, respectively. Since high level signals are sequentially output from the parallel output terminals of the shift register 106 at predetermined timing, the switching transistors T1 to T
9 is turned on sequentially for each block.

In addition, switching transistors ST1 to ST3
Each gate electrode is connected to the parallel output terminal of the shift register 107, and by sequentially outputting a high level from the parallel output terminal at a predetermined timing, the switching transistors ST1 to ST3 are sequentially turned on.

Furthermore, switching transistors ST1 to ST
The commonly connected terminals of the transistors 3 and 3 are grounded via the discharging switching transistor CT1, and the gate electrode of the switching transistor CT1 is connected to the terminal 1.
Connected to 08.

The operation of a conventional image reading device having such a configuration will be briefly described.

When light enters the optical sensors E1 to E9, the power supply 101 connects the capacitors C1 to C9 depending on the intensity of the light.
Charge is accumulated in the

Subsequently, the shift registers 106 and 107 sequentially output a high level at respective timings, and it is now assumed that a high level is output from the first parallel output terminals of both registers.

Then, the switching transistor ST1 connected to the switching transistors T1 to T3 of the first block and the common line 102 is turned on.
The charge stored in the capacitor C1 is input to the amplifier 105 through the switching transistor T1, the common line 102, and the switching transistor ST1, and is output as image information.

When the charge stored in the capacitor C1 is read out, a high level is applied to the terminal 108,
The switching transistor CT1 is turned on. Thereby, the residual charge in the capacitor C1 is transferred to the switching transistor T1, the common line 10
2. Completely discharged through the switching transistor ST1 and the switching transistor CT1.

Next, while keeping the first parallel output of shift register 106 at high level, shift register 1
07 is sequentially shifted to create a switching transistor.
ST2 and ST3 are turned on in order. As a result, the above reading and discharging operations are performed on the capacitors C2 and C3, and the information stored therein is sequentially read out.

When the reading of the information of the first block is completed in this way, the shift register 106 is sequentially shifted, and the reading of the information of the second and third blocks is performed in the same manner as described above.

In this way, the information stored in the capacitors C1 to C9 is serially read out and output from the amplifier 105 as image information.

Since the conventional image reading device shown in FIG. 5 includes capacitors C1 to C9 for storing charge, it is possible to increase the output signal.

In addition, optical sensors E1 to E9, capacitors C1 to
C9 and switching transistors T1-T9
When these are formed on the same substrate using a thin film semiconductor, there are advantages such as being able to reduce the number of connection points with external circuits.

However, thin film transistors (TFTs) have a characteristic of high resistance in the on state. For this purpose, the capacitances of capacitors C1 to C9 and the corresponding switching transistors T1 to
The time constant determined by the resistance value of T9 becomes large, and due to the parasitic capacitance and resistance of the common lines 102 to 104 and the switching transistors ST1 to ST3, the discharge time of the capacitors C1 to C9 disappears. Therefore, such conventional image reading devices have a problem in that it takes time to read information.

Furthermore, the conventional image reading device has a capacitor C
For each of No. 1 to C9, a discharging operation is required after reading each time, so there is also the problem that sufficiently high speed operation cannot be performed.

[Object of the Invention] The present invention has been made in view of the above-mentioned conventional problems, and its object is to provide an image reading device that has a simple configuration and is capable of high-speed operation.

[Summary of the Invention] In order to achieve the above object, the present invention includes a plurality of photoelectric conversion elements, and an electric charge that is electrically connected to each of the plurality of photoelectric conversion elements and that corresponds to each output signal of the photoelectric conversion element. a plurality of first accumulating means for accumulating a plurality of first accumulating means, a desired number of the first accumulating means forming one block, a plurality of blocks forming one group, and a plurality of first accumulating means for simultaneously taking out the charges accumulated in the first accumulating means for each block. 1 switch means, said first storage means is an image reading device in which each group in the same order is connected to the same common line through said first switch means, said first storage means a first discharging switch means electrically connected to the means for simultaneously discharging the residual charges of the first storage means one block at a time; a plurality of second storage means connected to the common line for storing the charges; and a plurality of second storage means electrically connected to the second storage means for simultaneously discharging residual charges in the second storage means for each block. The present invention is characterized by comprising: a second discharge switch means; and a serial output means connected to the common line and for time-sequentially taking out the charge stored in the second storage means as a signal.

More specifically, the present invention includes a first discharging switching transistor connected in parallel with each of the first capacitors for photocurrent accumulation, and a second discharging transistor capable of accumulating information for a plurality of blocks.
a discharging switching transistor that is connected in parallel with each of the second capacitors and operates for each block, and a switching transistor that extracts information for each block from the second capacitor in time series. It is characterized by

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of an image reading device according to the present invention. However, here, we will take as an example a case where there are 12 optical sensors.

In the same figure, an optical sensor E1, which is a photoelectric conversion element,
-E12, as will be described later, three blocks constitute one block, and two blocks constitute one group. For example, the optical sensors E1-E3 are the first block, the optical sensors E4-E6 are the second block,
Photosensors E1 to E6 are the first group.

Capacitors C1 to C12 for photocurrent accumulation are connected correspondingly to the optical sensors E1 to E12, respectively;
Discharge switching transistors DT1 to D12 serving as first discharge switching means;
Switching transistor T1 as switching means
The same applies to ~T12.

One electrode (common electrode) of each optical sensor E1 to E12 is connected to a power source 101, and a constant voltage is applied thereto.

The other electrodes (individual electrodes) of the optical sensors E1 to E12 are connected to switching transistors T1 to T, respectively.
12 and grounded via capacitors C1 to C12, respectively, and further connected to discharging switching transistors DT1 to DT1 to ground.
It is grounded via DT12.

The gate electrodes of the switching transistors DT1 to DT12 are commonly connected in groups of three, that is, in each block, and are each connected to parallel output terminals S13 to S16 of the shift register 210.
Since high level signals are sequentially output from the parallel output terminals S1 to S4 at predetermined timing, the switching transistors DT1 to DT12 are sequentially turned on for each block.

The gate electrodes of the switching transistors T1 to T12 are also commonly connected for each block, and each is connected to the parallel output terminals S1 to S4 of the shift register 201.
It is connected to the.

The other main electrodes of the switching transistors T1-T12 in the same order in each group are connected to common lines 202-207, respectively.
For example, the second switching transistors T2 and T8 in each group are connected to common line 203.

The common lines 202-207 are connected to the amplifier 105 via switching transistors ST1-ST6, respectively.
is connected to the input terminal.

Switching transistors ST1 to ST3 and
Each gate electrode of ST4 to ST6 is connected to the parallel output terminals S5 to S10 of the shift register 208 and shift register 209, respectively, and a high level is sequentially output from these parallel output terminals at a predetermined timing, so that the switching transistor ST
1 to ST6 are sequentially turned on.

In FIG. 1, the serial output means includes switching transistors ST1 to ST6 and shift registers 208 and 209, as described above.

Common lines 202 to 207 are connected to capacitors CC1 to CC6 for storing transfer charges, which are second storage means, respectively.
Discharge switching transistors CT1-- which are grounded through the transistors and serve as second discharge switch means
Grounded via CT6.

The capacitance of capacitors CC1 to CC6 is capacitor C
Set it to be sufficiently larger than that of 1 to C12.

Three gate electrodes of each of the switching transistors CT1 to CT6 are connected in common, and are connected to terminals S11 and S12, respectively. Therefore, by applying a high level to the terminal S11 or S12, the switching transistors CT1 to
CT3 or CT4 to CT6 are turned on, and common lines 202 to 204 or common lines 205 to 207
will be grounded.

Next, the operation of this embodiment having such a configuration will be explained using the timing chart shown in FIG.

First, when light enters the optical sensors E1 to E12, charges are accumulated in the capacitors C1 to C12 from the power source 101 according to the intensity of the light.

First, a high level is output from the parallel output terminal S1 of the shift register 201, and the switching transistors T1 to T3 are turned on [FIG. 2a].

By turning on the switching transistors T1 to T3, the capacitor C1 of the first block
The charges accumulated in ~C3 are transferred to capacitors CC1~CC3, respectively.

When the information of the first block is transferred, a high level is output from the output terminal S2 of the shift register 201, and the switching transistor T
4 to T6 are turned on [FIG. 2b].

This causes capacitor C4 of the second block to
The charges accumulated in ~C6 are transferred to capacitors CC4~CC6, respectively.

In parallel with the transfer operation of the second block, high level signals are sequentially output from the output terminals S5 to S7 of the shift register 208 [Fig. 2 e to g].

This allows the switching transistor ST
1 to ST3 are sequentially turned on, and the capacitor CC
The optical information of the first block transferred to and stored in CCs 1 to CC3 is read out in time series through an amplifier 105.

When the information of the first block is read, the terminal S
A high level is applied to the transistor 11, and the switching transistors CT1 to CT3 are simultaneously turned on [FIG. 2k].

As a result, the transfer charge storage capacitor CC
The residual charges of 1 to CC3 are completely discharged.

In parallel with the above readout and transfer charge discharge operations [Fig. 2 e to g and k], the shift register 2
A high level is output from the 10 parallel output terminals S13 [Fig. 2 m].

This allows the switching transistor DT
1 to DT3 are turned on, and the residual charges in the photocharge storage capacitors C1 to C3 of the first block are completely discharged.

In this way, the second block of information is transferred, the first
The operations of reading block information, discharging residual transfer charges, and discharging residual photocharges are performed in parallel.

When these operations are completed, the shift register 201 shifts and a high level is output from the parallel output terminal S3 [FIG. 2c].

This causes the switching transistor T7
~T9 is turned on, and the charges stored in the capacitors C7 to C9 of the third block are transferred to the capacitors CC1 to CC3.

In parallel with this third block information transfer operation, the parallel output terminals S8 to S8 of the shift register 209
A high level is sequentially output from S10 [Fig. 2 h to j].

This allows the switching transistor ST
4 to ST6 are sequentially turned on, and the capacitor CC
The information of the second block transferred and stored in CCs 4 to CC6 is read out in chronological order.

When the information of the second block is read, the terminal S
A high level is applied to the transistor 12, and the switching transistors CT4 to CT6 are simultaneously turned on [FIG. 2l].

As a result, the transfer charge storage capacitor CC
The residual charges of 4 to CC6 are completely discharged.

In parallel with the above-mentioned reading of the information of the second block and discharging of the residual transfer charge, a high level is output from the parallel output terminal S14 of the shift register 210 [Fig. 2n], and the switching transistor
ST4 to ST6 are simultaneously turned on.

As a result, the capacitor C4 for photocharge storage
~C6's residual charge is discharged.

Similarly, in parallel with the transfer of the information of the fourth block, the following operations are performed: reading the information of the third block, discharging the residual transfer charge, and discharging the residual photocharge of the third block. 4
The reading of the information of the block and the discharge operation of the residual transfer charge and the residual photocharge are performed in parallel with the transfer of the information of the first block.

The operations described above are repeated, and the optical information is read out in time series.

In this way, by transferring the information stored in the capacitors C1 to C12 block by block, the transfer and discharge operations, which were conventionally required 12 times for each block, can be reduced to 4 in this embodiment. This can shorten the overall reading time.

In addition, in parallel with the information transfer operation of the next block, the information of the previous block can be read and the residual transfer charge and residual photocharge can be discharged, so the overall operating time can be further shortened. .

In this embodiment, the 12 optical sensors are divided into four blocks, but the invention is not limited to this. From this embodiment, a desired number of optical sensors can be easily divided into a desired number of blocks.

FIG. 3 is a circuit diagram of a third embodiment of the present invention. However, the configurations of the optical sensors E1 to E18, the capacitors C1 to C18 for photocharge accumulation, the switching transistors DT1 to DT18 for photocharge discharge, and the switching transistors T1 to T18 are as follows.
Since it is substantially the same as in FIG. 1, and only the number has increased from 12 to 18, the explanation will be omitted. In addition, the third
In the figure, some circuits are omitted due to space limitations.

In this embodiment, three blocks form one group, and the main electrodes of the switching transistors having the same order in each group are connected to the common line 40.
2 to 410.

The gate electrodes of the switching transistors T1-T18 are connected in common for each block, and are connected to the parallel output terminals B1-B6 of the shift register 401, respectively.

Similarly, each gate electrode of the switching transistors DT1 to DT18 is connected to the shift register 40.
2 parallel output terminals S13 to S18.

In addition, the common lines 402 to 410 are grounded via capacitors CC1 to CC9 for transferring charge accumulation, and are connected to switching transistors CT1 to CT for discharging.
It is grounded via 9.

Switching transistors CT1 to CT for discharge
Three gate electrodes of No. 9 are connected in common,
Each is connected to terminals H1 to H3.

The common lines 402-410 are connected to the amplifier 105 via switching transistors ST1-ST9, and are connected to the amplifier 105 via switching transistors ST1-ST9.
The gate electrodes of shift registers 411 to 413
are connected to the parallel output terminals D1 to D9, respectively.

Next, the operation of this embodiment having such a configuration will be briefly explained using the timing chart shown in FIG.

First, a high level is output from the output terminal B1 of the shift register 401, and the switching transistors T1 to T3 are turned on [FIG. 4a].

By turning on the switching transistors T1 to T3, the capacitor C1 of the first block
The charges accumulated in ~C3 are transferred to capacitors CC1~CC3, respectively.

When the first block of information is transferred, a high level is output from the output terminal B2 of the shift register 401, and the switching transistor T
4 to T6 are turned on [FIG. 4b]. As a result, the charges accumulated in the capacitors C4 to C6 of the second block are transferred to the capacitors CC.
4 to CC6.

In parallel with the transfer operation of the second block, high level signals are sequentially output from the output terminals D1 to D3 of the shift register 411 [FIG. 4 g to i].

This allows the switching transistor ST
1 to ST3 are sequentially turned on, and the capacitor CC
The optical information of the first block transferred to and stored in CCs 1 to CC3 is read out in time series through an amplifier 105.

Furthermore, in parallel with the transfer operation of the second block,
A high level is output from the terminal S13 of the shift register 402 [FIG. 4s], the switching transistors DT1 to DT3 are turned on, and the residual photocharges in the capacitors C1 to C3 of the first block are discharged.

When the information of the first block has been read and the residual photocharge has finished discharging, a high level is applied to the terminal H1, and the switching transistor CT1
~CT3 are simultaneously turned on [FIG. 4p], and the residual charges in the capacitors CC1 to CC3 are completely discharged.

In parallel with this discharging operation, the shift register 40
A high level is output from the output terminal B3 of 1 [FIG. 4c].

This causes the switching transistor T7
~T9 is turned on, and the charges stored in the capacitors C7-C9 of the third block are transferred to the capacitors CC6-CC9.

In parallel with the above-mentioned discharge operation and transfer operation, a high level is sequentially output from the output terminals D4 to D6 of the shift register 412 [FIG. 4 j to l], the switching transistors ST4 to ST6 are sequentially turned on, and the second Block information is read out in chronological order.

Furthermore, in parallel with the above discharge operation and transfer operation, a high level is output from the output terminal S14 of the shift register 402, and the residual photocharges in the capacitors C4 to C6 of the second block are discharged [FIG. 4t]. It will be done.

Next, the transfer of the information of the fourth block (Fig. 4 d), the time-series readout of the information of the third block [Fig. [Fig. 4 q] and the discharging operation of the residual photocharges in the capacitors C7 to C9 [Fig. 4 u] are performed in parallel, and in the same manner,
Optical information from optical sensors E1 to E18 is repeatedly read.

As described above, in this embodiment, since one group is made up of three blocks, the information transfer operation of a certain block, the read operation of the previous block, the discharge operation of residual photocharge, and the operation of the previous block are performed. This operation can be performed in parallel with the discharging operation of the remaining transferred charges, and high-speed operation is possible as a whole.

Furthermore, capacitors C1-18 and CC1-
CC6 discharge can be performed independently,
You also have enough time.

[Effects of the Invention] As described above in detail, the image reading device according to the present invention includes a discharge switching means corresponding to the first storage means for storing photocharges, and a second storage means capable of storing information for a plurality of blocks. and discharge switch means corresponding to each of the second storage means, and serial output means for extracting information from the second storage means in time series.

The present invention has a second storage means that can store information for a plurality of blocks, so that it is possible to transfer, read,
Each discharge operation can be performed in parallel, and the overall operation time can be shortened.

Further, each operation of transfer, readout, and discharge can be performed with sufficient time, and each operation can be performed reliably, improving the reliability of image reading.

Further, since the discharge switch means is provided corresponding to each of the first storage means and the second storage means,
The first and second storage means can be completely discharged at high speed, and the influence of residual charges can be completely eliminated.

Furthermore, since the information is transferred block by block from the first storage means to the second storage means, the time required for the transfer can be shortened, and the overall operating speed can be further improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of an image reading device according to the present invention, FIG. 2 is a timing chart for explaining the operation of this embodiment, and FIG. 3 is a circuit diagram of a third embodiment of the present invention. 4 is a timing chart for explaining the operation of the third embodiment, and FIG. 5 is a circuit diagram showing an example of a conventional image reading device. E1-E18... Optical sensor, C1-C18...
Photocurrent storage capacitor, T1 to T18, ST1
~ST9...Switching transistor, DT1
~DT18...Switching transistor for discharge, CT1-CT9...Switching transistor for discharge.

Claims (1)

[Scope of Claims] 1. A plurality of photoelectric conversion elements, and a plurality of first storage means that are electrically connected to each of the plurality of photoelectric conversion elements and accumulate charges according to each output signal of the photoelectric conversion element. , a desired number of the first accumulating means are grouped into one block, and a first switch means for simultaneously taking out the charges accumulated in the first accumulating means for each block; The first storage means is an image reading device in which each group in the same order is connected to the same common line through the first switch means, and is electrically connected to the first storage means to read the first block. a first discharging switch means for simultaneously discharging the residual charges of the first storage means; and a first discharging switch means for discharging the residual charges of the first storage means; a plurality of second storage means connected to each other; a second discharging switch means electrically connected to the second storage means for simultaneously discharging the residual charge of the second storage means for each block; An image reading device comprising: serial output means connected to the common line and for extracting charges accumulated in the second storage means as a signal in time series.