JPH0358180B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and particularly to the formation of a guard ring layer in a method for separating each element.

Conventionally, when separating each element in a semiconductor integrated circuit device, especially a MOS type semiconductor integrated circuit device,
A highly concentrated impurity layer (guard ring impurity layer) of the same conductivity type as the substrate is formed on the substrate plane, and a thick oxide film (field oxide film) is formed using selective oxidation on the impurity layer.
Guard ring areas have been used. In this method, the field oxide film and the guard ring impurity layer penetrate into the device region during selective oxidation, which is disadvantageous for ultra-highly integrated devices.

One way to solve this problem is to separate the element region and the guard ring region perpendicularly to the main surface of the substrate. In this vertical separation structure, International Electron Devices Meeting
As reported on page 380 (1981), undesired lateral channels are formed on the vertically separated sides, leading to cut-off of the device.
adversely affect characteristics.

Also, one method to realize the vertical separation structure is
International Elctron Devices Meeting, page 384 (1981). In this method, an impurity layer of the same conductivity type as the substrate for preventing side channels is formed by ion implantation at the same time as a low-level high concentration guard ring impurity layer. In this method, if the substrate has a vertical side surface structure without an inclination placed at an arbitrary location within the surface of the substrate, it is difficult to introduce an impurity layer having the same conductivity as the substrate to prevent a side channel on the side surface. be. On the other hand, if a guard ring layer is simultaneously formed on the lower part and the side part by thermal diffusion, the surface concentration in the lower part cannot be high, which requires an isolation structure with a long distance between elements, making it unsuitable for high integration. do not have.

An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device having a preferable method for forming a guard ring layer for channel prevention.

The present invention is characterized by forming an oxide film on one main surface of a semiconductor substrate of one conductivity type, selectively forming a photoresist layer on the oxide film, and using the photoresist layer as a mask to form the oxide film on the main surface of a semiconductor substrate of one conductivity type. The film is selectively etched away, and the semiconductor substrate is selectively removed using the photoresist layer as a mask to form a high surface area under the photoresist layer and a low surface area surrounding the semiconductor substrate. a step of forming;
forming a high-concentration guard ring layer of one conductivity type on the lower surface portion of the semiconductor substrate by implanting ions of one conductivity type using the photoresist layer as a mask, and then removing the photoresist layer. a step of thermally diffusing impurities of one conductivity type to form a low concentration guard ring layer of one conductivity type on a side surface between the high surface portion and the low surface portion of the semiconductor substrate; a step of forming an insulating layer on a low surface portion of the semiconductor substrate to have approximately the same height as the high surface portion; and a step in which source and drain regions of opposite conductivity are in contact with the low concentration guard ring layer; The present invention provides a method of manufacturing a semiconductor integrated circuit device in which the high surface portion is formed so as not to contact the high concentration guard ring layer. According to the present invention, a guard ring layer having a surface concentration suitable for each of the side surface portion and the lower surface portion can be formed. Since the guard ring layer on the side surface has a low concentration, the breakdown voltage of the source and drain regions will not be undesirably lowered. On the other hand, since the guard ring layer in the lower surface area has a high concentration, even if the distance between elements is shortened, leakage current will not occur due to parasitic channels, making it suitable for high integration. Furthermore, in the present invention, the photoresist layer is triple-used as a mask for removing an oxide film, a mask for etching the semiconductor substrate, and a mask for ion implantation when forming a guard ring layer in the lower surface area. are doing. Therefore, even if two steps are required to form the guard ring layer as in the present invention, the overall number of alignment steps does not increase.

Next, an embodiment of the present invention will be explained with reference to the drawings.

As shown in FIG. 1, an oxide film 11 is formed on one main surface of a P-type silicon substrate 10 with a specific resistance of 10 to 15 Ω·cm.
700〓 Grow, apply photoresist material 12, open the area that will become the guard ring using photolithography, etch the exposed oxide film with a reaction sputtering device using CF ₄ gas, and continue using the same device.
The exposed surface of the silicon substrate is etched by 0.8 μm using Ccl ₄ gas to create a vertical isolation structure, resulting in the structure shown in FIG.

Thereafter, impurities of the same conductivity type as the substrate are ion-implanted at an acceleration energy of 100 Kev and a dose of 10 ¹² to 10 ¹³ ions/cm ² using the photoresist material 12 as a mask material to form a guard ring impurity layer 13 in the lower part of the substrate surface. After the photoresist material 12 is removed, the upper surface and side surfaces of the convex-shaped surface region adjacent to the lower portion are covered with the oxide film 11 as a mask to prevent impurities from diffusing into the side surfaces. Impurities of the same conductivity type as the substrate are thermally diffused in a shallow and low concentration only in the surface region 10a to form a side channel prevention impurity layer 14, and the impurity glass layer deposited by the thermal diffusion is removed to obtain the structure shown in FIG. .

Next, an oxide film 15 that will become a field insulating film is grown to a thickness of 1.0 μm using a plasma method or vapor phase growth, and then heat treated in an O ₂ atmosphere at 900°C, and a photoresist material 16 is applied, resulting in the structure shown in FIG. get. Here, the photoresist material is coated thinly on the high parts and thickly on the low parts of the uneven substrate surface to smooth the surface and use it for subsequent etching of the entire surface.

The entire surface of the smoothed surface is etched using a reactive sputtering device using a CF ₄ gas until the oxide film 11 is exposed, as shown in FIG. During this reactive sputter etching, it is desirable to select etching conditions such as a gas that etches the photoresist material and the deposited oxide film at approximately the same etching rate.

After removing the remaining thin oxide film 11, a gate oxide film 17 and a polycrystalline silicon gate electrode 1 are formed according to a normal silicon gate MOS manufacturing method.
8. After forming a substrate for forming a source and a drain, a reverse conductivity type impurity layer 21, and an interlayer insulating film 19 and opening an electrode extraction part, an Al wiring electrode 20 is formed to form a MOS type semiconductor integrated circuit device as shown in FIG. get. Although FIG. 6 shows a cut plane in a direction perpendicular to the channel, FIG. 7 shows a cut plane parallel to the channel.

As explained above in this invention, only the shallow low concentration impurity layer is in contact with the channel region or the substrate and the opposite conductivity type region, and this region is completely separated from the high concentration guard ring impurity layer. Even if the guard ring region is made very narrow, its impurity concentration can be freely selected, and since a side channel prevention impurity layer is introduced, an ultra-high density semiconductor integrated circuit device can be obtained.

In the above embodiments, the conductivity types of the semiconductor substrate and various semiconductor impurity layers can be changed as necessary, and the oxide film 1 can be changed as necessary in FIG.
Another mask material, such as a silicon nitride film, may be inserted between the photoresist material 1 and the photoresist material, and the formation of the side channel prevention impurity layer shown in FIG. It may be diffusion. Further, the photoresist material 16 described in FIG. 4 may be a material, such as a silica film, which has a surface smoothing effect and has an etching rate substantially equal to that of the deposited oxide film 15 in a subsequent whole-surface etching device.

[Brief explanation of drawings]

1 to 6 are cross-sectional views perpendicular to the channel of a MOS type semiconductor integrated circuit device in each step of an embodiment of the present invention, and FIG. 7 is a cross-sectional view parallel to the channel of the device. FIG. In the figure, 10...Semiconductor substrate, 11...Mask material oxide film, 12...Mask material photoresist, 13...Guard ring impurity layer, 14...Side channel prevention impurity layer, 15...Field insulation Oxide film, 16... Photoresist material for surface smoothing, 17... Gate oxide, 18... Polycrystalline silicon gate electrode, 19... Interlayer insulation oxide film, 20
. . . Al wiring electrode, 21 . . . source and drain impurity layer.

Claims (1)

[Claims] 1. A step of selectively etching a semiconductor substrate of one conductivity type to form a high surface portion and a surrounding low surface portion on the semiconductor substrate, and etching the semiconductor substrate with the high surface portion masked. By ion-implanting impurities of one conductivity type and thermally diffusing the impurities of one conductivity type, a first guard ring layer of high impurity concentration of one conductivity type is formed in the low surface portion of the semiconductor substrate. forming a second guard ring layer having an impurity concentration lower than that of the first guard ring layer on a side surface between the low surface portion and the high surface portion; a step of forming an insulating layer to have a shape that is approximately the same height as the high surface portion; source and drain regions of opposite conductivity types are in contact with the second guard ring layer having a low concentration;
A method for manufacturing a semiconductor integrated circuit device, characterized in that the first guard ring layer is formed from the higher surface portion so as not to be in contact with the first guard ring layer having a high concentration.