JPH0357078A - Automatic logic circuit conversion system - Google Patents

Abstract

PURPOSE:To increase the speed and to improve the quality by dividing first logic circuit data to partial circuits by a circuit dividing means. CONSTITUTION:An intermediate file 4 where intermediate results of conversion of circuit data are described and a automatic circuit dividing and restoring means 7 which divides circuit data before conversion to partial circuits and restores the data in accordance with rules are provided. Circuit data before conversion stored in an input file 2 is read into a circuit data input/output means 6 and is divided by the automatic circuit dividing and restoring means 7. That is, first logic circuit data is divided to partial circuits to set a working memory 5 to the capacity corresponding to the size of partial circuits. Thus, the time required for calculation and the memory capacity of the working memory 5 are reduced, and at least one of the area of the circuit and the delay is evaluated to attain the conversion quality equal to that of manual conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit 11 dynamic conversion system for converting the configuration of a logic circuit, and particularly to speeding up and improving the quality thereof.

[Conventional technology]

FIG. 9 is a block diagram showing the structure of a conventional logic circuit automatic conversion system. The circuit data before conversion is stored in input file 2. The data is stored in the logic circuit converter 1
The data is applied to the working memory 5 via the circuit data input/output means 6 within the circuit. The working memory 5 stores this data and performs conversion processing to be described later. Circuit conversion rules in IF-THEN format used in this conversion process are stored in the rule base 8. Furthermore, the interpolation means 9 converts the circuit data in the working memory 5 and the circuit conversion rules in the rule base 8 into χ·! We perform matching that responds to
One rule is selected from a set of matching rules, and the corresponding circuit data is converted.

Next, the operation will be explained. Figure 10 shows the above-mentioned
3 is a flowchart showing circuit conversion processing by the logic circuit automatic conversion system shown in the figure.

First, in step S30, the circuit data before conversion stored in the input file 2 is transferred to the circuit data input/output means 6.
It is exclusively read into the working memory 5 via the . Working memory 5 has a memory capacity corresponding to this circuit data.

In the next step S31, the circuit data in the working memory 5 and the circuit conversion rules in the rule base 8 are collated by the interleaving means to perform matching to extract possible rules.

ffi 1. FIG. 1A to FIG. 11H are diagrams showing examples of circuit conversion rules stored in the rule base 8. These rules execute the following processing when the circuit data satisfies the conditions in the IF clause.

FIG. 11A and FIG. 11B are diagrams showing examples of If conversion rules. In FIG. 11A, OR gates +- 51 and 52 are OF-combined and replaced by OR gate 53. In FIG. 11B, the inverter 71 is merged with the NOR gate 61 to form the OR gate 54, and the input stage of the NAND gate 81 is simplified.

FIG. 11C and FIG. 11D are diagrams showing examples of macro allocation rules. In FIG. 11C, a macro cell 101 including an AND gate 91 and a NOR gate 62 is constructed. In FIG. 11D, macrocell 102 is constructed which includes AND gates 92, 93 and NOR gate 63, and further includes AND gate 94 which functions as a buffer by applying power supply voltage vcc to one of its inputs. macrocell 1
01 and 102 are basic elements that can be realized in semiconductor technology at the actual manufacturing stage, and this conversion rule is mainly aimed at reducing the area and standardizing the manufacturing process.

FIG. 11E and FIG. 11F are diagrams showing examples of optimization rules. In FIG. 11E, inverters 72 and 73 arranged in parallel have been merged, leaving only inverter 72. In FIG. 11F, the signal line S2 connected to the output terminal Q of the flip-flop 111 via the inverter 74 is directly connected to the inverted output terminal -rQC. This optimization of output polarity eliminates the inverter 74. Note that the signal line S1 connected to the output terminal Q is not changed.

FIG. 11G and FIG. 11H are diagrams showing the same design constraint rules. At the 110th ffl, since the loads 121 and 122 are larger than the load driving capacity of the inverter 75, the inverter 76 is added/Jl1.

In FIG. 11H, the total load of inverter 77 and load 123 is larger than the load driving capacity of AND gate 95, so inverter 78, which has a larger load driving capacity than AND gate 95, is added to drive load 123. There is. As described above, this rule adds elements or distributes loads as necessary so as to satisfy the constraints on electrical drive capability indicated by the fan-out of each element.

In step S32, the ink printer 9 determines whether any of the circuit conversion rules described above matches the circuit data. Conditions for application of the circuit conversion rules are written in the IF clause so that there will be no contradiction in phase conversion. Circuit conversion rules are applied to circuit data that satisfies these conditions.

If no such circuit data exists, step S
Proceed to step 35 and store the circuit data at that time in working memory 5.
The circuit data is written to the output file 3 via the circuit data input/output means 6.

If there is circuit data to which the circuit conversion rules can be applied in step S32, all corresponding rules are applied. Usually, there are multiple rules that can be matched,
This is called a conflict set.

In step 333, the interpreter 9 evaluates the weights added to the rules of the competition set and the circuit patterns of conversion antagonists by those rules, and selects one rule from the rules of the competition set. Extinguish. In step S34, the rule selected by the competition resolution is executed in the interpreter means 9 to rewrite the circuit data in the working memory 5.

After converting the circuit data in step S34, the process returns to step 531, and further matching circuit conversion rules are applied to the converted circuit data. The circuit conversion rule is completely executed through this loop, and if it is determined in step S32 that no further conversion can be performed, the circuit data at that time is transferred from the working memory 5 to the conversion data input/output means 6 in step 335. It is written to output file 3 via

[Problem to be solved by the invention]

Is the conventional logic circuit automatic conversion system as described above? ,I
Since the circuit data has to be stored all at once in the working memory 5, the time required for separate calculations and the memory capacity of the working memory 5 rapidly increase as the scale of the circuit to be calculated increases. There was a problem that the amount of electricity increased.

Furthermore, the conflict resolution method used in Inkbrita Sendan 9 only evaluated the weights assigned to each rule and the matched circuit shapes, but did not directly evaluate the product and delay. Therefore, there was a problem that conversion quality comparable to that of manual conversion could not be achieved.

This invention was made to overcome the above-mentioned problems, and it reduces the time required for calculation and the memory capacity of working memory, and also reduces at least one of the area of the route and the delay. The eleventh objective is to obtain an automatic logic circuit conversion system that can achieve conversion quality comparable to manual conversion.

[Means to solve the problem]

The automatic logic circuit conversion system according to the present invention is a system for converting input first logic circuit data to obtain second logic circuit data, and the system converts the first logic circuit data into the inside of the system. a logic circuit data input/output means for inputting and outputting the second logic circuit data to the outside of the system; and a circuit conversion rule used when converting the first logic +i'l path data to the second logic circuit data. a rule base to be stored; circuit dividing means for dividing the logic circuit represented by the first logic circuit data into partial circuits to which circuit conversion rules can be applied; and first logic circuit data provided for each partial circuit; The working memory that holds this matches the first logic circuit data of the partial circuit held in the working memory with the four-way conversion rule, and the second logical circuit data corresponding to the partial circuit according to the matched circuit conversion rule. , and if the matched circuit conversion rules conflict, second logic circuit data corresponding to the partial circuit to be generated according to the multiple competing circuit conversion rules is generated. and an interleaving means for resolving conflicts between matched circuit conversion rules by evaluating at least one of delay and area.

[Effect]

Since the circuit dividing means in this invention divides the first logic circuit data into partial circuits, the capacity of the working memory corresponds to the size of the partial circuits.

Further, the interleaving means in the present invention resolves conflicts in circuit conversion rules by evaluating at least one of the delay and area of the second logic circuit data.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
FIG. 1 is a block diagram showing the configuration of an automatic logic circuit conversion system according to an embodiment of the present invention.

This logic circuit automatic conversion system includes, in addition to the above-mentioned blocks not shown in FIG.
The automatic circuit dividing and restoring means 7 is provided for cutting out and restoring partial circuits from circuit data before conversion.

FIG. 2 is a diagram showing how circuit data is converted. This figure shows an example in which circuits on a board composed of individual TTL elements T described in an input file 2 are combined into one LSI and written to an output file 3.

TTL circuit 210 placed on Brin 1 board 200
is two AND gates 96, 97 and an OR gate 5
5, and the TTLliil path 220 corresponds to the signal line S
Inverter 79 with input signal line S4 as input and signal line S4 as output.
It corresponds to It is assumed that the signal line S3 is connected to the output of the OR gate 55. When a conversion process described later is performed on such circuit data, a macro cell 10 including two AND gates 96 and 97 and a NOR gate 64 is generated.
3 and an inverter 79a, one LSI 300 that outputs signal lines S3 and S4 can be formed.

3A and 3B are flowcharts showing circuit conversion processing by the logic circuit automatic conversion system shown in FIG. 1. FIG.

First, step S1. In O, input file 2
The circuit data before conversion stored in is read into the circuit data input/output means 6. In the next step s11, the circuit data read in step S10 is subjected to circuit division by the 11th path division and restoration means 7.

FIG. 4 is a diagram showing how the circuit is divided. The partial circuit obtained by circuit division is configured so that circuit conversion rules such as the marking rule, macro allocation rule, optimization rule, and design constraint rule shown in FIG. 11 described above can be applied. That is, each partial circuit must be configured to include each corresponding element so as not to divide the region matching these rules, and is determined based on the division rule Ill as shown below.

The first division rule is the rule nl that a group of elements connected by a signal line without branches is included in one partial circuit. In FIG. 4, for example, the input terminals 41 and 42, the AND gate 98, and the OR gate 56 are connected by a signal line without branching, so that they are included in two partial circuits.

Furthermore, as a second division rule, there is a rule that a signal line having a branch and a terminal connected to the signal line are included in one partial circuit. In FIG. 4, for example, the output of the OR gate 56 has a signal line that branches to the AND gate 99 side and the latch 112 side via the connection point N1, but the part of the signal line that includes this connection point N1 is included in one partial circuit. This signal line is connected to the AND gate 99 side and the latch 1 in order to show the connection relationship between the phases of the partial circuits.
Information is given that it is the 12th side. However, AND gate 99 and latch 112 are not included in the partial circuit including connection point N1 according to the first division rule.

According to the first and second division rules as described above, a partial circuit 230 including input terminals 41, 42, an AND gate 98, an OR gate 56, and a connection point N1 as shown in FIG. 4, for example, is formed. Similarly, the input terminal 44
, a partial circuit 2401 including AND gate 99 and output terminal 45, and a partial circuit 250 including latch 112 and output terminal 46 are formed.

In addition, the first and second division rules [1 as an exception are buffers, drivers, etc. that have one input terminal or input signal line and generate an output that depends only on that input. Regarding the completion of circuits such as inverters, the third division rule is to include the input signal line, the circuit element, and the output signal line of the circuit element in one partial circuit, regardless of whether or not the input signal line is branched. There is.

In FIG. 4, inverter 70 is combined with a circuit element having only one input signal line, and a partial circuit 260 including input terminal 43, connection point N2, and inverter 70 is formed.

Note that the first division rule is mainly used for the second and third division rules in order to maintain matching between the partial circuit and the macro allocation rule.
The division rules are provided primarily to maintain munching between partial circuits and the E1 constraint rules for checking fan-out and the like. Further, even if the division is performed as described above, matching between the partial circuit and the standardization rule and optimization rule is maintained.

In step 512, the circuit automatic division and restoration means 7 creates a graph for determining the conversion order of each partial circuit obtained as described above. FIG. 5 is a graph corresponding to the partial circuit of FIG.

The nodes in the graph correspond to subcircuits, and the nodes correspond to the signal flows between the subcircuits. The entire circuit data divided into partial circuits and its graph are stored in the intermediate file 4. The above processing completes the division process that precedes the conversion process.

Step S1. 3, in order to perform the conversion process, i is determined whether there is an unconverted partial circuit in the intermediate file 4.
11 is performed by the circuit automatic division and restoration means 7. If there is a partial circuit to which the conversion rule should be applied, the process proceeds to step 514; if not, the process proceeds to step S21 in FIG. 3B, where the tin path data is written.

In step 514, the automatic circuit division and restoration circuit 7 loads the partial circuits from the intermediate file 4 to the working memory 5 in order from the output side using the graph shown in FIG. When converting a circuit, it is necessary to know the load on the output signal line of the partial circuit, so the conversion process is performed from the output side. Further, along with this partial circuit extraction, the graph is updated as follows so that the circuit automatic division and restoration means 7 can recognize unconverted partial circuits.

FIG. 6 is a diagram showing how the graph shown in FIG. 5 is updated. As the partial circuits 240 and 250 are cut out, the corresponding nodes and related signal lines are deleted, and the graph is updated to show the unprocessed portions/subcircuits. Next, the subcircuits that can be cut out are shown by nodes that have no exit direction.

In the updated graph of FIG. 6, the partial circuit 23 {
) is the partial circuit to be cut out next. In this way, partial circuits whose output sides are known are sequentially designated as extraction targets.

In step S15, matching between the partial circuit and the circuit replacement rule is performed, similar to step S31 of the conventional art shown in FIG.

In step Si6 of FIG. 3B, as in step S32 of FIG. 10 described above, it is determined whether there is a matching rule. ．． Perform I1 disconnection.

If there is a matching rule, the process advances to step S17; otherwise, the process advances to step S320. In step S20, the partial circuit is swept out from the working memory 5 and returned to the intermediate file 4 via the circuit automatic division and restoration means 7.

Then step 3 in Figure 3A 1. Returning to step 3, it is determined whether or not to process the next partial circuit.

This processing loop performs conversion processing on all of the partial circuits.

In step 317, if there are a plurality of matching rules in the interpolator 9 and a competitive set is formed, an evaluation function is calculated for each matching rule. FIG. 7 is a diagram showing how the evaluation function is calculated. In the figure, a macro allocation rule for allocating a NOR game Gl and an AND gate G2 within a macro cell MCI is shown as an example of a rule in a competitive set of which there are 71. Note that these allocations within the contention set are selected to satisfy the required driving capacity as indicated by the set 51 constraint rules.

First, the area index a'ea(Gl
．． ) and the delay index delay (G 1. ) are written out from a memory (not shown) connected to the 1,000-stage inkblitter 9. These indices are predetermined 2
Each of the various 11-gate macro layouts with patterns on the 12-conductor substrate is known and stored in the memory, not shown. Similarly, the area index area (G2) and the delay index d of AND gate G2
elay (G2) is calculated. If the area is large, the area index area is large, and if the delay is large, the delay index de
The lay becomes larger. In addition, the area index area (
MC 1 ) and delay index delay (MCI)
is also known, and is written out from a memory (not shown) connected to the 1,000-stage intub-retarder 9.

Next, Toki style (1). Based on Equation (2), the load improvement degree AIR and the delay improvement degree DIR are determined.

A I R − (area (G 1 ) +are
a (G 2)) area (M C 1 )
- (1) DI R - fdelay
(G1) +dclay (G2)1-d
elay (MC 1)
・” (2) Formula (+), (2)
As shown in FIG. 3, when the sum of the areas of gates Gi and G2 in the case of medium gate macro allocation is larger than the area of the macro cell MC1, the area improvement degree AIR takes a positive value.

Also, the sum of the delays caused by gates Gl and G2 is the macrocell M
When the delay is larger than the delay of C1, the delay improvement degree DIR becomes a positive value. The larger these values, the greater the degree of improvement. Note that a negative value indicates deterioration of characteristics.

Comparing the macro allocation and the complex gate macro allocation, the area of the complex gate macro allocation is generally smaller, but there is a tendency for the delay to increase as the wiring density increases and the wiring capacity increases. Therefore,
There is a trade-off relationship between improving area and improving delay.

What is the trade-off between area and delay?
In order to eliminate
, , is defined.

F −k XAIR+kDXDIR ・(3)E
VA area coefficient k and delay coefficient kD are set to be constant, for example, kA+IcD- so as to express the trade-off relationship between area, delay, and A in equation (3).

In step 318, the evaluation function F obtained in step S17 is
The interleaving means 9 cancels the conflict angle q using the IEV. FIG. 8 is a diagram showing how conflict is resolved.

In FIG. 8, there are 3a rules R1, R2, and R3 as macro allocation rules that satisfy the design constraint rules for the combination of the NOR gate G1 and the AND gate G2. Respective rules Rl, R2, R3 apply to composite gate macrocells MCI, MC2 and +11 gate macrocell MC.
3 and a single gate AND gate G2. Further, it is assumed that the magnitude relationship between the area improvement degree AIR and the delay improvement degree DIR corresponding to each of the conversion rules R1 to R3 is given, for example, in Table 1 below.

Table 1 Next, in the conversion, the value of the parameter is determined according to the most important ``I''.The value of this parameter is inputted from the outside by, for example, an operator.For example, k
When the relationship A is +kD-1.0, if the purpose is to improve the area, then k -
1.0, kD- 0.0^, and if the purpose is to improve the delay, k-
0.0, kD- 1.0^. Note that if it is necessary to consider both characteristics, an intermediate setting between these^, such as k-kD-0.5, is used.

Table 2 is a table showing an example of the settings of the coefficients k 1 and k , and the selected cells and application rules based on the relationship in Table AD 1.

Table 2 In this way, circuit conversion rules are determined according to the purpose, and conflicts are resolved.

Furthermore, as shown below, design constraint rules may be used later to resolve conflicts. For example, for the purpose of improving the area, first extract the macro cell MCI with the minimum area fj, and then add processing to check the fan-out.

If the macrocell MCI satisfies both the area and fanout conditions, rule R1 is applied. As another example, assume that the macro cell M C 2 with the smallest delay is extracted with the delay reformed as I1. Then, it is determined whether macrocell MC2 satisfies the fan-out conditions. ν
, {If the conditions are not satisfied, the next combination of macro cell MC3 and game} G2 with the smallest delay is performed. If the driving capacity of macro cell MC3 is sufficiently large and the fan-out condition is satisfied, rule R3 is selected as the most applicable rule. In this way, conflicts can be resolved even if the application order of each rule is changed.

In step 519, the ink printer 9 rewrites the circuit in the working memory 5 by executing the rule selected as described above. Step L7]. 5
Return to , perform matching again, and form a new competitive set.

If there is no matching rule in step S16, the process proceeds to step S20, and after the circuit data in the working memory 5 is flushed out to the intermediate file 4 as described above, the process returns to step S313.

In the STEP sub 313, the lil path automatic division and restoration 1,000 steps 7 examines the graph, applies a statement to the remaining unconverted partial circuits, and repeats the above process. If there is no unconverted partial circuit, the process proceeds to step 521, where all circuit data in the intermediate file 4 is written to the output file 3, and the conversion process Pv is ended.

In addition, although the above embodiment shows a case where an existing 7Y circuit printed by TTL is converted into one LSI, the present invention is not limited to this, and for example, conversion from a CMOS LSI to an ECL LSI, etc. It may be a conversion from one LSI to another LSI using conductor technology, or it may be a conversion from an abstract gate circuit that does not depend on semiconductor technology to an LSI using a specific semiconductor technology. , the same effects as in the above embodiment can be achieved in such cases as well.

〔Effect of the invention〕

As described above, according to the present invention, the circuit dividing means divides the l-th logic circuit data into partial circuits, so that the capacity of the working memory corresponds to the size of the partial M path.

Furthermore, the interpreter in the present invention eliminates conflicts in circuit conversion rules by evaluating at least one of the delay and area of the second logic circuit data.

Therefore, it is possible to obtain a logic circuit conversion system that can reduce the time required for calculation and the memory capacity of the working memory, and can evaluate the circuit area and delay to achieve conversion quality comparable to manual conversion.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing 11 parts of an automatic logic circuit conversion system according to an embodiment of the present invention, FIG. 2 is a diagram showing how circuit data is converted, and FIGS. Flowchart showing the circuit conversion process according to one embodiment, FIG. 4 is a diagram showing the state of circuit division, FIG. 5 is a diagram showing a graph for determining the conversion order, and FIG. 6 is a diagram showing the graph shown in FIG. 5. Figure 7 is a diagram showing the state of update, Figure 7 is a diagram showing how the evaluation function is applied, Figure 8 is a diagram showing {・l child of conflict resolution, and Figure 9 is a diagram showing the groove of the conventional automatic logic circuit conversion system. FIG. 10 is a flowchart showing conventional circuit conversion processing; 1. Figure A ~ 1st. ．．
The IH diagram is a diagram showing how the circuit conversion rules are applied. In the figure, 5 is a working memory, 6 is a circuit data input/output means, 7 is a circuit "one-motion division restoring means, 8 is a rule base, 9 is an interleaving means, 23f), 240, 25
0,260 is a partial circuit. Note that the same reference numerals in each figure refer to the same or corresponding parts.

Claims (1)

[Claims] (1) Convert the input first logic circuit data and convert it into the second logic circuit data.
A system for obtaining logic circuit data, the logic circuit data input/output means inputting the first logic circuit data into the system and outputting the second logic circuit data to the outside of the system. a rule base that stores a circuit conversion rule used when converting the first logic circuit data into the second logic circuit data; and a rule base that stores a circuit conversion rule used to convert the first logic circuit data into the second logic circuit data; circuit dividing means that divides the circuit into partial circuits to which the partial circuit can be applied; a working memory that is given and holds the first logic circuit data for each partial circuit; 1 logic circuit data and the circuit conversion rule, generate the second logic circuit data corresponding to the partial circuit according to the matched circuit conversion rule, and perform the matched circuit conversion. When the rules conflict, the second circuit corresponding to the partial circuit to be generated according to the plurality of conflicting circuit conversion rules
an interpreter means for resolving conflicts between the matched circuit conversion rules by evaluating at least one of delay and area of logic circuit data.