JPH077142A - Semiconductor integrated circuit and design assisting system therefor - Google Patents

Abstract

PURPOSE:To enhance the performance of circuit without requiring new design of function cell by providing a path analyzing/extracting means, a parameter optimizing means, an auto placement and routing means, etc. CONSTITUTION:The design assisting system comprises a path analyzing/ extracting means 11 for calculating a delay time from the logical description of circuit and making a separation between an objective and path for optimization, and a parameter optimization means 12 for calculating the optimal values of the physical profile and wiring profile of a transistor and outputting the optimal values thus calculated. The system further comprises means 14 for synthesizing the symbolic layout of a described path, a compaction means 15 for determining a layout containing accurate placement information of transistor, restrictive information extracting means 16 for extracting layout and terminal information, and means 17 for effecting automatic placement and routing according to the layout of cell base. This system eliminates the need of new design of a function cell realizing the optimization at the stage of layout required for a high speed circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate array capable of embedding functional cells together with a designing method capable of obtaining an LSI of lower cost and higher performance in the case of designing an LSI circuit layout on a cell basis. Relates to a structure of a functional cell-embedded gate array including a functional support cell and a design support device for a semiconductor integrated circuit that enables an effective functional cell reuse method.

[0002]

2. Description of the Related Art A cell-based design method using standard cells can significantly reduce the time and labor required for layout design, as compared with the case where all LSI layout design is performed by manual design (full custom design).

In the following description, a cell-based layout design using standard cells will be described.

FIG. 12 shows a standard floor plan based on cells. Cell-based system LS
In the design of I, the standard cell (32) is used for the control circuit section that becomes a random logic description, and the functional cell block (42) for speeding up is used for the data path that requires high performance (for example, Multiplier, floating point arithmetic unit, etc.)
Is often used. Further, a functional cell block (41) for high integration is used for an on-chip cache, a register file, etc. which requires high integration.

In recent years, due to the development of logic synthesis tools, in the control circuit (control circuit section) for controlling instruction reading, decoding, operation instruction, etc., description in programming language or description in truth table is also used. And the logical description can be constructed. Since this control circuit unit is normally a random logic circuit, it is possible to use standard cells and mount them in the layout of the actual circuit by an automatic placement and routing program.

In the design method based on the cell base, since the standard cell has a fixed width that has already been optimized in units of basic cells, it is not easy to improve the circuit performance by optimizing the transistor width. . Therefore, the standard cell is not suitable for realizing a data path or the like that requires high speed, and this is realized by an independent functional cell.

In other words, the arithmetic unit forming the data path is
This high-speed calculation algorithm has been studied, and the speed can be increased by using this calculation algorithm.
Further, the speed can be increased by optimizing the logic circuit, transistor configuration, and shape. In addition, the layout of the data path often has high regularity. Therefore, in the arithmetic unit, as a block having an independent function, the design from the logic circuit design to the layout design is often performed manually.

In the cell-based layout design method using the functional cells, the layout design by hand is limited to the functional cells, and the portions other than the functional cells can be realized by the standard cells. Therefore, it takes more design than the full custom design. The cost can be reduced. Further, it is possible to further reduce the cost by reusing the existing functional cell.

However, with the increasing demand for higher speed and higher functionality of the system, there is a demand for higher performance and higher functionality of the system LSI used. Therefore, there is an increasing demand for higher speed and higher functionality of the required functional cells, which increases the types of functional cells used and also makes reuse difficult. As a result, even in a cell-based design method using functional cells, the cost for layout design of a newly designed functional cell portion is increasing.

Further, a method for reducing the cost for layout design of the functional cell has been studied as follows. The main ones are the following two methods.

(1) Automatic synthesis of functional cells (2) Layout synthesis from functional cell logic description (1) is used in memory and some simple arithmetic units. Although some high-performance circuits can be obtained, the functions and layouts that can be realized are limited. The method (2) is a method for automatically synthesizing the layout of functional cells, which is largely borne by the hand design, from the logic description.
However, although there are great expectations for these, at present it is not possible to obtain circuits with sufficient performance.

As described above, in the cell-based design method, it is very effective to use the functional cell for speeding up the circuit, but under the present circumstances, a new functional cell is often designed. Cost burden is increasing.

Further, in a portion other than the functional cell, for example,
There may be a path with a large delay time (critical path) in a portion which is not a normal function cell, such as a control circuit portion realized by a standard cell. It is often difficult to deal with this at the layout level.

On the other hand, it is often the case that the system required by the gate array is an LSI. The use of the gate array has the advantages that the period from the design to the production of the product is shorter and the manufacturing cost can be reduced as compared with the conventional full custom design. However, on the other hand, there are problems that the usage efficiency of the chip area becomes low and that the optimum performance cannot be obtained for the applied design rule.

The functional cell-embedded gate array compensates for the above-mentioned weak points of the gate array. When a system LSI is configured using a functional cell embedded gate array, a gate array is used for a control unit that serves as a random logic description, and a functional cell ( For example, a multiplier, a floating point arithmetic unit, etc. are used.

That is, a functional cell having a certain specific function,
For example, the memory, the adder, the multiplier, and the like are optimized and designed in advance by handwriting, so that they have high chip area usage efficiency and high performance. Therefore, by designing an LSI using a functional cell-embedded gate array equipped with high-performance functional cells, it is possible to realize a higher-performance system with a shorter design period and lower cost as in the conventional gate array. There are expectations.

However, on the other hand, if a high-performance functional cell is not prepared, or if it cannot be reused well,
The layout design of a new functional cell must be performed, which increases the design period and design cost and eliminates the advantage of using the functional cell embedded gate array.

Further, in order to reduce the design period and the design cost, even if the functional cell which can be used for one specific purpose is reused for another purpose, it is reused as it is because of a slight difference from the required function. Often not. Therefore, there is a need for a technique for more effectively reusing high-performance functional cells.

Therefore, as a first method of reusing the functional cell, considering that all the functions are incorporated in the functional cell to form a general-purpose functional cell, the range of application in which the functional cell can be reused is expanded. However, in this case, the functional portion 152, which is almost unnecessary for some applications as shown in FIG. 13, causes enlargement of the cell area and deterioration of performance, which is not realistic.

As a second method of reusing the functional cell, there is a method of paying attention to the common basic function of the functional cell and reusing the basic functional cell providing the basic function. This means that even if the functions to be realized are different for each functional cell, if they are functions that are somewhat similar, there are common basic functions, and some specific functions required for the system are The background is that they are often added to each.

In the above method, as shown in FIG. 11, a basic function cell (81) having only a very basic function among the function cells is used to expand the function of the basic function cell (81). For strengthening, a part of the macro cell of the gate array part (82) is used. Of the gate array part, a part of the new functional cell (84) that expands / enhances the function of the basic functional cell is called a functional cell reinforced macro (83). The part will be called a non-functional cell (86).

The basic function cell is optimized to a layout level as a high performance function cell. This basic function cell realizes only the simplest function possible.
For example, an addition block that executes only addition is also an example. In this example, the function-enhancing macro is in charge of detailed flag generation of the calculation result and overflow processing.

However, the operating speed of the circuit using the gate array is slower than the operating speed of the functional cell designed by hand.
Originally, one of the ideas of embedding functional cells in a gate array is to realize a circuit with a gate array,
Alternatively, the function that is disadvantageous in operation speed is supplemented by a function cell.

Therefore, the second method of reusing a high-performance basic functional cell with a circuit having a gate array (functional cell reinforced macro) having a lower performance than this is a reversal of the conventional idea. It was a method of doing so, and a method of realizing this was not considered.

The signal propagation delay on the circuit depends on the capacitance of the transistor and the wiring capacitance (in particular, the wiring length) between the transistors. The circuit performance can be improved by optimizing these, but the effect can be expected by arranging and wiring in consideration of the wiring length in the gate array.

Further, some studies and proposals have been made on the automatic placement and routing technology in consideration of the wiring length. If these techniques are used to optimize the wiring length between the transistors, It is expected that the difference in operating speed between the gate array circuit and the manually designed functional cell will be reduced.

Therefore, as shown in FIG. 10A, if the functional cell strengthening macro portion is locally arranged and wired in the vicinity of the basic functional cell so that the wiring length is optimized, a new high-performance function can be obtained. It is possible to obtain the functional cell that has, and if the whole is divided into a certain region and the placement and wiring are performed by giving each constraint condition, an optimum circuit can be obtained for each divided region.

However, the conventional divided placement and routing program (see FIG. 14) does not support a completely new design method of using the gate array to strengthen the basic function cell.
In other words, as described above, it is possible to divide the area of the placement and wiring, perform wiring independently, and optimize each at a local level. However, since the mutual terminal positions of the divided areas and the mutual loads connected to the divided areas are not taken into consideration, the performance of the entire LSI chip was evaluated even if the wiring length was optimal at the divided local level. In this case, optimum performance may not always be obtained.

[0029]

As described above, in the cell-based design method, since the standard cell has a fixed transistor width that is already optimized for each basic cell, the transistor width is optimized. Improving the performance of a circuit by means of is not easy. To optimize this, many combinations of transistor widths are considered for each basic cell, and a huge number of basic cells are prepared, which is not realistic.

For the data path that needs to be speeded up, it has been unavoidable to reuse or newly design a functional cell whose layout is optimized by hand design. However, as the demand for higher speed and higher functionality of the system has increased, it has become difficult to suppress an increase in cost associated with reusing or newly designing a functional cell.

On the other hand, a critical path also exists in the control circuit section which is usually realized by the standard cell.
It is often difficult to deal with this at the layout level for the above reasons.

Further, when a system is designed using a functional cell embedded gate array as in the conventional case, a high performance system can be realized by using a high performance functional cell having a function required for the system.

However, on the other hand, if a high-performance functional cell is not prepared, layout design must be newly performed. Moreover, even if a functional cell that can be used for a certain specific purpose is reused for another purpose, it cannot be reused in many cases due to a slight difference in function. In addition, incorporating all the functions and creating a general-purpose function cell leads to an increase in the block area and a decrease in performance, and cannot solve the above problems.

Further, conventionally, the functional cell-enhancing macro and the non-functional cell interactively place and route each other, and the LS is traded off due to the arrangement length of each other.
There is no design support device that guarantees optimum performance for the entire I-chip.

An object of the present invention is to solve the above-mentioned problems, and an object of the first invention is to optimize the layout at a layout level in order to speed up the circuit when realizing an LSI layout on a cell basis. It is an object of the present invention to provide a design support device for a semiconductor integrated circuit, which can improve the circuit performance at a low design cost without requiring a new design of a functional cell to be operated.

A second object of the present invention is to provide a semiconductor integrated circuit capable of realizing high performance while having a high mass production effect by incorporating a block having a simple function.

Further, an object of the third invention is to perform optimum placement and wiring of the functional cell strengthening macro for strengthening the basic functional cell and the non-functional cell, and further, considering the mutual connection and the load information, each circuit. It is an object of the present invention to provide a design support device for a semiconductor integrated circuit capable of synthesizing circuits so as to obtain optimum performance of the entire chip in consideration of a trade-off of wiring by giving the constraint as a layout and wiring.

A fourth object of the present invention is to analyze connection information of a macro block (critical path block) for optimization and the entire circuit, copy some cells, rearrange buffers, An object of the present invention is to provide a semiconductor design support device that generates a high-performance circuit by changing the circuit connection description.

[0039]

In order to solve the above-mentioned problems, the first invention is a cell-based layout design method, in which the width of a transistor for a path for which the delay time is to be optimized in a circuit to be realized, A design support device for designing a semiconductor device having a special block capable of automatically optimizing a width and a length of a wiring, the delay time being calculated from a logic description of a circuit, and being larger than a certain fixed time, or Path analysis and path extraction means for searching and extracting a path having a small delay time and separating it into an optimization target path and a non-target path, calculating load information of a transistor on the path, and calculating the physical properties of the transistor. Parameter optimization means for calculating and outputting the optimum values of the physical shape and the wiring shape, and the described pattern based on the path description, the physical shape of the transistor, and the wiring shape information. Symbolic layout synthesizing means for synthesizing the symbolic layout of the above, compaction means for determining a layout having accurate shape layout information of transistors based on the symbolic layout, and constraint information for extracting layout shape and terminal information from actual layout data. It is composed of extraction means and automatic placement and routing means for performing placement and routing in a cell-based layout based on the logic description of the circuit.

According to the second aspect of the present invention, a part of the manufacturing process is commonly manufactured in advance, and at least a part of the integrated circuit is provided in the integrated circuit which realizes various different functions in the remaining manufacturing processes. An integrated circuit in which a function cell having a fixed function is prepared in advance, and the function of the part is changeable, has at least two function changeable regions by design, and at least one of them is adjacent to the function cell. It is characterized by being

Further, according to the second aspect of the present invention, at the stage where a part of the manufacturing process is manufactured in advance in common, the transistor structure arranged in at least one of the function changeable regions is arranged in another region. It is characterized by a different transistor structure.

According to a third aspect of the invention, in the functional cell embedded gate array, the logic description describing the operation of the circuit is separated into at least two descriptions from the whole description, and the logic description is separated by the separating means. For each description, based on the given constraint information, assume the relative positional relationship of the macrocells that realize the basic logical functions, estimate at least the wiring length from that, and output it. Means, and detailed wiring means for arranging the macro cells and performing actual wiring between the macro cells. The rough placement and routing means performs rough placement and routing for one separated description. It has means for outputting the constraint information about the description and the rough placement and routing result, and the rough placement and routing result of one separated description, the outputted constraint information, of the other description. One of the features is that it can be input when performing the rough placement and routing described one by one, and it is possible to perform the rough placement and routing based on the constraint information. Furthermore, depending on the characteristics of the target circuit, the rough placement and routing can be performed. Characteristically, the evaluation function for executing can be changed accordingly.
The detailed placement and routing means is capable of inputting constraint information of general placement and routing of one separated description and known layout data. Further, the detailed placement and routing is performed at the same time when the detailed placement and routing of the input description is performed. It is possible to combine known layout data with the detailed placement and routing result. Further, depending on the characteristics of the target circuit, the evaluation function for executing the detailed placement and routing is also changed accordingly. It is characterized by being able to.

In the fourth invention, the delay time is calculated from the connection description (netlist) of the circuit, a path having a delay time larger or smaller than a certain fixed time is searched, and cells on the path are searched. A path analysis and path extraction unit that separates the circuit connection description by the extracted and optimized paths and non-target paths, and two connection descriptions separated by the path analysis and path extraction unit ( And a cell relocation means for modifying the two connection descriptions while preserving the logic of the entire circuit based on the result of the analysis by the net analysis means. The net analyzing means is composed of a buffer position analyzing means and a cell copy judging means, and the buffer position analyzing means analyzes the connection description of the circuit and outputs a buffer. Analyzing position, and the driving capability of,
The optimum buffer position and driving capacity are calculated, and the result is output, and the cell duplication determination means analyzes the connection description of the circuit and stores the original logical relationship,
It is characterized in that whether or not it is possible to put a copy of the cell and the equivalent cell in the circuit connection description relating to the optimization target path into the circuit connection description relating to the optimization non-target path is determined.

[0044]

In the design support apparatus according to the first aspect of the present invention, when cell-based layout design is performed, a path that requires high-speed operation can be optimized in a specially prepared block.

The path analysis and path extraction means analyzes and calculates the delay time of the path from the logical description of the circuit, extracts the path exceeding a certain delay time, and selects the path to be optimized and the non-target. Separation into paths, the parameter optimizing means calculates optimum transistor and wiring shape parameters based on the extracted paths, and the symbolic layout synthesizing means calculates the optimum transistor and wiring shapes. In consideration of the shape parameter of, the symbolic layouts of the extracted paths are synthesized, and the compactor synthesizes the actual layout of the critical path portion based on the synthesized symbolic layout.

The constraint information extracting means extracts layout shape and terminal information from the synthesized real layout, and the automatic placement and routing means extracts the paths other than the paths extracted by the path analysis and path extracting means. The layout of standard cells is synthesized from the logical description of the circuit. Then, it is integrated with the actual layout of the critical path portion synthesized by the compactor to complete the entire layout.

Further, in the second aspect of the present invention, the functions associated with the functional cells, which are required to have high performance, are realized by the transistor rows arranged in the region adjacent to the functional cells. Generally, in automatic placement and routing, the smaller the number of gates handled, the higher the quality result obtained. In consideration of this situation, the transistor in that region is optimized in advance, so that the performance can be greatly improved.

By these operations, the function associated with the function block can be realized with high performance, and the function cell itself can be simplified.

Furthermore, according to the third aspect of the present invention, the functional cell reinforced macro that constitutes the functional cell and the non-functional cell that is the portion excluding the functional cell reinforced macro are combined into optimum circuits by the divided placement and routing technology. As a matter of course, from the execution result of the rough placement and routing of the functional cell strengthening macro, the constraint information of the functional cell is output, and the constraint information is given as the constraint of the rough placement and routing of the non-functional cell part. The rough placement and routing is performed, the constraint information of the non-functional cells is output, the rough placement and routing of the functional cell strengthening macro is performed again, and the rough placement and routing of the functional cells and the non-functional cells is optimized. Optimizes the entire circuit by performing detailed placement and routing of functional cells based on the optimized rough placement and routing results and performing placement and routing of the entire circuit including non-functional cells based on this result. High performance LSI can be designed.

According to the fourth aspect of the present invention, when a cell-based layout design is performed, a path which requires a high speed operation is optimized in a specially prepared block. The path analysis and path extraction means analyzes and calculates the delay time of the path from the connection description of the circuit, extracts the path exceeding a certain delay time, and separates it into the optimization target path and the non-target path. To do. A macroblock for optimization is constructed by separating the connection description of the cells passing through the separated optimization target paths. The buffer position analysis means of the net analysis means calculates the load connected to the output of the buffer from the connection description of the circuit, and provides information for buffer rearrangement. The cell duplication determination means of the net analysis means searches for a cell having observable input / output from outside the macroblock for optimization, calculates the load of the wiring connected to the corresponding cell, and Providing information on availability and reproduction. The cell rearrangement means corrects the circuit connection description based on the information obtained from the net analysis means.

[0051]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Invention FIG. 1 is a block diagram for realizing a design support device for a semiconductor integrated circuit according to the first invention, and FIG. 2 is a standard floor plan of an LSI realized by this design support device. Is shown. An outline of the configuration and processing flow of a semiconductor integrated circuit design support device as an embodiment of the first invention will be described below with reference to FIGS. 1 and 2.

As shown in FIG. 2, the LSI designed by the semiconductor integrated circuit design support apparatus of the present invention has a critical path block (31) and a standard cell (3).
2). Also, if necessary, RA
It also includes functional cells (41) for high integration such as M and register files.

In the conventional LSI design method, as shown in FIG. 12, functional cells are reused or newly designed. Therefore, the layout structure needs to be divided into blocks for each function (that is, for each function cell).

However, in the semiconductor integrated circuit design support apparatus of the present invention, attention is paid to paths requiring high-speed operation,
A block that realizes optimization at the layout level for these speedups (critical path block (31))
Therefore, it is not premised that blocking is performed for each function (although some existing function cells can be reused).

In general, when a cell-based layout is realized, the transistor width is fixed in basic cell units. Therefore, when optimizing the circuit at the layout level of the standard cell, conventionally, only the mapping of the basic cells and the wiring between the basic cells can be considered.

However, if the semiconductor integrated circuit design support apparatus of this embodiment is used, as shown in FIG. 2, a portion (critical path block (31)) capable of optimizing the width of the transistor is specially provided. Also in the cell-based layout design, the transistor width can be optimized here for some paths that determine performance. Therefore, it is not necessary to newly design the functional cell for speeding up.

In the semiconductor integrated circuit design support system of this embodiment, optimization of the transistor width and the shape of the wiring is considered only for a part of the paths, so that it is expected that the performance will be improved with a realistic processing amount. it can. Further, it is possible to reduce the cost conventionally required for designing a new functional cell for speeding up the circuit.

The configuration of the design support apparatus of this embodiment will be described below. The design support apparatus of this embodiment includes a path analysis and path extraction program (11), a parameter optimization program (12), a selma pink program (13), a symbolic layout synthesis program (14), a compactor (15), and constraint information. It is composed of an extraction program (16) and an automatic placement and routing program (17).

For the critical path block (31) and standard cell (32) as shown in FIG. 2, it is necessary to divide the entire circuit (separate the logic description of the circuit) according to the performance required by the circuit. . At this time, the optimization target paths that require high performance are collected in the critical path block (31), and the non-optimization paths that do not require high performance are standard cells (3).
It is allocated to 2). The path analysis and path extraction program (11) does this.

Next, the layout of the critical path block (31) is synthesized from the separated logical description of the optimization target path by the parameter optimization program (12), the cell mapping program (13), and the symbolic. A layout synthesis program (14) and a compactor (compaction program) (15).

On the other hand, the non-optimized paths realized by the normal standard cells are synthesized by the automatic placement and routing program (17). At this time, the physical constraint information of the critical path block (31) is required, which can be obtained from the constraint information extraction program (16).

Next, the operation of this design support apparatus will be described with reference to FIG. [1] Path Analysis and Path Extraction and Description Separation (Path Analysis and Path Extraction Program (11)) Here, a logical description expression of a circuit: cir_logc (101)
Input the path analysis and path extraction program (1
According to 1), the path to be optimized: c_path (11
1) and other parts (paths not targeted for optimization):
It is separated into nonc_path (112).

Logic description of circuit: cir_logc (101)
Is assumed to be obtained as a result of a designer designing with a logic diagram or obtained by logic synthesis from a functional description.

Path analysis and path extraction program (11)
Calculates the delay time of each path by searching the cells for the delay time of all paths according to the net description of the circuit based on cir_logc (101). At this time, the delay time information of the cell is obtained from the standard cell life: sc_lbi (100). Then, as a result of the delay time calculation, based on the target performance set by the designer, a path having a large delay time that does not satisfy the target performance is extracted.

At this time, a path having the extracted path and a gate shared with this path and having a large proportion occupied by this gate (an evaluation function for determining whether the proportion occupied by the number of gates is large or small is specified separately). Program) is output to c_path (111), and all other paths (paths not subject to optimization) are nonc_path
Output to (112).

[2] Transistor width and wiring length optimization (parameter optimization program (12)) Here, the parameter optimization program (12) uses the c_path (111) as input data and the transistor width of the critical path portion Optimum value and wiring constraint: t _
opt (121) is calculated.

At the layout level, in order to speed up the circuit, the width of the gate of the transistor, the width and length of the wiring,
It is necessary to optimize cell allocation. In standard cells, the gate width of the transistor in the basic cell is
It is already fixed and cannot be optimized. Therefore, in the present invention, a critical path block (31) is provided in order to optimize the width of the gate of the transistor, and the circuit is optimized there to speed up the operation of the circuit.

The parameter optimization program (12)
The drive capability of each transistor is evaluated based on the fanout of each transistor and the virtual wiring length between the basic cells using c_path (111) as input data. Then, based on the evaluation, the optimum value of the transistor width corresponding to the driving ability is calculated. This result calculation is output to t_opt (121).

At this time, the designer can specify the optimization level as required. -For example, if more optimization is considered, a constraint on the wiring length between cells can be added to t_opt (121) so as to reach the target performance.

[3] Symbolic layout synthesis In this step, c_path (111), t_opt (12
1) as input data, cell mapping program (1
3), symbolic layout synthesis program (14)
Synthesizes the symbolic layout: c_smb (141).

In this embodiment, the cell library: sc_lbi
An example of synthesizing a symbolic layout using the transistor arrangement of (100) will be shown. First, by the cell mapping program (13), c_path (111)
Cell allocation. At this time, the cell to be preferentially assigned is determined from the wiring constraint information given by t_opt (121). That is, when the wiring length between specific cells must be shortened, the constraint is t_opt (12
1), and cell allocation is performed so as to give priority to this.

Since the relative placement of the transistors and their connections are determined at the time of allocating the cells, the symbolic layout synthesizing program (14) determines the symbolic layout based on the connection data of the circuits by the allocated cells: c_smb (141) is synthesized.

Of course, some programs are known as a program for directly synthesizing the symbolic layout based on the description of the path, and this program can also be used.

[4] Compactor (compacting program) Here, the symbolic layout is c_smb (14
With 1) as an input, the compactor
Perform 5). As a result of the compaction, the layout data of the critical path block, c_layout (151) is obtained. This means is publicly known and is not particularly new in this embodiment, and is a program for synthesizing an actual layout from a symbolic layout. After passing through this step, the layout of the critical path block (31) is completed.

[5] Constraint Information Extraction Based on c_layout (151), the constraint information extraction program (16) extracts block constraint information (161) such as block size and terminal information of the critical path block. This information becomes important information when the subsequent placement and routing of standard cells is performed.

As described above, from [2] to [5], the synthesis of the critical path block is performed. Next [6],
In [7], the placement and routing of standard cells and the final layout are combined.

[6] Automatic placement and routing of standard cells The conventional automatic placement and routing program of standard cells (17) is used. Position of critical path block and block constraint information: c_cnst (161)
Is given, the automatic placement and routing program (17) causes the logical description of the non-target path for optimization: nonc_path (1
From 12), the layout of non-target paths for optimization:
The nonc_layout (171) is synthesized. This means is also publicly known, and an existing one can be used instead of a new one in this embodiment.

[7] Layout integration Layout of paths that are not targeted for optimization, synthesized by the automatic placement and routing program: nonc_layout (171)
And the layout of the critical path block, c_lay
integrated out (151) and finally the whole layout: totl
_Layout (181) is synthesized.

Through the process described above, the layout of the cell-based LSI having the critical path block (31) shown in FIG. 2 can be designed. However, although not described in detail here, there is a case where it is necessary to prepare a filter program for converting the data format between the programs, particularly when using the existing program.

Further, in the semiconductor integrated circuit design support apparatus according to the above-mentioned embodiment of the present invention, only one critical path block (31) is shown, but the present invention is not limited to this and a plurality of critical path blocks may be assumed. .

The existing function cell (4
Regarding the use of 2) as well, in the present embodiment, it is possible to use this together, and the use of this functional cell is not prohibited. Application Example The design support apparatus for a semiconductor integrated circuit according to the first aspect of the invention having the configuration described above can also be applied to optimization of the layout area. Here, it will be described below as an application example.

In the above-described embodiment, focusing on the paths that require high-speed operation, the block (critical path block (31)) that realizes optimization at the layout level for speeding up these paths is constructed. explained.

On the other hand, if the delay time distribution of the paths of the circuit has a certain width, there are also paths having delay times sufficiently smaller than the design target T, as shown in FIG.

Therefore, in the present application example, contrary to the above-described embodiment, the optimization target is narrowed down to the path having a small delay time. That is, in the processing [1] path analysis and path extraction and description separation of this embodiment, paths with small delay time can be extracted and separated at the same time. In this path with a small delay time, there is a margin to slightly reduce the width of the transistor or a margin to slightly increase the wiring length.
By using this margin, it is possible to relax restrictions on layout. Furthermore, the layout of the circuit can be effectively optimized by using it together with the optimization for speeding up the circuit of the above embodiment.

The effect of the performance improvement by the circuit optimization by the first invention, that is, the semiconductor integrated circuit design support apparatus of the first embodiment is as follows.

FIG. 3A is a model of the distribution of the delay time of the path in the LSI. The horizontal axis shows the path delay time, and the vertical axis shows the number of paths at each delay time. Here, t min is the minimum delay time of the gate, and t max is the maximum delay time of the path.

Usually, when designing an LSI, there is an operation speed targeted by the designer. When the delay time corresponding to the operation speed is T, the path (20) in the range of T <t <t_max determines the performance of the LSI. (Strictly speaking,
The critical path with the delay time t max is determined. In order to reach the target performance, the designer will make an effort to reduce the delay time of these paths, i.e. to bring tmax as close to T as possible. It is said that a critical path that determines performance and a path that has a delay time close to that of the critical path are about a few percent to a dozen percent of the entire circuit. Then, a critical path of about several percent to a dozen percent will dominate the overall performance of the circuit.

In the standard cell, the width of the transistor is fixed in units of basic cells, but it is possible to optimize the transistor width and the wiring length only in these portions by extracting the critical path or a path corresponding thereto. It is an invention. That is, as described in the embodiments of the present invention, by providing the critical path block (31), the transistor width can be optimized.

At this time, the target circuit is a few% of all circuits.
Since the scale is from 10 to 10%, it is possible to optimize with a realistic processing amount. Then, as a result of focusing on reducing the delay time only in these portions, it is possible to significantly improve the performance with the minimum effort (see FIG. 3B).

On the other hand, as described in the application example, the path having a short delay time is optimized for reducing the transistor area. This makes it possible to reduce the layout area.

Further, this design method is also effective for a higher-level design method. In the conventional cell-based design method, from the upper level design stage, it was necessary to design with a strong awareness of functional cells (up to the layout level) that can always be used.

That is, since the functional cells for speeding up the circuit are used, the block formation for each function defined in the upper level reaches the layout level and has a considerable influence. If the design is proceeded without paying much attention to the layout level, the layout level is likely to break down. Then, when a failure occurs, the entire design including the upper design has to be changed. Moreover, whether or not the breakdown occurs at the layout level is often known only after the layout design of each functional cell to be used has advanced to some extent, and when it becomes clear, it is extremely difficult to correct it.

Since this design method is premised on the automation of the layout level, the designer does not use much nerve in the layout level as if the circuit is realized by the gate array, and the upper level (up to the logic design level) is used. You can focus on the design. Further, since the blocking for each function is limited to the case where the functional cell for reuse is used, it is possible to estimate the layout in advance, so that the restriction due to the blocking at the layout level is loose and the breakdown at the layout level is caused. Is also hard to get up. Furthermore, automation has the advantage that design defects at the layout level can be found early and corrections and changes can be handled quickly. Second Invention FIG. 4 shows a diagram of a gate array mother body for realizing the first embodiment as the second invention.

In this embodiment, an adder 51 is mounted as a functional cell, a first transistor array region 52 having a small gate size is provided in a portion adjacent to the adder 51, and a second transistor array region is surrounded so as to surround the first transistor array region 52. It has 53. Of these, the first and second transistor array regions 52 and 53 are designated in advance as user definable.

A logical description of a part which is a function associated with addition such as flag generation and which is required to have a high performance but has a different function depending on the system is specified by instructing the automatic placement and routing program to execute the first transistor array area. 52 is laid out. The remaining description is automatically placed and wired in the second transistor array region 53.

FIG. 5 shows a diagram of a gate array matrix for realizing the second embodiment of the present invention. In this embodiment, the arrangement direction of the basic cells in the first transistor array region 52 is different from the arrangement method of the basic cells in the second transistor array region 54.

In the automatic placement and routing method in which the cell rows and the wiring portions are alternated after completion, such as a gate array, there are sides where it is easy to strictly set the terminal position and sides which are difficult to set.
On the other hand, considering only the degree of integration, it is easier to increase the degree of integration if the terminal positions are not fixed.

In this embodiment, there is a functional cell first, and the first transistor array region 52 around the functional cell is automatically placed and wired first, and then the second transistor array region 54 is formed.
Place and route automatically. First transistor array region 5
When 2 is automatically placed and wired, the functional cell is fixed, so the terminal position is also fixed, and it is necessary to strictly wire to that portion. However, the signal between the first transistor array region 52 and the second transistor array region 54 is, so to speak, an intermediate signal, and the position is not necessarily limited. Limiting the terminal position may lead to a decrease in the degree of integration.

Therefore, the first transistor array region 52
Strictly wire the side in contact with the functional cell so that the terminal position can be easily set precisely. On the other hand, the assembly with the second transistor array region 54 brings the terminal position to the side where it is difficult to strictly set it, and increases the degree of integration by not fixing the position. For the second transistor array region 54,
Since the signal line with the first transistor array region 52 has already been determined as position information, the boundary line with the first transistor array region 52 is a side where the terminal position can be set precisely.

FIG. 6 shows the cell structure used in the first transistor array region 52 for realizing the first and second embodiments described above, and FIG. 7 shows the cell structure used in the second transistor array regions 53 and 54. The cell structure is shown below. In FIGS. 6 and 7, 55 is a polysilicon layer and 56 is a diffusion layer.
In this embodiment, the first transistor array region 52 realizes the function associated with the functional cell. Therefore, since there is a strong demand for a special circuit, the cell structure is such that each transistor is independent.

On the other hand, the second transistor array region 5
General combination gates are sufficient, since 3, 54 realize other functions. In the cell structure shown in FIG. 7, a part of the transistor is electrically pre-connected by the polysilicon layer 55, but this is sufficient to realize a general combination gate. Conversely, the polysilicon layer 55
Since they are electrically connected with each other, it is possible to improve the degree of integration without using an extra metal wiring layer. Therefore, high performance and high degree of integration can be realized at the same time by realizing the functions associated with the functional cells with the cell structure shown in FIG. 6 and realizing the other parts with the cell structure shown in FIG.

According to the present invention, the functions associated with the built-in functional cells, which are required to have high performance, are realized by the transistor rows arranged in the region adjacent to the functional cells. High performance, high performance for the LSI as a whole.

Further, since the associated function can be realized with high performance, the built-in block can have a simple function, and can be used for many applications, so that the mass production effect is large. Due to these effects, it is possible to realize a high-performance gate array that is highly effective in mass production.

This effect will be described more specifically by using the first embodiment.

The gate array shown in the first embodiment has a built-in adder 51 as a functional cell in advance. Addition is a very simple and basic function and may be performed when used in most systems, while this adder 5
Various types of high-speed circuits have been studied for many years, and many have attempted to increase the speed by using a structure that is not an ordinary combinational gate. Therefore, the gate array in which the adder 51 is previously incorporated as a functional cell can be used for a very general purpose, and a high performance product can be obtained as compared with the case where the adder 51 is realized on a normal gate array.

On the other hand, flag generation using the result of addition is also performed quite frequently. The type of flag required varies considerably from system to system, and the time allowed for processing is short because it is generated using the result of addition,
In this embodiment, such a function is automatically placed and wired in the area adjacent to the addition function cell. By implementing with automatic placement and routing, it is possible to freely generate only the flags necessary for the system, and since the area where they are placed and routed is limited, it can be expected that the wiring length will be shortened. Since the wiring load is reduced, higher speed can be expected. Further, there is an appropriate balance relationship between the wiring length and the size of the transistor, and it is possible to reduce the size of the transistors arranged in the transistor row on the assumption that the wiring length is short.

This means that the same logic is realized in a small area, which means that the wiring length is further shortened. That is, since positive feedback is applied to the performance and area, the performance / area ratio when the automatic placement and wiring area is limited and the optimum transistor size is used is higher in each stage than when realized by a general gate array. It will be good.

Further, the present invention is remarkably versatile in comparison with the fact that such a flag circuit mounted in a functional cell cannot be used except for a system using exactly the same flag. Further, if the flag generating circuit is incorporated as a functional cell as far as possible, the original addition can be realized with about 10 gates or less per bit, so that the flag generating circuit portion has a circuit scale equal to or more than that of the adder portion. turn into. If the number of circuits is reduced, the speed of the functional cell will be reduced, so the merit of using it will be diminished.
In this embodiment, since only the adder is mounted as a functional cell, the versatility is not lowered at all and the mass production effect is high.

As described above, according to the present invention, a semiconductor integrated circuit having high performance and high mass production effect can be obtained.

Regarding the embodiments and effects of the invention, M
It should be noted that although an OS transistor is used, a similar effect can be obtained with another type of transistor such as a bipolar transistor or a BiCMOS transistor, or a combination thereof. Third Invention Hereinafter, an embodiment according to the third invention will be described with reference to FIGS.
This will be described using 1. The outline of the design flow in this design support apparatus is shown in FIGS.

FIG. 8 shows the rough placement and routing from the logical description, and the optimization process in the rough placement and routing.
The design flow until a layout is synthesized by detailed placement and routing is shown. FIG. 9 shows a flow of data in the above-mentioned rough layout and detailed layout. The design flow will be described with reference to these figures.

FIG. 10 is a diagram for explaining the relationship between the terminal position of the functional cell and the performance of the non-functional cell, and the optimization in the rough placement and routing will be described using this.

FIG. 11 shows an outline of the structure of the functional cell. For the sake of convenience of the following description, a brief summary thereof will be given. The basic function cell (81) is a functional cell having a very basic function in consideration of reuse. To enhance the function of this basic function cell, a normal gate array section (82) is used.
Use part of. Of the gate array portion (82), the portion for enhancing the function is the functional cell enhancing macro (83).
And the other part is the non-functional cell (85).

The new function cell (84) having the function necessary for the system LSI to be designed is the basic function cell (81).
And a functional cell strengthening macro (83).
The new functional cell (84) and the non-functional cell (85) are connected via terminals (86) to (90) on the functional cell.

The basic function cell (81) is optimized up to the layout level, and as a function cell library,
It has layout data and logical description data. However, it is possible to prepare a description at the functional description level or higher.

The basic function cell strengthening macro (83) and the non-function cell (85) do not have layout data and are expressed by logical descriptions (71), (72) or higher level description.

Since the design flow up to the logical description level for describing the required system operation is the same as the conventional one, the description is omitted here, and it is assumed that the logical verification has been completed. I will explain the flow.

[1] Separation of Description First, the logical description (71) of the functional cell reinforced macro and the logical description (72) of the non-functional cell part are separated (61) from the entire logical description.

The description of the functional cell is made up of the description of the basic functional cell and the description of the functional cell strengthening macro (71). Among the functional cells, automatic placement / wiring (general placement wiring, detailed placement wiring) is used. The circuit is synthesized only in the functional cell strengthening macro portion.

Here, the description is separated into the description (71) of the functional cell strengthening macro and the description (72) of the non-functional cell section when the circuit is realized by automatic placement and wiring in the gate array section. This is because different processes are performed as shown in FIG. 8, and it is necessary to distinguish and input them in the automatic placement and routing program.

[2] General layout and wiring (functional cell reinforced macro) From the logical description (71) of the functional cell reinforced macro, the rough layout and wiring of the functional cell reinforced macro portion is performed (62).

At this time, as the initial constraint (73), the constraint on the layout and wiring region (region designation of the functional cell strengthening macro), the terminal position of the basic functional cell, and the physical constraint of the basic cell such as load information connected to the terminal are set. , There is a timing constraint for optimizing the wiring length.

Since the non-functional cell constraint information is still unknown, the general layout and routing is not taken into consideration here so that the wiring length in the functional cell strengthening macro is optimized without considering the constraint regarding the non-functional cell at all. Is done.

In this general layout and wiring, under the above-mentioned initial constraint (73), the relative positional relationship of macrocells that realize more basic logical functions such as AND and OR is assumed,
The wiring length is estimated from there. At this time, the actual wiring is not performed, and the rough arrangement of the macro cells is determined based on the number of wirings between the macro cells and the positional relationship of the macro cells, and the wiring length and the wiring region are evaluated.

As a result of this rough placement and routing, the rough placement and routing of the functional cell strengthening macro (macro cell rough placement and routing (76)) optimized independently of the non-functional cells is obtained.
Further, the constraint information (74) relating to the functional cell necessary for the general placement and routing of the next non-functional cell (next step [3]) is output. The restriction information (74) regarding the functional cell includes the terminal position of the functional cell, the load information of the functional cell at the terminal, the information regarding the critical path of the functional cell, and the like.

[3] General placement and routing (non-functional cell section) From the logical description (72) of the non-functional cell, the general placement and routing is performed for the non-functional cell section (63). At this time, the area constraint in the case of performing the placement and routing and the constraint information regarding the terminal connected to the functional cell are given by the constraint information (74) of the functional cell output in [2].

Here again, the actual wiring is not performed, and the necessary layout wiring area is estimated and evaluated from the positional relationship between the macro cells to obtain the rough layout position (77) of the cell.

The output information is the constraint information (73) of the non-functional cell part. The constraint information (73) of the non-functional cell portion includes critical path information in the non-functional cell portion, load information (wiring length) on the non-functional cell side in the terminal of the functional cell.
And so on, which includes information that restricts the placement and routing of functional cells.

The general layout and wiring of [2] and that of [3] may be different in the evaluation function, algorithm, or program itself of the rough layout and wiring of cells. This is because the function-enhancing macro is required to have performance comparable to that of the basic function cell, has a small number of gates, and has a feature that the layout and wiring area is limited to a local portion, whereas the non-function cell portion has Since it targets all circuits except macros for enhanced functions, it does not require as much performance as functional cells, and has the feature of using a large number of gates.

Therefore, the evaluation functions and algorithms of these programs, or the programs themselves do not have to be the same, and it is sufficient that data such as constraint information can be exchanged between these programs.

By the way, as a result of the placement and routing of the functional cell according to [2], a general placement and routing optimum for the functional cell was obtained, but the terminal position of this functional cell is not always the optimal position for the non-functional cell portion. Absent.

That is, the optimization in [2] does not consider the constraint condition of the non-functional cell at all. Therefore, in the non-functional cell, a path with a long wiring length is generated, which deteriorates the overall performance. (Fig. 10
(A)).

This will be described below with reference to FIG. FIG. 10A is a schematic layout and wiring result when the constraint of the non-functional cell portion is not considered, and FIG.
Is a model of the rough placement and routing result in the case of considering the constraint of the non-functional cell portion. In the drawing, the wiring is assumed from the positional relationship between the terminal and the macro cell block.

When the functional cells are arranged and wired independently of the non-functional cells as in [2], the positional relationship with the macro cell block on the non-functional cells is not taken into consideration.
There may be a case where the macro cell block of the non-functional cell is connected to a terminal (of the functional cell) apart from the macro cell block as shown in FIG. (For example, the terminal 89 and the block A, the block B, and the terminal 90 and the block B) As a restriction of the non-functional cell portion, a terminal (of the functional cell) connected to the same macro cell block of the non-functional cell portion is a functional cell. If the cells are specified to gather in the placement and routing of FIG.
As shown in (b), the terminals are rearranged, and further, the critical path is improved by the rough placement and routing of the non-functional cells (process [5]).

[4] General layout and wiring (functional cell strengthening macro) The basic operation is the same as in [2]. As shown in FIG. 9, the difference from [2] is that the constraint information (7
5) was added (64).

Here, in order to optimize the performance of the entire circuit, the rough placement and routing are performed in consideration of the restrictions on the non-functional cell side, and the terminals of the functional cell strengthening macro are rearranged.

The circuit obtained by this schematic layout and wiring is
Since it was synthesized under the condition that more constraints were added,
The circuit itself may have lower performance than the circuit synthesized at the point [2].

However, the terminal position of the functional cell synthesized here is more optimized by the next rough placement and wiring ([5]) of the non-functional cell part, because the constraint on the non-functional cell side is taken into consideration. Therefore, the performance of the entire circuit can be expected to improve as a result.

[5] Schematic placement and routing (non-functional cell section) The operation is exactly the same as in [3]. Here, as described above, since the terminals are rearranged in consideration of the constraint on the non-functional cell side, optimization can be expected rather than [3] (6
5).

The designer specifies the non-functional cell constraint information (75).
Based on the reported critical path information in
It is judged whether or not the evaluated overall placement and routing is as requested by the designer, and the process proceeds to the next step. If in the non-functional cell part,
There is a critical path due to the functional cell terminals,
If it affects the overall performance, the process from [4] to [5] is repeated again.

If the result is as requested, the process proceeds to step [6]. Alternatively, if a little more optimization is desired, the process may return to [4] to [5].

[6] Detailed Placement / Wiring (Functional Cell Reinforcement Macro) Detailed arrangement and wiring is performed based on the description portion (71) of the functional cell reinforcement macro. At this time, in addition to the initial constraint (73), finally, the constraint information (74) of the functional cell evaluated in [4],
Finally, the constraint information of the non-functional cell evaluated in [5] (75)
Is also entered. The general arrangement position (76) of the cell is
Based on the final result evaluated in [4], macro cells are allocated and actual wiring is performed so as to satisfy each constraint.

When optimum wiring satisfying each constraint is realized, the layout of functional cells (78) is completed by combining with the layout data (79) of basic functional cells.

At this time, the functional cell constraint information (78) is output, which includes detailed input / output load information at the functional cell terminals evaluated from the actual wiring, the functional cell terminal position, and the functional cell section. Contains the critical path information in, and these are used in the detailed placement and routing of the non-functional cell portion in [7] below.

[7] Detailed Placement / Wiring (Overall Logic Description) Based on the logic description (71) of the non-functional cell, detailed placement / wiring of the non-functioning cell portion is performed and further layout of the functional cell portion (7)
Combine with 8) to complete the overall layout (67).
In addition, the rough arrangement position (77) of the cells is based on the result evaluated in [5].

Here again, although wiring is actually performed, detailed placement position constraints are given by the constraint information (78) of the functional cells and the constraint information (75) of the final non-functional cells.

The layout is completed if actual wiring satisfying this is possible under the given restrictions.

The detailed arrangement and wiring of [6] and the detailed arrangement and wiring of [7] may differ in cell arrangement, inter-cell wiring algorithm, or program itself.
This is also for the same reason as in the case of the general layout and wiring, and since the performance and the circuit scale of the target circuit are different, the evaluation function and algorithm of the program that synthesizes these,
Alternatively, the programs themselves need not be the same.

The design flow has been described above. However, in the semiconductor integrated circuit design support apparatus of this embodiment,
Since automatic placement and routing of circuits is performed in consideration of the trade-off between functional cells and non-functional cells, it is possible to realize a circuit having optimum performance in the gate array portion.

According to the third invention, in a system designed by using a functional cell embedded type gate array, a functional cell constituted by strengthening the function of a high performance basic functional cell by a gate array portion is used. As a result, it is possible to realize the functional cells required for the system specifications.

As described above in detail with respect to the semiconductor integrated circuit design support apparatus as each embodiment according to the first aspect of the present invention, as shown in FIG. 2, a portion where the transistor width can be optimized (critical path block ( 31)) is specially provided, even in the cell-based layout design, for some paths that determine performance,
The width of the transistor can be optimized at the stage of this layout design. Also, since optimization of the transistor width and the shape of the wiring is limited to a part of paths, C
In AD (computer-aided design system and its program), improvement in performance can be expected with a realistic amount of processing. Further, it is possible to reduce the cost conventionally required for designing a new functional cell for speeding up the circuit.

By the way, the LSI designed by the semiconductor integrated circuit design support apparatus according to the embodiment of the first aspect of the invention described above is composed of the critical path block (31) and the standard cell (32) as shown in FIG. It is configured and also includes a functional cell (41) for high integration such as a RAM and a register file as needed. As shown in FIG. 1, the design support apparatus for a semiconductor integrated circuit shown in the embodiment has a path analysis and path extraction program (1
1), parameter optimization program (12), cell mapping program (13), symbolic layout synthesis program (14), compactor (15), constraint information extraction program (16), automatic placement and routing program (1)
7).

For the critical path block (31) and standard cell (32) having the structure shown in FIG.
In some cases, it may be necessary to divide the entire circuit (separate the logic description of the circuit) according to the performance required by the circuit. At this time, the optimization target paths that require higher performance are collected in the critical path block (31) area, and the optimization non-target paths that do not require higher performance are standard cells (32). Is allocated to the area. The path analysis and path extraction program (11) shown in FIG. 1 executes this allocation.

Next, the parameter optimization program (12) and the cell mapping program shown in FIG. 1 are to synthesize the layout of the critical path block (31) from the logical description of the separated optimization target paths. (1
3), symbolic layout synthesis program (1
4), compactor (compaction program) (1
5).

On the other hand, the non-optimized paths realized by normal standard cells are synthesized by the automatic placement and routing program (17) shown in FIG. At this time, the physical constraint information of the critical path block (31) is required, which is the constraint information extraction program (1
I'm trying to get from 6).

As described above, according to the semiconductor integrated circuit design support apparatus of the embodiment of the first aspect of the present invention, in the cell-based layout design, the width of the transistor is reduced with respect to a part of the paths that determine the performance. By providing a special block for optimizing, and optimizing there, a high-performance circuit can be obtained at low cost.

However, depending on the circuit structure, the effect of improving the performance may be small. That is, depending on the terminal position of the whole block or the cell extraction method for optimization, a macroblock and standard cells for optimization as shown in FIGS. As a result, the increase in the delay time may offset the effect of the optimization in the macroblock for the optimization.

For example, referring to FIG. 15, from the outside of the critical path block (31) as a macro block for optimization, the critical path block (3
Consider two paths A (501) and B (502) which are input to the buffer in 1) and whose output signals are again output to the outside of the critical path block (31).
The path A (501) is the critical path block (3
Although the delay time is slightly increased by passing through 1), the position of the terminal (500) and the critical path block (31) in the entire block and its terminal (51
0) The increase value is small because the positions are close. On the other hand, pass B
(502) passes through the critical path block (31), so that the terminal (52
0) and the position of the critical path block (31) and the position of the terminal (530) are distant from each other, an extra wiring length is generated, and the layout of the critical path block (31) is optimized by one stage of the buffer. Since the effect is not reflected at all, the degree of increase of the delay time is larger than that of the path A. This is one of the causes of the reduction in the effect of circuit optimization.

Not only the buffer but also NAND, NO
Even when there is a path that is shared by a normal cell such as R and is input to the critical path block (31) and immediately output, delay time may increase due to wiring overhead.

For this, the path C (50
3) and the path D (504) will be described as an example. Path C
(503) was one of the critical paths of this circuit at the stage before the macro conversion into the critical path block (31). On the other hand, the path D (504) had a delay time substantially equal to the design target value, and shared a part of the gate E (cell 55) with the path C (503).

All paths of path C (path C1, circuit C1 (5
40), gate E (550), circuit C2 (560), path C2), from circuit C1 (540) to rotation C2 (5
Up to 60) is macro-coded as a part of the critical path block (31) and is optimized here at the transistor level, the delay time of the path C is reduced by the effect of shortening the delay time in the critical path block (31). It is shortened to the design target value (see FIG. 15).

On the other hand, the path D (504) slightly increases the delay time due to the overhead of wiring with the critical path block (31) in the paths D1 and D2, and the optimization effect in the critical path block (31) can be obtained. Since it cannot be obtained, a problem occurs that the delay time of the path D (504) increases and the design target value is slightly exceeded. Thus, depending on the path, the performance may be degraded.

Fourth Aspect Therefore, in a semiconductor integrated circuit design support apparatus according to an embodiment of a fourth aspect of the present invention described below, in order to solve the above-mentioned problems, macroblocks for the optimization (critical It is possible to analyze the connection information of the path block (31)) and the entire circuit, copy some cells, rearrange buffers, change the connection description of the circuit, and generate a circuit with higher performance. .

The semiconductor design support system of this embodiment is characterized by changing the connection description (net description) of the circuit while preserving the logical contents realized by the original circuit.

FIG. 17 shows a processing flow of the semiconductor integrated circuit design support apparatus according to the fourth invention.
Reference numeral 19 shows the state of rearrangement of buffers and cells realized by the design support device for the semiconductor integrated circuit.

Hereinafter, with reference to FIGS. 17, 18 and 19,
The configuration and processing outline of a semiconductor integrated circuit design support apparatus as an embodiment according to the fourth invention will be described.

The semiconductor integrated circuit design support apparatus according to the fourth aspect of the present invention, as shown in FIG.
0), cell extraction means (191), net analysis means (19)
2), the cell rearrangement means (195).

The path analysis means (190) calculates the delay time of the path based on the logical description expression of the circuit (usually also serving as the connection description of the circuit) (101) by the path analysis program.

The cell extracting means (191) extracts cells on the path having a delay time larger than a certain delay time based on the result of the path analyzing means (190) and separates the connection description. As a result, the critical path block (3
The candidates of the cells forming 1) are determined.

Here, in order to clearly explain the procedure of processing, the above two means are described separately, but in order to improve the efficiency of processing of the program, the processing can be performed simultaneously.

The basic idea of the above two means is the same as that of the semiconductor integrated circuit design support apparatus according to the first invention, and the semiconductor integrated circuit design support apparatus according to the fourth invention. In realizing the above, it is practically possible to apply the configuration of the design support device for a semiconductor integrated circuit of the first invention.

Although the logical expression of the critical path block (31) is expressed by the cell connection description,
It should be noted that the actual layout of the critical path block (31) is different from that of the standard cells.

The net analysis means (192) gives information for improving the connection description of the cells constituting the critical path block (31) based on the circuit connection description.

The processing relating to the improvement of the cell connection description will be described later in detail.

The cell relocating means (195) relocates cells on the basis of the information given by the net analyzing means (192), and finally the critical path block (31).
Determine the connection description of the cells that make up the cell.

Next, the processing of the net analysis means will be described with reference to the examples of FIGS. The net analysis means includes [1] buffer position analysis means (193),
[2] There is a cell duplication determination means (194), which will be described below. [1] Buffer Position Revision Means (193) The buffer position analysis means (193) determines the position of the buffer included in the critical path block (31) or the driving capability of the buffer connected to the input of the critical path block (31). To analyze.

FIG. 18 shows an example in which the critical path block (31) includes a buffer (21) provided for driving many loads on a certain signal.

Therefore, the buffer position analysis means outputs the output signal (220) from the buffer (21) to the critical path block (31) for the buffer (21) connected to the input terminal of the critical path block (31). If it has a configuration that is also output to the outside of, the information that this can be rearranged outside the critical path block (31) is given.

For example, as shown in FIG. 19, the critical path block (31) is input, and the critical path block (21) immediately after passing through the one-stage buffer (21) in the critical path block (31). The signal (502) that is output to the outside of 31) is replaced with the signal that is input to the critical path block (31) by moving the buffer (21) to the outside of the critical path block (31). You can As a result, the critical path path block (3
The terminals (201 to 205) of 1) are reduced, and the wiring overhead between the critical path block (31) and the standard cell portion is reduced.

Further, the buffer position analyzing means inserts a new buffer in consideration of the size of the driving load (see FIG. 20). That is, the buffer (2
When the load of the standard cell part (32) connected to the output of 5) is large, the delay time of the signal (210) input to the critical path block (31) becomes large due to the influence. Therefore, as shown in FIG.
2) is inserted to distribute the load between the critical path block (31) and the standard cell unit (32).

The critical path block (31)
It is also possible to replace the buffer (21) that has moved out of the space with a buffer having a different driving force. [2] Cell duplication determination means (194) The cell duplication determination means (194) is configured such that all input / output signals of cells in the critical path block (31) are from outside the critical path block (31) (that is, in the standard cell section). (From (32)), check whether it is observable.
If it is observable, a cell equivalent to the above cell can be placed (reproduced) in the standard cell section (32).

First, the following condition A must be satisfied in order to be able to observe all output signals of the cell. (A) "The cell output signal is directly output to the outside of the critical path block (31)" or "The cell output signal is output to the outside of the critical path block (31) through either a buffer or an inverter. Has been output to
Either of the above is established.

Further, in order to be able to observe all the input signals of the cell, it is necessary to satisfy one of the following three conditions. (B-1) "The input signal of the cell is directly input from outside the critical path block (31)." (B-2) "The input signal of the cell passes through either the buffer or the inverter. Critical path block (3
1) Input from outside. "(B-3)" The input signal of the cell is the output signal of the cell directly inside the critical path block (31) and is output outside from the critical path block (31). "Next, FIG. The process of cell relocation according to the fourth aspect of the invention will be specifically described with reference to FIG.

To simplify the description, in the example shown in FIG. 21, four cells (301, 302, 303, 304) out of the cells included in the critical path block (31) are included.
think of. Two NANs are provided outside the critical path block (31) (that is, the standard cell portion (32)).
Consider the D cell (305, 306). These two cells have a signal (3) from the critical path block (31).
20, 321) are respectively connected via terminals (309, 310). In the example of FIG. 21, the NAND cell (301) and the NOR cell (302) are subject to cell duplication.

FIG. 22 shows the result of cell duplication. N in the critical path block (31)
The input signal (316, 315) and output signal (317) of the AND cell (301) (however, the output signal (320) outside the critical path block (31)) and the input signal (313, 314) of the NOR cell (302). ) And the output signal (318) (the same as the output signal (321)) are observable from outside the critical path block (31), so that they are duplicates of the NAND cell (307) and NO, respectively.
The R cell (308) can be placed outside the critical path block 31). (That is, condition (A), (B-
Satisfies 1). 22) If it is determined that the overhead of wiring reduces the effect of optimization in these input / output signals (313 to 316, 320, 321) shown in FIG. As shown, it is possible to reduce the wiring overhead by placing a copy of the cell in the critical path block (31) in the standard cell section (32).

Due to the cell duplication, the signals (320, 32) output from the critical path block (31) are output.
1) and the terminals (309, 310) can be reduced. on the other hand,
Duplicate NAND instead of signal (320, 321)
Output signal (3) of the cell (307) and the NOR cell (308)
The NAND cells (305, 306) are input to (30, 331). As a result, the NOR cell (301) and the NAND cell (3) in the critical path block (31) are
The load of 02) can be reduced respectively. Also,
The signals (320, 321) are respectively the signals (330, 33).
1), and because the terminals (309) and (310) of the critical path block (31) are reduced, the wiring restrictions on the signals (330, 331) can be relaxed.

The cell relocating means, based on the information obtained from the net analyzing means, has a connection description c_path (111) which constitutes a path to be optimized and a circuit connection description nonc_path (which describes other parts). 112)
And the wiring constraint information c_cnst (161)
Is output.

According to the semiconductor integrated circuit design support apparatus of the fourth embodiment, the macroblock (critical path block (31)) for optimization and the connection information of the entire circuit are analyzed. , Some cell duplicates,
A semiconductor integrated circuit with high performance can be generated by rearranging the buffer and changing the connection description of the circuit.

[0189]

As described above, according to the first invention, in the layout design by the cell-based method,
It is expected that the circuit performance will be improved without designing a new functional cell that optimizes the performance at the layout level by handwriting. In addition, the layout design procedure of the functional cell by handwriting, which has been performed for improving the performance, can be considerably reduced, and the design cost after the layout level can be reduced.

Further, according to the second invention, it is possible to provide a semiconductor integrated circuit capable of realizing high performance while achieving a high mass production effect by incorporating a block having a simple function.

Furthermore, according to the third invention, the period until the layout design of a functional cell having a new function can be greatly shortened, and the matrix of the gate array to be used can be reused, so that the cost can be greatly reduced. Moreover, it can be applied to a wider range of application fields.

Furthermore, according to the fourth invention, it is possible to suppress the wiring overhead between the block (critical path block) for optimization in consideration of the optimization of performance at the layout level and the standard cell.
As a result, not only can the optimization effect due to the critical path block be improved, but also the number of terminals of the critical path block can be reduced, the performance improvement effect due to the reduction of the load of intermediate nodes inside the critical path block, and the layout level. There is an effect that the load of the optimization program can be reduced, and the load of the placement and routing program can be reduced by relaxing restrictions on cell positions when performing automatic placement and routing.

[Brief description of drawings]

FIG. 1 is a block diagram for realizing a semiconductor integrated circuit design support apparatus according to a first invention.

FIG. 2 is a diagram showing a floor plan according to an embodiment of the first invention.

FIG. 3 is a diagram showing a distribution of delay times of paths in the first invention.

FIG. 4 is a schematic diagram showing a first embodiment of the second invention.

FIG. 5 is a schematic view showing a second embodiment of the second invention.

FIG. 6 is a diagram showing a cell structure used in a first transistor array region in the second invention.

FIG. 7 is a diagram showing a cell structure used in a second transistor array region in the second invention.

FIG. 8 is a diagram showing a design flow of an embodiment in the third invention.

FIG. 9 is a diagram showing a configuration of a functional cell in a third invention.

FIG. 10 is an explanatory diagram of optimization of functional cells and non-functional cells according to an embodiment of the third invention.

FIG. 11 is a configuration diagram of a functional cell in a third invention.

FIG. 12 is a diagram showing a conventional cell-based standard floor plan for the first invention.

FIG. 13 is a diagram showing a design example in which a general-purpose function cell in the third invention is reused.

FIG. 14 is a diagram showing a conventional design flow for the third invention.

FIG. 15 is a diagram illustrating a path having a delay time as a factor that hinders optimization of a circuit layout.

FIG. 16 is a diagram illustrating a path having a delay time as a factor that hinders optimization of a circuit layout.

FIG. 17 is a schematic configuration diagram of a semiconductor integrated circuit design support device in a fourth invention.

FIG. 18 is a diagram showing a specific example of a case where the buffer can be rearranged obtained according to the fourth invention.

FIG. 19 is a diagram showing the rearrangement of the layout of the buffer obtained according to the fourth invention.

FIG. 20 is a diagram showing the rearrangement of the layout of the buffer obtained according to the fourth invention.

FIG. 21 is a diagram showing a specific example of a case where cell duplication processing is possible.

FIG. 22 is a diagram showing a specific example of the cell duplication rearrangement process obtained by the fourth invention.

[Explanation of symbols]

11 Path Analysis and Path Extraction Program 12 Parameter Optimization Program 13 Cell Mapping Program 14 Symbolic Layout Synthesis Program 15 Compactor (Compaction Program) 16 Constraint Information Extraction Program 17 Automatic Placement and Routing Program 31 Critical Path Block 32 Standard Cell 41 For High Integration Functional cell block (RAM, register file, etc.) 51 Addition functional cell 52 First transistor array region 53, 54 Second transistor array region 55 Polysilicon layer 56 Diffusion layer 71 Functional cell enhancement macro logic description 72 Non-functional cell Logical description of part 73 Initial constraint 74 Constraint information about functional cell (outline wiring) 75 Constraint information about non-functional cell 76 Macro cell placement position of functional cell strengthening macro Information 77 Macro cell placement position information of non-functional cell section 78 Layout call of functional cell, constraint information (detailed wiring) 81 Basic functional cell 82 Gate array section 83 Functional enhancement macro 84 Functional cell 85 Non-functional cell section 86-90 Terminals 91, 92 Macro cell block of non-functional cell part 100 Standard cell library: sc_lib 101 Logical description expression of circuit: cir _logc 111 Critical path part: c _path 112 Parts other than critical path part: cnoc_path 121 Transistor width recurrence value and wiring constraint: t _Op
t 141 Symbolic layout: c _smb 151 Layout data of critical path block: c _layout 161 Restriction information of block: c _cnst 171 Layout of part excluding critical path block: nonc_layout 181 Total layout: torl_layout 190 Path analysis means 191 Cell extraction means 192 Net analysis means 193 Buffer position relocation means 194 Cell duplication determination means 195 Cell relocation means 201-205, 309-310 Terminals of critical path block that can be deleted by cell duplication 305,306 Output from critical path block Examples of cells for inputting signals 307, 308 Examples of cells duplicated in standard cell section 313 to 316 Signals input to critical path block 320, 321 Critical path Signal 501 path is outputted from the replicated cell signal 330 and 331 standard cell unit output from the lock A 502 path B 503 pass C 504 path D

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/04 21/822 8122-4M H01L 21/82 C 8832-4M 27/04 A

Claims (5)

[Claims] 1. In a cell-based layout design method, a special block for automatically optimizing a width of a transistor, a width and a length of a wiring for a path for which a delay time is to be optimized in a circuit to be realized. Is a design support device for designing a semiconductor device having a delay time calculated from a logic description of a circuit, and a path having a delay time larger or smaller than a certain delay time is searched and extracted for optimization. Path analysis and path extraction means for separating a target path and a non-target path, and by the means, load information of the transistor on the extracted optimization target path is calculated, and the physical shape of the transistor is calculated. The wiring shape is calculated based on the parameter optimization means for calculating and outputting the optimum value and the physical shape of the transistor and the wiring shape information obtained by the means. Symbolic layout synthesizing means for synthesizing the symbolic layout of the issued path, compaction means for determining an actual layout having accurate shape layout information of transistors and wirings based on the symbolic layout obtained by the means, and the means. The semiconductor device is characterized by comprising constraint information extraction means for extracting the layout shape and terminal information obtained by the above, and automatic placement and routing means for performing placement and routing in a cell-based layout based on the logic description of the circuit. Integrated circuit design support device. 2. In an integrated circuit which is manufactured in advance by performing a part of a manufacturing process in common and which realizes various different functions in the remaining manufacturing processes, at least a part of the integrated circuit has a fixed function. In an integrated circuit in which a functional cell is prepared in advance and the function of that portion cannot be changed, at least two functionally changeable regions are provided by design, and at least one of them is adjacent to the functional cell. Integrated semiconductor circuit. 3. A transistor structure disposed in at least one of the function changeable regions is different from a transistor structure disposed in another region at a stage where a part of the manufacturing process is commonly manufactured in advance. The semiconductor integrated circuit according to claim 2, wherein: 4. A gate array in which functional cells can be embedded, means for separating a logical description into at least two descriptions from the whole description, and the constraint information given to each description separated by the separating means. Under the assumption, the relative positional relationship of the macro cells that realizes the basic logical function is assumed, and at least the wiring length is estimated and evaluated therefrom, and the rough placement and routing means for outputting this is provided, and the placement between the macro cells and the macro cell Detailed wiring means for performing actual wiring between the two, and the rough placement and routing means performs rough placement and routing for one separated description, and as a result, constraint information and rough placement and routing for the one description. A means for outputting a result, and a general layout and wiring result of one separated description, the outputted constraint information, and a general layout and wiring of one description among other separated descriptions. It can be input at the time of execution, and it is possible to perform rough placement and routing based on the constraint information. Depending on the characteristics of the target circuit, the evaluation function when performing rough placement and routing can also be changed accordingly. The detailed placement and routing means can input the detailed placement and routing result of one separated description, the output information and known layout data, and the detailed placement and routing result of one separated description. A design support device for a semiconductor integrated circuit, characterized in that the evaluation function when executing detailed placement and routing can be changed in accordance with the characteristics of the target circuit. 5. A target for optimization by calculating a delay time from a circuit connection description (netlist), searching for a path having a delay time larger or smaller than a certain fixed time, and extracting cells on the path. Path analysis and path extraction means for separating the circuit connection description by the target path and non-target path, and connection of cells on the optimization target path separated by the path analysis and path extraction means Description (netlist)
And a cell analysis unit that corrects the connection description of the entire circuit and the connection description of the separated cell based on the result analyzed by the net analysis unit while preserving the logic of the entire circuit. A semiconductor circuit design support device comprising: an arranging unit; and the net analyzing unit, which includes a buffer position analyzing unit and a cell duplication judging unit, and the buffer position analyzing unit. Is characterized by analyzing the connection description of the circuit, analyzing the position of the buffer, and the driving capability, calculating the optimum buffer position and driving capability, and outputting the calculation result, wherein the cell duplication determining means is: Analyzing the circuit connection description and preserving the original logical relationship while optimizing the duplication of cells and equivalent cells in the circuit connection description related to the path to be optimized Possible to determine whether to place the circuit connection description of the path to be non-target, a semiconductor circuit design support apparatus is characterized in.