JPH0355783B2 - - Google Patents
Info
- Publication number
- JPH0355783B2 JPH0355783B2 JP24006585A JP24006585A JPH0355783B2 JP H0355783 B2 JPH0355783 B2 JP H0355783B2 JP 24006585 A JP24006585 A JP 24006585A JP 24006585 A JP24006585 A JP 24006585A JP H0355783 B2 JPH0355783 B2 JP H0355783B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion part
- diffusion
- oxide film
- resin
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000009792 diffusion process Methods 0.000 claims description 38
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000011347 resin Substances 0.000 claims description 16
- 229920005989 resin Polymers 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 description 10
- 239000012535 impurity Substances 0.000 description 9
- 238000007789 sealing Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Landscapes
- Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〔技術分野〕
この発明は、二重拡散により形成される縦型の
MOS型半導体素子の封止に用いる樹脂の評価、
主に樹脂中の不純物イオンの量を評価する技術に
関する。[Detailed Description of the Invention] [Technical Field] This invention relates to a vertical type formed by double diffusion.
Evaluation of resins used for sealing MOS type semiconductor devices,
Mainly related to technology for evaluating the amount of impurity ions in resin.
従来は封止樹脂中の不純物による影響を見るた
めに第２図に示すようにソース電極１とドレイン
電極２間のゲート電極３の一部を削除した形の
MOS型半導体素子が使用され、リーク電流によ
り不純物量を検知することが行なわれていた。
Conventionally, in order to examine the influence of impurities in the sealing resin, a part of the gate electrode 3 between the source electrode 1 and the drain electrode 2 was removed, as shown in Fig. 2.
MOS type semiconductor elements were used, and the amount of impurities was detected by leakage current.
図示例のMOS型半導体素子は、Ｐ型のシリコ
ン基板８と使用したＮチヤンネルMOS型半導体
素子で、４はドレイン領域、５はソース領域、６
は表面の酸化膜であり、ベース領域７上に設けら
れた電極３のソース例半分が削除され、その表面
全体を樹脂７封止した構造をもつ。 The illustrated example MOS type semiconductor element is an N channel MOS type semiconductor element using a P type silicon substrate 8, in which 4 is a drain region, 5 is a source region, and 6 is a drain region.
is an oxide film on the surface, and has a structure in which half of the source of the electrode 3 provided on the base region 7 is removed and the entire surface is sealed with a resin 7.
ゲート電極３に正の電圧を加えるとき、電界の
向きは図中矢印の如く酸化膜６の表面に向かい樹
脂７中に不純物イオン、例えばNa+が存在すると
き、ソース電極１側の酸化膜６表面に広がり、こ
の表面に集つた正イオンによりゲート電極３のな
い部分にもチヤネルが伸び、ゲート電極３のない
部分にも電圧が加わつたように作用し、ドレイン
電極２とソース電極１間にリーク電流が流れるこ
とにより、リーク電流の大小により樹脂７中の不
純物イオン量を評価するものである。 When applying a positive voltage to the gate electrode 3, the direction of the electric field is directed toward the surface of the oxide film 6 as shown by the arrow in the figure, and when impurity ions such as Na + are present in the resin 7, the direction of the electric field is directed toward the surface of the oxide film 6 on the source electrode 1 side. The positive ions that spread over the surface and gather on this surface cause a channel to extend to the area where the gate electrode 3 is not present, acting as if a voltage is applied to the area where the gate electrode 3 is not present, and causing a voltage to be applied between the drain electrode 2 and the source electrode 1. As the leakage current flows, the amount of impurity ions in the resin 7 is evaluated based on the magnitude of the leakage current.
しかし、このMOS型半導体素子では微小なリ
ーク電流の検出が困難であるという欠点があつ
た。 However, this MOS type semiconductor device has a drawback in that it is difficult to detect minute leakage currents.
本発明は、二重拡散により形成される縦型の
MOS型半導体素子の封止に用いる樹脂の評価、
主に樹脂中の不純物イオンの量を評価するのに用
いるMOS型半導体素子を提供することを目的と
する。
The present invention is a vertical type formed by double diffusion.
Evaluation of resins used for sealing MOS type semiconductor devices,
The object of the present invention is to provide a MOS type semiconductor element mainly used for evaluating the amount of impurity ions in a resin.
この発明の要旨とするところは、第１図実施例
に示さるる如く、裏面にドレイン電極２を有する
第１伝導型の半導体基板８の表面上に、第１伝導
型とは逆の性質を有する第２伝導型の深い第１拡
散部４を形成し、この第１拡散部４の上面部中に
第１伝導型の第２拡散部５を周囲を第１拡散部４
で囲むソース領域として形成、第１拡散部４と
第２拡散部５をソース電極１で接続し、ゲート電
極３を、酸化膜６を介して半導体基板８の表面よ
り第１拡散部４上まで第２拡散部５との間に間隔
をへだてるようにして設け、表面を樹脂７で封止
して成るMOS型半導体素子である。
The gist of the present invention is that, as shown in the embodiment of FIG. A deep first diffusion part 4 of the second conductivity type is formed, and a second diffusion part 5 of the first conductivity type is formed in the upper surface of the first diffusion part 4.
The first diffusion part 4 and the second diffusion part 5 are connected by the source electrode 1, and the gate electrode 3 is formed from the surface of the semiconductor substrate 8 to above the first diffusion part 4 via the oxide film 6. This is a MOS type semiconductor element which is provided with a space between it and the second diffusion part 5 and whose surface is sealed with resin 7.
以下この発明を第１図に示す実施例に基づいて
説明する。 The present invention will be explained below based on the embodiment shown in FIG.
図示例は二重拡散により形成される縦型のＮチ
ヤンネル型のMOS型半導体素子である。N-型シ
リコン基板を第１伝導型の半導体基板８とし、そ
の上面側に第２伝導型としてＰ型の第１拡散部４
を形成し、第１拡散部４の上面中に外周を第１拡
散部４で囲まれるようにN+型の第２拡散部５を
ソース領域として形成して成るものである。半
導体基板８の裏面側はN+層９が形成され、ここ
にドレイン電極２が設けられている。 The illustrated example is a vertical N-channel MOS semiconductor element formed by double diffusion. An N - type silicon substrate is used as a first conduction type semiconductor substrate 8, and a P type first diffusion portion 4 is provided as a second conduction type on the upper surface side.
, and an N + type second diffusion part 5 is formed as a source region in the upper surface of the first diffusion part 4 so that the outer periphery is surrounded by the first diffusion part 4. An N + layer 9 is formed on the back side of the semiconductor substrate 8, and a drain electrode 2 is provided here.
６は酸化膜で半導体基板８から第２拡散部５の
表面を被覆しており、第１拡散部４の中央部上に
は開口している。この酸化膜６の第２拡散部５上
にソース電極１が設けられている。 An oxide film 6 covers the surface of the second diffusion part 5 from the semiconductor substrate 8, and is open above the center of the first diffusion part 4. A source electrode 1 is provided on the second diffusion portion 5 of this oxide film 6.
１０は酸化膜で、酸化膜６上に半導体基板８の
表面から第１拡散部４の外周に至る部分及び酸化
膜６の開口部上を被覆している。このようにして
第１拡散部４の内周側と第２拡散部５の外周側の
部分は酸化膜１０で被覆されないままになつてい
る。以上のような状態で、酸化膜６と１０の表面
上は樹脂７で封止されている。 Reference numeral 10 denotes an oxide film that covers the oxide film 6 from the surface of the semiconductor substrate 8 to the outer periphery of the first diffusion portion 4 and over the opening of the oxide film 6. In this way, the inner peripheral side of the first diffusion part 4 and the outer peripheral side of the second diffusion part 5 remain uncovered with the oxide film 10. In the above state, the surfaces of the oxide films 6 and 10 are sealed with the resin 7.
而してゲート電極３に電圧を加えると電界が矢
印で示すようにゲート電極３の上面より第１拡散
部４の第２拡散部５上の露出した酸化膜６に向か
い、封止した樹脂７中の正イオンがこの酸化膜６
の表面上に集まり れに対応してドレイン領域で
ある半導体基板８とソース領域である第２拡散部
５間の酸化膜６下にはチヤネルが形成され、リー
ク電流が流れる。このようにしてソース電極１と
ドレイン電極２間が導通する。従つてこのリーク
電流量を検知することにより樹脂７中の不純物イ
オン量を知ることができる。 When a voltage is applied to the gate electrode 3, the electric field is directed from the upper surface of the gate electrode 3 to the exposed oxide film 6 on the second diffusion part 5 of the first diffusion part 4, as shown by the arrow, and the sealed resin 7 The positive ions inside this oxide film 6
Correspondingly, a channel is formed under the oxide film 6 between the semiconductor substrate 8, which is the drain region, and the second diffusion region 5, which is the source region, and a leakage current flows. In this way, the source electrode 1 and the drain electrode 2 are electrically connected. Therefore, by detecting the amount of leakage current, the amount of impurity ions in the resin 7 can be known.
尚、上記実施例では、封止樹脂中の正イオン量
を評価する場合を示したが、負イオン量を評価す
る場合は、ＰチヤンネルMOS型半導体素子とし
て本発明を実施し、シリコン基板８に正電圧を、
ゲート電極３に負電圧を加えるようにすればよ
い。 In the above example, a case was shown in which the amount of positive ions in the sealing resin was evaluated, but when evaluating the amount of negative ions, the present invention was implemented as a P-channel MOS type semiconductor element, and the silicon substrate 8 was positive voltage,
A negative voltage may be applied to the gate electrode 3.
以上のように本発明のMOS型半導体素子にあ
つては、第２伝導型の第１拡散部が第１伝導型の
第２拡散部を囲むように形成されているためドレ
イン領域となる第１拡散部とソース領域となる第
２拡散部間に形成されるチヤネル長さに対してチ
ヤネル幅が大きくなり、不純物量が少なくても大
きなリーク電流が流れ、高感度で封止樹脂中の不
純物イオン量を検知することができるのである。
As described above, in the MOS type semiconductor device of the present invention, since the first diffusion part of the second conductivity type is formed to surround the second diffusion part of the first conductivity type, the first diffusion part becomes the drain region. The channel width is larger than the length of the channel formed between the diffusion part and the second diffusion part which becomes the source region, and even if the amount of impurities is small, a large leakage current flows, and impurity ions in the sealing resin are detected with high sensitivity. The amount can be detected.
第１図はこの発明の一実施例を示す図で、ａは
断面図、ｂはａのＡ−Ａ矢視図、第２図は従来例
を示す図で、ａは断面図、ｂ平面図である。
１……ソース電極、２……ドレイン電極、３…
…ゲート電極、４……第１拡散部、５……第２拡
散部、６……酸化膜、７……樹脂、８……半導体
基板、９……N+層、１０……酸化膜。
Fig. 1 is a diagram showing an embodiment of the present invention, where a is a sectional view, b is a view taken along the line A-A of a, and Fig. 2 is a diagram showing a conventional example, where a is a sectional view and b is a plan view. It is. 1... Source electrode, 2... Drain electrode, 3...
... Gate electrode, 4 ... First diffusion part, 5 ... Second diffusion part, 6 ... Oxide film, 7 ... Resin, 8 ... Semiconductor substrate, 9 ... N + layer, 10 ... Oxide film.
Claims (1)
半導体基板８の表面上に、第１伝導型とは逆の性
質を有する第２伝導型の深い第１拡散部４を形成
し、この第１拡散部４の上面部中に第１伝導型の
第２拡散部５を周囲を第１拡散部４で囲むソース
領域として形成し、第１拡散部４と第２拡散部
５をソース電極１で接続し、ゲート電極３を、酸
化膜６を介して半導体基板８の表面より第１拡散
部４上まで第２拡散部５との間に間隔をへだてる
ようにして設け、表面を樹脂７で封止して成る
MOS型半導体素子。1. A deep first diffusion region 4 of a second conductivity type having properties opposite to that of the first conductivity type is formed on the surface of a semiconductor substrate 8 of a first conductivity type having a drain electrode 2 on the back surface. A second diffusion part 5 of the first conductivity type is formed in the upper surface of the diffusion part 4 as a source region surrounded by the first diffusion part 4, and the first diffusion part 4 and the second diffusion part 5 are connected to each other by the source electrode 1. A gate electrode 3 is provided via an oxide film 6 from the surface of the semiconductor substrate 8 to above the first diffusion part 4 with a gap between it and the second diffusion part 5, and the surface is covered with a resin 7. sealed with
MOS type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24006585A JPS6298246A (en) | 1985-10-25 | 1985-10-25 | Mos type semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24006585A JPS6298246A (en) | 1985-10-25 | 1985-10-25 | Mos type semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6298246A JPS6298246A (en) | 1987-05-07 |
| JPH0355783B2 true JPH0355783B2 (en) | 1991-08-26 |
Family
ID=17053963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24006585A Granted JPS6298246A (en) | 1985-10-25 | 1985-10-25 | Mos type semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6298246A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4546796B2 (en) * | 2004-09-16 | 2010-09-15 | パナソニック株式会社 | Semiconductor device |
-
1985
- 1985-10-25 JP JP24006585A patent/JPS6298246A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6298246A (en) | 1987-05-07 |
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