JPH03120830A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a lateral transistor having stable hFE by forming a metal film connected with the emitter region or the base region of a lateral transistor, via an insulating film, on the part between the collector and the emitter. CONSTITUTION:The title device is provided with the following; a first and a second regions 3, 4 of opposite conductivity type formed on a semiconductor substrate 1 of a conductivity type, a third region 5 containing high concentration impurity of a conductivity type, an insulating film 2 formed on the substrate 1, and electrode wirings 6-8 connected with the first, the second and the third regions 3-5, via an aperture formed in the insulating film 2. A wiring 10 connected with the first region 3 or the third region 5 is formed on the insulating film 2 between the first region 3 and the second region 4. For example, a channel stopper 10 is formed on the part between a collector and an emitter, via the insulating film 2, at the same time when a collector electrode 6, an emitter electrode 7 and a base electrode 8 are formed. Wiring of the channel stopper 10 is connected with the emitter electrode 7 or the base electrode 8, at the other position.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a high voltage lateral transistor and a high voltage lateral thyristor suitable for integrated circuits.

[Conventional technology]

Conventionally, high-voltage lateral transistors and high-voltage lateral thyristors have been developed by diffusing p-type impurities into an n-type semiconductor substrate, for example, in the case of a lateral transistor.
In order to form collector regions and form contacts to the base region, n-type impurities are diffused to form high-concentration n-type impurities.
The structure was such that positive type regions were formed and electrodes were taken out from these regions. This will be further explained below using the drawings.

FIG. 3 is a schematic cross-sectional view of a semiconductor chip showing an example of a conventional lateral transistor. The manufacturing method will be explained below.

First, the insulating film 2 is formed on one main surface of the n-type semiconductor substrate 1 . Next, p-type impurities are selectively diffused to form a collector region 3 and an emitter region 4, and an n+-type region 5 whose impurity concentration is higher than that of the n-type semiconductor substrate 1 in order to form an ohmic contact to the base region. Form. Next, a collector electrode 6 makes ohmic contact with these diffusion regions.
．． An emitter electrode 7 and a base electrode 8 were formed, covered with a protective film 14, and further sealed with a mold resin or the like.

[Problem to be solved by the invention]

However, in the structure of the conventional resin-sealed lateral transistor described above, there are several tens of seven points between the emitter and the collector.
When applying the above high voltage, as shown in Figure 3,
A negative electric field extends to the oxide film on the emitter and collector,
A depletion layer 9 is formed, an inversion layer is generated between the emitter and the collector, and the effective distance W between the emitter and collector is often shortened. For this reason, a phenomenon occurs in which the direct current amplification factor hPE of the transistor increases, and a small base current causes a large leakage current between the emitter and the collector.

Also, in the case of Cyrisk, there are several tens of V between the cando and the anode.
When a voltage of Becomes shorter. As a result, a phenomenon occurs in which the hPE of the transistor formed by the anode gate and the n-gate of the thyristor increases, and a large leakage current occurs between the anode and the cathode due to a small n-gate current.

[Means to solve the problem]

A semiconductor device according to a first aspect of the present invention includes first and second regions of opposite conductivity types formed on a semiconductor substrate of one conductivity type, a third region containing high concentration impurities of one conductivity type, and a third region formed on a semiconductor substrate of one conductivity type. through the insulating film formed in the first insulating film and the opening provided in the insulating film. In a semiconductor device having an electrode wiring connected to a second region and a third region, an electrode wiring connected to the first region or the third region is provided on the insulating film between the first region and the second region. It is equipped with additional wiring.

A second semiconductor device of the present invention includes first and second regions of opposite conductivity types formed on a semiconductor substrate of one conductivity type, a third region containing high concentration impurities of one conductivity type, and a third region containing high concentration impurities of one conductivity type; through the insulating film formed in the first insulating film and the opening provided in the insulating film. In a semiconductor device having an electrode wiring connected to a second and a third region, a diffusion region of one conductivity type in the first region, an electrode wiring connected to the diffusion region, and a field plate connected to the electrode wiring. It has been established.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention, particularly showing the case of a lateral transistor.

An insulating film 2 is formed by thermal oxidation of an n-type semiconductor substrate 1 having a relatively high resistivity (5 to 30 Ω crn), a window is selectively opened in the insulating film 2 by photolithography, a p-type semiconductor region is formed, and a collector is formed. A region 3 and an emitter region 4 are provided. Next, a window is opened in the insulating film 2 by selective photolithography again to provide an n++ diffusion layer, and a base diffusion layer 5 as a third region is provided. Next, we open the window of the ohmic contact section and see the first layer of AJ? Provide electrode wiring,
Collector electrode 6. Emitter electrode7. A base electrode 8 is provided. At the same time, the channel stopper 1 according to the present invention
0 is provided on the collector-emitter through an insulating film. This wiring as the channel stopper 10 is connected to the emitter electrode 7 or the base electrode 8 at another position.

With such a structure, the depletion layer 9 extending from the collector region 3 is not extended by the channel stopper 10, so the base width w1 does not become narrower, and therefore the hFE of the lateral PNP Tr does not become larger.

Next, a glabellar nitride film 11 is formed, a through hole is formed, and a collector field plate 12 and an emitter field plate 13 are provided by two-layer wiring. This field plate is provided to obtain a withstand voltage of several tens to several hundreds of volts. A protective film 14 is provided thereon to cover it with a nitride film.

FIG. 2 is a sectional view of a semiconductor chip according to a second embodiment of the present invention, and shows the case where the present invention is applied to a lateral thyristor.

The difference between the second embodiment and the first embodiment is that the collector region 3 is formed by an n-gate diffusion layer 31. Anode diffusion layer 41. emitter region 4. The two points are that the name of the base diffusion layer 5 is changed to an n-gate diffusion layer 51, and that the cathode diffusion layer 15 is provided within the n-gate diffusion layer 31.

This second embodiment also includes a channel stopper 10, which is connected to the n-gate electrode 81. If such a structure is adopted, the depletion layer 9 extending from the n-gate diffusion layer 31 will not extend due to the Champors 1 to 10;
The base width W2 does not become narrower. Therefore, the anode P
Lateral PNP composed of n gates
The hpg of the Tr will not increase.

〔Effect of the invention〕

As explained above, the present invention provides a metal film connected to the emitter or base region of a lateral transistor, which is a semiconductor device, through an insulating film between the collector and the emitter. When a voltage higher than V is applied, a negative electric field due to polarization of the mold resin material is prevented from being applied to the collector and emitter as well as the insulating film, and the bus between the collector and emitter is not effectively shortened. , there is an effect that a lateral transistor with stable hFE can be obtained.

Similarly, in the case of a thyristor, by providing a metal film connected to the n-gate on the anode and the p-gate via an insulating film, the minute leakage current flowing to the n-gate is amplified and the leakage current between the anode and cathode is reduced. A lateral thyristor with stable pressure resistance can be obtained.

[Brief explanation of drawings]

1 and 2 are sectional views of first and second embodiments of the present invention, and FIG. 3 is a sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1... N-type semiconductor substrate, 2... Insulating film, 3... Collector region, 4... Emitter region, 5... Base diffusion layer, 6... Collector electrode, 7... Emitter electrode,
8... Base electrode, 9... Depletion layer, 10... Channel stopper 11... Interlayer insulating film, 12... Collector field plate, 13... Emitter field plate, 14... Protective film , 15... Cathode diffusion layer, 16... Cathode electrode, 17... Cathode field plate, 31... N gate diffusion layer, 41...
・Anode diffusion layer, 51...n gate diffusion layer, 61・
...p gate electrode, 71...anode electrode, 81...
・N gate electrode, 121...p gate field plate.

Claims (2)

[Claims] (1) A first semiconductor substrate of an opposite conductivity type formed on a semiconductor substrate of one conductivity type.
and a third region containing a second region and a high concentration impurity of one conductivity type.
A semiconductor device having a region, an insulating film formed on the semiconductor substrate, and an electrode wiring connected to the first, second and third regions through an opening provided in the insulating film, A semiconductor device characterized in that a wiring connected to the first region or the third region is provided on the insulating film between the first region and the second region. (2) A first semiconductor substrate of an opposite conductivity type formed on a semiconductor substrate of one conductivity type.
and a third region containing a second region and a high concentration impurity of one conductivity type.
A semiconductor device having a region, an insulating film formed on the semiconductor substrate, and an electrode wiring connected to the first, second and third regions through an opening provided in the insulating film, A semiconductor device characterized in that a diffusion region of one conductivity type, an electrode wiring connected to the diffusion region, and a field plate connected to the electrode wiring are provided in the first region.