JPH0353365A - Data transfer device - Google Patents

Abstract

PURPOSE:To easily decide the best data latch timing with no actual measurement by deciding the data latch timing of the reception side at the transmission side. CONSTITUTION:At the transmission side a data transmission timing signal 13 having a cycle t1 and the duty t2:(t1 - t2) synchronous with the clock signal outputted from a clock generating circuit 1 is produced by a timing generating circuit 2. The signals 13 are counted up by an m-bit counter 3, and an (n - 1)-selector 4 received the timing signals 14 and 15, i.e., the counter output transmits data to the reception side after multiplexing the data in time division. Meanwhile the signal 13, i.e., the output of the circuit 2 undergoes the plus/minus inversion via an inverting circuit 6 and is sent to the reception side. As a result, the best data timing can be easily decided with no actual measurement.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data transfer device that transfers data by time division multiplexing.

(Prior Art) An example of a conventional data transfer device will now be described with reference to FIG.

Data transmission timing generation circuit 1#'i is connected to a delay line circuit 32 that creates switching timing for data to be multiplexed. 1. The transmission timing signal is transferred via the output buffer 35-2'i.

Data to be transmitted is held in data registers 33-1 to 33-n. The gate circuits 34-1 to 34-n switch transmission data using the output of the delay line circuit 2. Multiplex. These data are transferred to the transfer path 4 by the output buffer 35-1.
Sent to 0.

The timing signal sent via the transfer path 40 is received by the input buffer 736-2 and input to the delay line circuit 37 which creates the latch timing of the received data. The delay line circuit 37 includes a timing adjustment circuit 38-1.
~38-n is connected, and this circuit connects delay line circuit 3.
Adjust the output of 7 to the best latch timing.

Data latch circuits 39-1 to 39-n are supplied with adjusted timing signals. Latch received data.

Figure 4 is a diagram showing the data transfer timing.
) shows the timing on the transmitting side, and (b) in the figure shows the timing on the receiving side. Timing signals 11 to l5 are the third
The timing of each line 41 to 45 in the figure is shown.

1 for the above precepts? and data registers 33-i to 33
The data held in -n is the gate circuit 34-1 to 34-3.
4-n, and the transfer path 40 via the buffer 35-1.
．． The input buffer 36-1 passes through the data latch circuit 39.
-1 to 39-n.

At this time, on the transmitting side, the timing signal generation circuit 31 generates a timing signal such as the timing signal 1l shown in FIG. 4(a), and the delay line circuit 32 switches the data! By sequentially delaying the time tx at , and sequentially opening and closing the gate circuit 34 using the output, data is time-division multiplexed.

In addition to the multiplexed data, the timing signal generation circuit 3l
output to the receiving side of Banfa 35-2.36-2
Send via.

On the receiving side, a timing signal such as the timing signal 13 in FIG. 4(b) sent from the transmitting side is delayed by a delay line circuit 37. Furthermore, since the output of the delay line circuit 37 can only be set at fixed time intervals, the timing adjustment circuits 38-1 to 38-n are used to adjust the time from data switching as shown in timing signal 14.15 in FIG. 4(b). 9. Create a data latch timing signal such that t2 becomes t2. Data is latched by data latch circuits 39-1 to 39-n.

(Problem to be Solved by the Invention) In such a conventional data transfer device, the timing adjustment circuits 38-1 to 38-n need to actually measure data transfer in order to determine the latch timing. Ta. 1. In order to create a timing signal on the receiving side, if the environmental conditions on the sending and receiving sides change differently. The drawback was that the timing adjustment circuit had to be readjusted.

The purpose of the present invention is to provide a data transfer device that can easily determine the best data timing without actual measurement, and that does not require readjustment even if there is a change in the environment on the transmitting/receiving side. It is in.

(Means for Solving the Problem) In order to achieve the above object, a data transfer device R according to the present invention is provided.
h The transmitting side circuit and the receiving side circuit. A transfer path connected between the transmitting side circuit button and the receiving side circuit. A data transfer device that transmits time-division multiplexed data and separates and outputs the data on the receiving side. The transmission side circuit includes a timing signal generation circuit that generates a data transfer timing signal synchronized with a clock, and an inversion circuit that inverts the output of the timing signal generation circuit. Multiplicity f of data to be transferred
When n is 9, the logarithm of n with the base 2 is greater than 9, and the mbit counter has an integer mobitm closest to that number and counts up the timing signal, and each data is time-division multiplexed based on the counter output. n-1
With selector. a buffer for transmitting the time division multiplexed signal and the output of the inverting circuit; With the counter. It has a decoder that decodes the received imbit counter output, and a data latch circuit that separates the received time division multiplexed signal using the decoder output.

(Example) Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data transfer device according to the present invention.

The clock generation circuit 1 is connected to a timing signal generation circuit 2 which generates a data transfer timing signal synchronized with a clock output.

This timing signal is input to an mbit counter 3p that counts up the timing signal and an inversion circuit 6.

Timing signal 14 output from mbit counters 3 to 9
．． 15 is input to the n-1 selector 4.

The n-1 selector 4 includes data registers 5-1 to 5- that hold transmission data based on the timing signal 14.15.
The output of n is switched and time division multiplexed.

The time-division multiplexed data is sent to the transfer path 12 by the output buffer 7-1.

On the other hand, the timing signal 16 inverted by the inverting circuit 6
is sent to the transfer path 12 by the output buffer 7-2.

The data and timing signal passing through the transfer path 12 are received by the input buffer 78-1.8-2K, the data is input to the data latch circuit 11-1-11-n, and the timing signal 17 is input to the mbit counter 9. Ru. mb
The it counter 9 counts the timing signal 17, and the count result is decoded by the mn decoder 10. The data passing through the buffer 8-1 is latched into the data launch circuit 11 by this decoder output.

Here, m is larger than the logarithm of n to the base 2. is the integer closest to that number.

FIG. 2 is a diagram showing the data transfer timing of FIG. 1. Figure (a) shows the timing on the transmitting side;
7 represents the timing of each line in FIGS. 13-19.

Now. In this structure, data registers 5-1 to 5-
The data held by nVC passes through the n-1 selector, buffer 7-1, input buffer 8-1, and is latched into data latch circuits 11-1 to 11-n.

On the transmitting side, the clock generator circuit l outputs 9 as shown in Figure 2 (
A period tl. synchronized with a clock signal such as a). A duty t2'' (tl-t2) (7J data transmission timing signal is generated by the timing generation circuit 2. This timing signal 13 is counted up by the mbit counter 3, and the timing signal 14.15 which is the output of the counter is generated.
The n-1 selector 4 that receives the signal 'i' performs full time division multiplexing on the data and sends it to the receiving side M, as shown in FIG. 2(a).

1. The timing signal which is the output of the timing signal generation circuit 2 is inverted from positive to negative by the inverting circuit 6 and then transmitted to the receiver 8 side.

On the receiving side, Hanwha 7-2. The timing signal 17 received by 8-2kALT is counted up by the m-bit counter 9, and its output is sent to the ij m-n decoder lO.
decoded with Based on the decoded output, the data latch circuits 1l-1 to 11-n are transferred to the buffer 7-1.8-1i.
The passed data is latched as shown in Figure 2 (b3).

As described above, according to the present invention, the latch timing signal of the data latch circuit is controlled by the latch timing signal of the data latch circuit. It is possible to create the p-counter 9 and decoder 10 using only the timing signal sent from the sending and borrowing side without using a delay line circuit and creating it on the receiving side.

(Effects of the Invention) As described above, according to the present invention, in a data transfer device that multiplexes data, the data latch timing on the receiving side, which could not be determined without actual measurement, can be determined from the transmitting side. Therefore, there is an effect that the best data latch timing can be easily determined without actual measurement.

However, the data latch timing can be determined only on the transmitting side. Even if the environmental conditions on the sending and receiving sides change differently. This has the effect that there is no need to readjust the data latch timing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data transfer device according to the present invention, and FIG. 2 is a diagram showing the timing of data transfer in FIG. Figure 3 is a diagram showing an example of a conventional data transfer device. FIG. 4 is a diagram showing the timing of data transfer in FIG. 1. 1... Clock generation circuit 2.31... Timing signal generation circuit 3... mbi
t counter 4...n-1 selector 5.33...data register 6...inverting circuit 7
...Output buffer 8...Input buffer 9...
ml>it counter 10...m-n decoder 11
...Data latch circuits 13 to 19...Timing signal 32.37...Delay line circuit 34...Gate circuit 35...Output buffer 6.
...Input buffer 8...timing'? Ai! i circuit 9...data latch circuits 1 to 45...timing signal

Claims (1)

[Claims] A data transfer device consisting of a transmitting side circuit, a receiving side circuit, and a transfer path connected between the transmitting side circuit and the receiving side circuit, and transmits data by time division multiplexing, and separates and outputs the data on the receiving side. In the transmitting circuit, the transmitting side circuit includes a timing signal generating circuit that generates a data transfer timing signal synchronized with a clock, an inverting circuit that inverts the output of the timing signal generating circuit, and a multiplicity of data to be transferred.
Then, each data is time-divided based on an mbit counter that counts up the timing signal and has a bit number of an integer m that is larger than the logarithm of n to the base 2 and is closest to that number. It has an n-1 selector for multiplexing, a buffer for transmitting the time division multiplexed signal and the output of the inverting circuit, and the receiving side circuit has a buffer for receiving received data and a timing signal, and counts up the received timing signal. A data transfer device comprising: a receiving side mbit counter; a decoder that decodes the receiving side mbit counter output; and a data latch circuit that separates a received time division multiplexed signal using the decoder output.