JPH03145349A - Data transfer equipment - Google Patents

Abstract

PURPOSE:To eliminate the need for readjustment of timing by deciding a data latch timing at a receiver side from a sender side when data is communicated multiplexingly. CONSTITUTION:A timing signal generating circuit 2 generates a data transmission timing signal synchronously with a clock signal outputted from a clock generating circuit 1 at the sender side. Then an n-bit shift register 3 receiving the timing signal 1 as its clock input shifts an input data '1' sequentially and a multiplexer 4 receiving a timing signal being an output of the shift register 3 applies time division multiplex to the data and sends the result to a receiver side. In the case of communication with data multiplex, the data latch timing of the receiver side having not been decided without actual measurement is measured from the sender side, then the readjustment of the data latch timing is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to time-division multiplex transfer of data, and particularly to a data transfer device used for transfer.

(Prior Art) FIG. 3 is a block diagram showing an example of a data transfer device according to the prior art. In figure M1, 301 is a data transmission timing generation circuit.

302 is a delay line circuit for creating switching timing of data to be multiplexed; 303-1 to 303-n are registers for holding data to be transmitted, respectively;
304-1 to 304-n are gate circuits for switching and multiplexing transmission data using the output of the delay-in circuit 302, 305-1 to 305-2 are output buffers, and 306-1 to 306-2 are gate circuits for multiplexing transmission data. 307 is a delay 2-in circuit for creating latch timing of received data.

308-1 to 308-n are respectively timing adjustment circuits for adjusting the best latch timing from the output of the delay 2-in circuit 307, and 309-1 to 309-n are each latching received data with the output of the timing adjustment circuit. A data latch circuit 310 is a data and timing signal transfer path.

FIG. 4 is an explanatory diagram showing the data transfer timing in FIG. 3. (a) shows the timing of the sending side, (
b) shows the timing on the receiving side. Furthermore, timing signals 1 to 5 represent the respective timings of signal lines 311 to 315 in FIG.

In the above configuration, data registers 303-1 to 303-1
The data held in 3-n is sent to gate circuit 304-1.
~304-n, output buffer 305-1. Launch circuits 309-1 to 309-3 through the receiving side manual buffer 306-1
09-nK-) is touched. At this time, on the transmitting side, the timing signal generation circuit 301 generates a timing signal such as the timing signal l shown in FIG. The output opens and closes gate circuits one after another. For this.

Data is time-division multiplexed.

The output of the timing signal generation circuit 301 along with the multiplexed data is directly sent to the receiving side buffers 305-2 and 306.
-2.

On the receiving side, a timing signal such as timing signal 3 in FIG. 4 (bl) sent from the transmitting side is delayed by a delay line circuit 307,
The output of No. 7 can only be set at predetermined time intervals.

Therefore, timing adjustment circuits 308-1 to 308-n
Then, a data latch timing signal such as timing signals 4 and 5 in FIG. 4(b) such that the time from data switching is t2 is created, and the data latch circuits 309-1 to 309-1.
Data is latched at 309-n.

(Problems to be Solved by the Invention) In the conventional configuration described above, the latch timing is determined by the timing adjustment circuit.

The drawback is that it is necessary to actually measure data transfer. Furthermore, since the timing signal is created on the receiving side, there is a drawback that if the environmental conditions change between the transmitting side and the receiving side, the timing adjustment circuit needs to be readjusted.

An object of the present invention is to eliminate the above drawbacks by determining the data latch timing on the receiving side from the transmitting side when data is multiplexed and communicated.

An object of the present invention is to provide a data transfer device configured so that there is no need to readjust timing.

(Means for Solving the Problems) A data transfer device according to the present invention includes a transmitting side, a timing signal line, and a receiving side, and the transmitting side includes a timing signal generation circuit, a shift register, and a multiplexer. On the other hand, the receiving side consists of an inverting circuit and a second shift register.

On the transmitting side, the timing signal generation circuit is for generating a data transfer timing signal synchronized with the clock, and the shift register has the number of bits equal to the multiplicity n of the data to be transferred, and clocks the output of the timing signal generation circuit. This is the ninth type that shifts data as input, and the multiplexer is for time-division multiplexing by switching the data to be transferred based on the output of the shift register.

On the other hand, on the receiving side, the 1 inverting circuit is used to invert the timing signal sent by the timing signal, and the second shift register is used on the sending side to shift data using the output of the inverting circuit as a clock input. They have the same n-bit configuration.

The timing signal line provided between the transmitting side and the receiving side is for sending the output of the timing signal generating circuit together with data to the destination inverting circuit.

(Actual flow side) Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data transfer device according to the present invention. In FIG. 1, 1 is a clock generation circuit, 2 is a timing signal generation circuit for generating a timing signal for data transfer synchronized with the clock output from the clock generation circuit 1, and 3 is an output of the timing signal generation circuit 2. Logic level l+ as clock input
An n-bit shift register for creating data switching timing by shifting the data of 1#l,
Data registers 5-1 to 5-n each hold transmission data.

4 Data registers 5-1 to 5-n that receive the output of the n-bit shift register 3 and hold transmission data
6-1 to 6-2 are output buffers, respectively, and 7-1 is a multiplexer circuit for switching and time-division multiplexing the outputs of .
~ 7-2 is a buffer circuit, 8 is an inverter circuit for inverting the timing signal sent by the timing signal line, and - 9 is an inverter circuit that uses the output of the inverter circuit 8 as a clock input to output data at logic level "'1". n-bit shift register +10-1 to 10 to create a data latch timing signal by shifting
-n is a data latch circuit for latching data that has passed through the buffer 7-1 as an output of each n-bit type shift register.

11 is a data signal line for transferring data.

12 is a timing signal line for transferring timing signals. Here, n is the multiplicity of data to be transferred.

FIG. 2 is an explanatory diagram showing data transfer timing.

In FIG. 2, (al indicates the timing on the transmitting side, and (b) indicates the timing on the receiving side. Timing signals 1 to 7 indicate the timings of signal lines 14 to 19 in FIG. 1, respectively, and the clocks in FIG. The timing of the signal line 20 is shown.

In the above configuration, the data held in the data registers 5-1 to 5-n is transferred to the multiplexer 4. Output buffer 6-1 (transmission I11), and input buffer 7-
1 (reception side) and is latched by latch circuits 1O-1 to 10-n. At this time, on the transmitting side, the clock generation circuit l
The timing signal generating circuit 2 generates a data transmission timing signal of one period tl and duty t2 (tl-12) in synchronization with the lock signal as shown in FIG. The input data f11'' is sequentially shifted by the n-bit type shift register 3 which uses l as the clock input. As shown in a), data is time-division multiplexed and transmitted to the receiving side.

The transmitting side transmits the timing signal l, which is the output of the timing signal generating circuit 2, to the receiving side.

On the receiving side, the timing signal 4t received through the buffer 6-2, 7-2 is inverted by the inverter circuit 8. Next, an n-bit shift register 9 which uses the timing signal 5, which is the output of the inverter circuit 8, as a clock input sequentially shifts the input data "l", as shown in FIG.
Data latch timing signals 6, 7t- are outputted.

The data latch circuits 1O-1 to 1°-n that received this,
The data passing through buffer 6-1.7-1 is shown in Figure 2 (
Latch as in b).

As described above, according to this embodiment, an n-bit shift register and a multiplexer are used on the transmitting side without using a delay-in circuit.

By using an inverter and an n-bit shift register on the receiving side, it is possible to create a data transfer device that does not require data latch timing adjustment on the receiving side.

(Effects of the Invention) As explained above, the present invention allows data latch timing on the receiving side to be easily determined from the transmitting side, which could not be determined without actual measurement, when multiplexing data and communicating. This method has the advantage that the best data latch timing can be determined without actual measurement. Furthermore, since the data latch timing can be determined only by the transmitting side, there is also the effect that there is no need to readjust the data latch timing even if the environmental conditions change between the transmitting side and the receiving side.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the data transfer device of the present invention. FIG. 2 is an explanatory diagram showing data transfer timing in the same embodiment. FIG. 3 is a block diagram showing an example of a data transfer device according to the prior art. FIG. 4 is an explanatory diagram showing data transfer timing according to the configuration of FIG. 3. 1... Clock generation circuit 2.301... Timing signal generation circuit 3.9...
Shift register 4...Multiplexer 5-1.5-2.5-n, 303-1, 303-2゜3
03-n...Data register 6-1.6-2, 305-1, 305-2...Output buffer 7-1.7-2, 306-1, 306-2...Input buffer 8... Inverter circuit 10-1.10-2.10-n, 309-1, 309-
2,309-n...Data latch circuit 11.12...
- Timing signal line 302.307 --- Delay 2-in circuit 304-1,
304-2, 304-n...gate circuit 308-1.
308-2, 308-n...timing adjustment circuit 310...transfer path

Claims (1)

[Claims] a timing signal generation circuit for generating a data transfer timing signal synchronized with a clock; and a shifter for shifting the data by using the output of the timing signal generation circuit as a clock input and having the number of bits equal to the multiplicity n of the data to be transferred. A transmitting side includes a register and a multiplexer for switching and time-division multiplexing the data to be transferred based on the output of the shift register, and also includes a timing signal line for sending the output of the timing signal generation circuit to the destination together with the data, Further, an inverting circuit for inverting the timing signal sent through the timing signal line, and a second n-bit shift register, which is the same as that on the transmitting side and using the output of the inverting circuit as a clock input, are provided on the receiving side. What is claimed is: 1. A data transfer device comprising: