JPH0350527A - Substrate for thin-film transistor array - Google Patents
Substrate for thin-film transistor arrayInfo
- Publication number
- JPH0350527A JPH0350527A JP1186720A JP18672089A JPH0350527A JP H0350527 A JPH0350527 A JP H0350527A JP 1186720 A JP1186720 A JP 1186720A JP 18672089 A JP18672089 A JP 18672089A JP H0350527 A JPH0350527 A JP H0350527A
- Authority
- JP
- Japan
- Prior art keywords
- film
- light
- insulating film
- light shielding
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は薄膜トランジスタアレイ基板に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a thin film transistor array substrate.
アクティブマトリクス液晶ディスプレイに用いられる薄
膜トランジスタアレイ基板は、ガラス等の透明基板の上
にアモルファスシリコン膜を動作層とした薄膜トランジ
スタのアレイを有して構成される.第2図は従来の薄膜
トランジスタアレイ基板の断面図である。ガラス基板1
上に設けたゲート電極4と、ゲート電極4を含む表面に
設けたゲート絶縁膜5と、ゲート絶縁膜5の上に設けた
アモルファスシリコン膜6と、アモルファスシリコン膜
6に接続して設けたドレイン電極8及びソース電極9に
より薄膜トランジスタが形成され、表示領域となる表示
電極7がトランジスタのソース電極9に接続されており
、表示電極7の電位をトランジスタで制御することによ
って表示を行なう。A thin film transistor array substrate used in an active matrix liquid crystal display is constructed by having an array of thin film transistors with an amorphous silicon film as an active layer on a transparent substrate such as glass. FIG. 2 is a cross-sectional view of a conventional thin film transistor array substrate. Glass substrate 1
A gate electrode 4 provided above, a gate insulating film 5 provided on the surface including the gate electrode 4, an amorphous silicon film 6 provided on the gate insulating film 5, and a drain provided connected to the amorphous silicon film 6. A thin film transistor is formed by the electrode 8 and the source electrode 9, and the display electrode 7 serving as a display area is connected to the source electrode 9 of the transistor, and display is performed by controlling the potential of the display electrode 7 with the transistor.
上述した従来の薄膜トランジスタアレイ基板は、ガラス
基板裏側から光が遮光されないため、薄膜トランジスタ
のオフ電流が光照射によって増大するという問題点があ
る。The conventional thin film transistor array substrate described above has a problem in that the off-state current of the thin film transistor increases due to light irradiation because light is not blocked from the back side of the glass substrate.
薄膜トランジスタの半導体層は、ゲート電極によって一
部が遮光されているが、ゲード電極とドレイン・ソース
電極の間の多重反射により半導体層が光照射をうけ、光
キャリアによるオフ電流が発生してしまうのである.
また、表示電極外から光が漏れるという問題点があり、
これは、通常、対向基板に設けられた金属パターンによ
って遮断され、透過光、すなわち表示光とはならない工
夫が施されるが、この場合2枚のガラス基板を精度よく
貼り合わせる必要があり、高精度,大型化の方向にとっ
て困難な内容となる。The semiconductor layer of a thin film transistor is partially shielded from light by the gate electrode, but due to multiple reflections between the gate electrode and the drain/source electrodes, the semiconductor layer is exposed to light and off-current due to photocarriers is generated. be. In addition, there is a problem that light leaks from outside the display electrode.
This is normally blocked by a metal pattern provided on the opposing substrate, and measures are taken to prevent it from becoming transmitted light, that is, display light, but in this case, it is necessary to bond two glass substrates together with high precision, and This will be difficult in terms of accuracy and size.
本発明の薄膜トランジスタアレイ基板は、透明基板上に
設けて表示電極形成領域に開孔部を設けた遮光膜と、前
記遮光膜を含む表面に設けた眉間絶縁膜と、前記遮光膜
上の前記層間絶縁膜上に設けた薄膜トランジスタと、前
記薄膜トランジスタと接続し且つ前記開孔部に整合して
前記層間絶縁膜上に設けた表示電極とを有する.
〔実施例〕
次に、本発明について図面を参照して説明する.
第1図(a),(b)は本発明の一実施例の平面図及び
A−A’線断面図である。The thin film transistor array substrate of the present invention includes a light shielding film provided on a transparent substrate and having an opening in a display electrode forming area, a glabella insulating film provided on a surface including the light shielding film, and an interlayer between the layers on the light shielding film. The device includes a thin film transistor provided on an insulating film, and a display electrode provided on the interlayer insulating film connected to the thin film transistor and aligned with the opening. [Example] Next, the present invention will be explained with reference to the drawings. FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of an embodiment of the present invention.
第1図(a).(b)に示すように、ガラス基板1の上
にスパッタ法によりC『膜を100nmの厚さに堆積し
、表示電極形成領域に相当する部分のCrliを選択的
にエッチングして開孔し、遮光膜2を形成する.次に、
遮光膜2を含む表面にCVD法により窒化シリコン膜を
400nmの厚さに堆積して眉間絶縁膜3を形成する.
次に、眉間絶縁WA3の上にC『膜を120nmの厚さ
に堆積して、これを選択的にエッチングし、遮光膜2の
上の眉間絶縁膜3の上にゲート電極4を形戒する。Figure 1(a). As shown in (b), a C film is deposited to a thickness of 100 nm on the glass substrate 1 by sputtering, and holes are formed by selectively etching the Crli in the portion corresponding to the display electrode forming area. Form a light shielding film 2. next,
A silicon nitride film is deposited to a thickness of 400 nm on the surface including the light shielding film 2 by the CVD method to form a glabellar insulating film 3.
Next, a C film is deposited to a thickness of 120 nm on the glabellar insulating film WA3, and this is selectively etched to form a gate electrode 4 on the glabellar insulating film 3 on the light shielding film 2. .
次に、ゲート電極4を含む表面に窒化シリコン膜を40
0nmの厚さに堆積してゲート絶縁膜5を形成する.次
に、ゲート電極4に対応するゲート絶縁膜5の上にアモ
ルファスシリコン膜6及びアモルファスシリコンの表面
に設けたn”型拡散層6aを選択的に形戒し、遮光膜2
の開孔部上のゲート絶縁M5の上に厚さ40nmのIT
O膜を選択的に設けて表示電極7を形成する.ここで、
表示電極7は遮光膜2の開孔部周縁と幅4μmの重複部
分を有するように形成される.次に、アモルファスシリ
コン膜6を含む表面にAI!膜を400nmの厚さに堆
積して選択的にエッチングし、ドレイン電極8及びソー
ス電f!9を形成す.る.次に、ソース・ドレイン電極
9,8をマスクとしてゲート電極4に対応する領域のn
+型拡散層6aを除去し、薄膜トランジスタアレイ基板
を構成する.ここで、遮光膜2は適当な電位に保たれる
が、アクティブマトリクス液晶ディスプレイにおいては
、遮光膜2を対向電極電位とすることにより、遮光膜2
と表示電極7の間で蓄積容量を形成することが有利であ
る.
〔発明の効果〕
以上説明したように、本発明は、透明基板上に設けた遮
光膜によって、表示電極形戒領域以外の薄膜トランジス
タ領域の遮光を行なうことにより、背面光照射によるト
ランジスタオフ電流の増大を抑制し、表示電極外からの
漏れ光を遮断するという効果を有する.
又、この遮光膜は薄膜トランジスタと同一の基板上にホ
トリソグラフィ技術によりパターニングされて形成され
るため、トランジスタ表示電極との相対位置を精度よく
制御できることが可能であり、高精度,大型化の点で有
利である.Next, a silicon nitride film is applied to the surface including the gate electrode 4 for 40 minutes.
A gate insulating film 5 is formed by depositing it to a thickness of 0 nm. Next, the amorphous silicon film 6 and the n'' type diffusion layer 6a provided on the surface of the amorphous silicon are selectively formed on the gate insulating film 5 corresponding to the gate electrode 4, and the light shielding film 2 is formed.
A 40 nm thick IT
Display electrodes 7 are formed by selectively providing an O film. here,
The display electrode 7 is formed so as to overlap the periphery of the opening of the light-shielding film 2 with a width of 4 μm. Next, AI! is applied to the surface including the amorphous silicon film 6. A film is deposited to a thickness of 400 nm and selectively etched to form the drain electrode 8 and the source electrode f! Form 9. Ru. Next, using the source/drain electrodes 9 and 8 as a mask, n of the region corresponding to the gate electrode 4 is
The + type diffusion layer 6a is removed to form a thin film transistor array substrate. Here, the light-shielding film 2 is kept at an appropriate potential, but in an active matrix liquid crystal display, the light-shielding film 2 is kept at a potential of a counter electrode.
It is advantageous to form a storage capacitor between the display electrode 7 and the display electrode 7. [Effects of the Invention] As explained above, the present invention can increase transistor off-current due to backlight irradiation by shielding thin film transistor regions other than the display electrode shape region from light using a light shielding film provided on a transparent substrate. This has the effect of suppressing light leakage from outside the display electrodes. In addition, since this light-shielding film is formed by patterning using photolithography technology on the same substrate as the thin-film transistor, it is possible to control the relative position with the transistor display electrode with high precision, making it possible to achieve high precision and increase size. It's advantageous.
第1図(a).(b)は本発明の一実施例の平面図及び
A−A’線断面図、第2図は従来の薄膜トランジスタア
レイ基板の断面図である。
1・・・ガラス基板、2・・・遮光膜、3・・・層間絶
縁膜、4・・・ゲート電極、5・・・ゲート絶縁膜、6
・・・アモルファスシリコン膜、6a・・・n+型拡散
層、7・・・表示電極、8・・・ドレイン電極、9・・
・ソース電極.Figure 1(a). (b) is a plan view and a sectional view taken along the line AA' of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional thin film transistor array substrate. DESCRIPTION OF SYMBOLS 1... Glass substrate, 2... Light shielding film, 3... Interlayer insulating film, 4... Gate electrode, 5... Gate insulating film, 6
...Amorphous silicon film, 6a...n+ type diffusion layer, 7...display electrode, 8...drain electrode, 9...
・Source electrode.
Claims (1)
遮光膜と、前記遮光膜を含む表面に設けた層間絶縁膜と
、前記遮光膜上の前記層間絶縁膜上に設けた薄膜トラン
ジスタと、前記薄膜トランジスタと接続し且つ前記開孔
部に整合して前記層間絶縁膜上に設けた表示電極とを有
することを特徴とする薄膜トランジスタアレイ基板。A light-shielding film provided on a transparent substrate and having an opening in a display electrode formation region, an interlayer insulating film provided on a surface including the light-shielding film, and a thin film transistor provided on the interlayer insulating film on the light-shielding film. A thin film transistor array substrate comprising: a display electrode connected to the thin film transistor and provided on the interlayer insulating film in alignment with the opening.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1186720A JPH0350527A (en) | 1989-07-18 | 1989-07-18 | Substrate for thin-film transistor array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1186720A JPH0350527A (en) | 1989-07-18 | 1989-07-18 | Substrate for thin-film transistor array |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0350527A true JPH0350527A (en) | 1991-03-05 |
Family
ID=16193458
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1186720A Pending JPH0350527A (en) | 1989-07-18 | 1989-07-18 | Substrate for thin-film transistor array |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0350527A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998016868A1 (en) * | 1996-10-16 | 1998-04-23 | Seiko Epson Corporation | Liquid crystal device substrate, liquid crystal device, and projection display |
JP2006003920A (en) * | 1997-10-31 | 2006-01-05 | Seiko Epson Corp | Liquid crystal device, electronic apparatus, and projection display device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60207116A (en) * | 1984-03-31 | 1985-10-18 | Toshiba Corp | Display electrode array |
-
1989
- 1989-07-18 JP JP1186720A patent/JPH0350527A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60207116A (en) * | 1984-03-31 | 1985-10-18 | Toshiba Corp | Display electrode array |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998016868A1 (en) * | 1996-10-16 | 1998-04-23 | Seiko Epson Corporation | Liquid crystal device substrate, liquid crystal device, and projection display |
US6297862B1 (en) | 1996-10-16 | 2001-10-02 | Seiko Epson Corporation | Light shielding structure of a substrate for a liquid crystal device, liquid crystal device and projection type display device |
US6388721B1 (en) | 1996-10-16 | 2002-05-14 | Seiko Epson Corporation | Light shielding structure of a substrate for a liquid crystal device, liquid crystal device and projection type display device |
US6573955B2 (en) | 1996-10-16 | 2003-06-03 | Seiko Epson Corporation | Capacitance substrate for a liquid crystal device and a projection type display device |
CN1294451C (en) * | 1996-10-16 | 2007-01-10 | 精工爱普生株式会社 | Base plate for liquid crystal apparatus, liquid crystal apparatus and projecting display device |
JP2006003920A (en) * | 1997-10-31 | 2006-01-05 | Seiko Epson Corp | Liquid crystal device, electronic apparatus, and projection display device |
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