JPH0340517A - Driving/protecting circuit for power device - Google Patents
Driving/protecting circuit for power deviceInfo
- Publication number
- JPH0340517A JPH0340517A JP17631889A JP17631889A JPH0340517A JP H0340517 A JPH0340517 A JP H0340517A JP 17631889 A JP17631889 A JP 17631889A JP 17631889 A JP17631889 A JP 17631889A JP H0340517 A JPH0340517 A JP H0340517A
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- circuit
- gate
- power device
- igbt
- short
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- 238000001514 detection method Methods 0.000 description 16
- 230000002159 abnormal effect Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電圧制御形パワーデバイスを出力素子として
用いるパワーICモジュール等のバフ−デバイス回路に
関し、特にそのパワーデバイスの駆動回路において過電
流及び短絡の保護機能を持つパワーデバイスの駆動・保
護回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buff device circuit such as a power IC module that uses a voltage-controlled power device as an output element, and particularly to a buff device circuit such as a power IC module that uses a voltage-controlled power device as an output element. This invention relates to a drive/protection circuit for power devices with a short-circuit protection function.
従来、パワーデバイス回路にかいて用いられている電圧
制御形パワーデバイスの駆動・過電流保護回路の一例を
第3図に示して説明する。第3図において、1はマイク
ロコンピュータ(以下マイコンと略称する)、2は駆動
(ドライバー)回路、3は電流検出内蔵の電圧制御形パ
ワーデバイスとしてのIGBTであシ、そのエミッタE
は接地され、フレフタCが誘導性負荷6に接続されてい
る。そして、このIGBT3を駆動する駆動回路2には
マイコン1よシ入力信号vrNが入力され、ゲート抵抗
4を介してIGBT3のゲートGに接続されている。噴
た駆動回路2はそのゲートGに逆バイアスを印加するた
め+VCCと−VXXの2電源が供給されている。また
、IGBT3のセンスSとエミッタEの間に接続された
センス抵抗5にょ1GBT3のコレクタ電流ICをモニ
ターし、その電圧と基準電圧源70基準電圧Vrefl
を比較器8で比較することによシ、過電流の検出を行な
い、過電流状態になると異常信号Vν0をマイコン1に
出力するものとなっている。An example of a drive/overcurrent protection circuit for a voltage controlled power device conventionally used in a power device circuit will be described with reference to FIG. In Fig. 3, 1 is a microcomputer (hereinafter abbreviated as microcomputer), 2 is a drive (driver) circuit, and 3 is an IGBT as a voltage-controlled power device with built-in current detection.
is grounded, and the flefter C is connected to the inductive load 6. The input signal vrN from the microcomputer 1 is input to a drive circuit 2 for driving this IGBT 3, and is connected to the gate G of the IGBT 3 via a gate resistor 4. In order to apply a reverse bias to the gate G of the drive circuit 2, two power supplies, +VCC and -VXX, are supplied. In addition, the sense resistor 5 connected between the sense S and the emitter E of the IGBT 3 monitors the collector current IC of the 1GBT 3, and the voltage and the reference voltage source 70 reference voltage Vrefl are monitored.
By comparing the values with the comparator 8, overcurrent is detected, and when an overcurrent condition occurs, an abnormality signal Vv0 is output to the microcomputer 1.
次に動作について第4TIAのタイミングチャートを参
照して説明する。なか、第4図にかいて太い矢印で示す
符号Iの部分は通常時の波形を示し、同じく符号■の部
分は過電流時の波形を、符号■の部分は短絡時の波形を
それぞれ示している。Next, the operation will be explained with reference to the timing chart of the fourth TIA. In Fig. 4, the part marked with symbol I indicated by a thick arrow indicates the waveform during normal operation, the part marked with symbol ■ indicates the waveform during overcurrent, and the part marked with symbol ■ indicates the waveform during short circuit. There is.
筐ず通常の状態(符号Iの部分)では、マイコン1より
の第4図(d)に示す入力信号VINに対応して、駆動
回路2の出力であるゲート印加電圧vGxは、−v■か
ら+VCCの電源レベルとなる(第4図(b))。In the normal state of the housing (the part marked with I), the gate applied voltage vGx, which is the output of the drive circuit 2, changes from -v■ in response to the input signal VIN shown in FIG. 4(d) from the microcomputer 1. The power level becomes +VCC (Fig. 4(b)).
このため、IGBT3はオン状態とib1コレクタ電流
Iaが流れる(第4図(耐)。そしてコレクタ電流Ic
が増加し、過電流検出レベルを越えた過電流状態(符号
■の部分)では、コレクタ電流Icが過電流検出レベル
21を越えると、比較器8からマイコン1に異常信号v
yoが出力される(第4図(C))。すると、マイコン
1はその異常信号に基づき処理を行々つた後、入力信号
VINを「H」レベルからrLJレベルとする(第4図
(d))。そのため、駆動回路2はその出力を−vnの
電源レベルとし、IGBT3のゲートGを逆バイアスす
ることによってIGBT3をオフとし、コレクタ電流I
cを遮断する。また、符号sHで示す短絡時に短絡電流
が流れた状態(符号■の部分)でも、その電流が過電流
検出レベル21を越えるため、過電流状態と同様の動作
によりコレクタ電流Icを遮断し、保護を行なうことが
できる。Therefore, IGBT3 is in the on state and ib1 collector current Ia flows (Fig. 4 (withstanding). And collector current Ic
increases and exceeds the overcurrent detection level (part marked with symbol ■), when the collector current Ic exceeds the overcurrent detection level 21, an abnormal signal v is sent from the comparator 8 to the microcomputer 1.
yo is output (FIG. 4(C)). Then, the microcomputer 1 performs processing based on the abnormal signal and then changes the input signal VIN from the "H" level to the rLJ level (FIG. 4(d)). Therefore, the drive circuit 2 sets its output to the power level of -vn, reverse biases the gate G of the IGBT 3 to turn off the IGBT 3, and collects the collector current I
Block c. In addition, even in the state where a short circuit current flows during a short circuit indicated by the symbol sH (the part marked with a symbol ■), the current exceeds the overcurrent detection level 21, so the collector current Ic is cut off by the same operation as in the overcurrent state, and protection is achieved. can be done.
しかし、従来の電圧制御形パワーデバイスの駆動・過電
流保護回路は、以上のように構成されているので、過電
流が発生し、パワーデバイスの保護のためにゲート印加
電圧を下げるためにマイコンによる信号処理が必要であ
った。筐た、マイコンのソフトウェアによるために計算
時間や異常信号のサンプリング時間が必要なため、入力
信号にフィードバックをかけるのに時間がかかる。この
ためパワーデバイスに短絡が生じた場合、フィードバッ
クがかかる1で、パワーデバイスが破壊し碌い短絡耐量
のあるデバイスを使用しなければ々らず・スイッチング
スピードp Wax(mat)等の特性を悪くした状態
で使用していた。また、パワーデバイスをブリッジ構成
に接続した場合、オフ状態のデバイスにdマ/dtが印
加されゲート電圧が上昇し、誤動作するのを防止するた
めに、オフ時にゲートを逆バイアスする必要がある。こ
のため、駆動回路を2電源で使用するか、あるいは1電
源で、逆バイアス用のダイオード回路やレギュレータ回
路を使用する必要があった。However, the drive and overcurrent protection circuits of conventional voltage-controlled power devices are configured as described above. Signal processing was required. Since the system uses microcomputer software, calculation time and sampling time for abnormal signals are required, so it takes time to apply feedback to the input signal. For this reason, if a short circuit occurs in the power device, the power device will be destroyed due to feedback 1, making it necessary to use a device with high short-circuit tolerance.・Characteristics such as switching speed p Wax (mat) will be adversely affected. It was used in the same condition. Furthermore, when a power device is connected in a bridge configuration, it is necessary to reverse bias the gate when the device is off in order to prevent dma/dt from being applied to the off-state device, causing the gate voltage to rise and malfunctioning. For this reason, it was necessary to use a drive circuit with two power supplies, or to use a reverse bias diode circuit or a regulator circuit with one power supply.
本発明は上記のような問題点を解消するためになされた
もので、IGETなどのパワーデバイスの短絡耐量に関
係なく、スイッチングスピードとVCI(sat)等の
特性の良い状態のデバイスを使用するための、過電流保
護・短絡保護回路を得るとともに、1電源で、逆バイア
スをし危いでdマ/dtによるゲート電圧の誤動作をし
ない駆動回路を得ることを目的とする。The present invention was made in order to solve the above problems, and it is possible to use devices with good characteristics such as switching speed and VCI (sat), regardless of the short circuit tolerance of power devices such as IGET. It is an object of the present invention to obtain an overcurrent protection/short circuit protection circuit, and also to obtain a drive circuit which uses a single power supply and does not cause malfunction of gate voltage due to dma/dt due to dangerous reverse bias.
本発明に係る電圧制御形パワーデバイスの駆動・過電流
及び短絡保護回路は、短絡が発生すると同時に、そのバ
ク−デバイスのゲート印加電圧を低下させてそのコレク
タ電流を低下させる動作を入力パルス毎に行なうととも
に、過電流保護は、過電流発生から誘導性負荷々どの場
合のフリーホイールダイオードのりカバリ−電流を考慮
し、あるデイレイ時間後に直接駆動回路の遮断を行なう
。The driving/overcurrent/short-circuit protection circuit for a voltage-controlled power device according to the present invention performs an operation for each input pulse to reduce the voltage applied to the gate of the back-device and the collector current at the same time that a short circuit occurs. At the same time, overcurrent protection takes into account the recovery current of the freewheeling diode in any case from overcurrent occurrence to inductive loads, and directly shuts off the drive circuit after a certain delay time.
筐た、その駆動回路のオフ時に、IGBT等のパワーデ
バイスのゲートとエミッタ間を低インピーダンスでショ
ートしたものである。When the drive circuit is turned off, the gate and emitter of a power device such as an IGBT are short-circuited with low impedance.
本発明に係る短絡保護回路は、短絡が発生すると同時に
ゲート印加電圧を低下させ、コレクタ電流を低下させる
ことができるので、IGBT等のパワーデバイスの短絡
耐量にあわせて短絡とする検出値を設定でき、スイッチ
ングタイムr V(J(sat)を最良にしたデバイス
を自由に使用できる。また過電流保護回路も、フリーホ
イールのりカバリ−電流分を除くためのデイレイ時間を
設けるだけで、直接駆動回路を遮断するため、高速動作
が可能となる。しかもマイコンによる信号処理は不要で
、異常信号による状態検出のマイコンは行なうだけとな
り1マイコンの負荷が軽くなる。また、IGBT等のバ
ク−デバイスのオフ時に、ゲートとエミッタ間を低イン
ピーダンスでシュートすることにより、dマ/atによ
るゲート誤動作を防止できるとともに、逆バイアス回路
が不要となう、1電源で、すべての駆動保護回路を動作
させることが可能となる。The short-circuit protection circuit according to the present invention can reduce the gate applied voltage and reduce the collector current at the same time a short circuit occurs, so it is possible to set a detection value for determining a short circuit according to the short-circuit tolerance of a power device such as an IGBT. , the device with the best switching time rV(J(sat)) can be used freely.In addition, the overcurrent protection circuit can be used simply by providing a delay time to remove the freewheel coverage current. This enables high-speed operation.In addition, there is no need for signal processing by the microcomputer, and the microcomputer only needs to detect the status based on the abnormal signal, reducing the load on one microcomputer.Also, when a back-up device such as an IGBT is turned off, By creating a low impedance shot between the gate and emitter, gate malfunctions due to d/at can be prevented, and a reverse bias circuit is not required, making it possible to operate all drive protection circuits with a single power supply. becomes.
以下、本発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図は本発明によるパワーデバイスの駆動・保護回路
の一実施例を示すブロック構成図である。FIG. 1 is a block diagram showing an embodiment of a power device drive/protection circuit according to the present invention.
第1図において、マイコン1よりの入力信号vI)1は
、パルス0バイ・パルス形のラッチ回路10を経て駆動
回路2εタ一ンオフ回路11に入力されると共に、駆動
回路2からゲート抵抗4を介してIGBT3のゲートG
に接続される。そして入力信号のオフ時には、ターンオ
フ回路11により IGBT3のゲートGを低インピー
ダンスでグランド(IGBT3のエミッタ電位)にショ
ートするように接続されている。また、IGBT3のセ
ンスSεエミッタEの間に接続されたセンス抵抗5によ
り11GBT3のコレクタ電流Icをモニターし、短絡
検出は基準電圧源12の基準電圧vranと・過電流検
出は基準電圧源Tの基準電圧V、。fl (<Vraf
z)と電圧比較をそれぞれ比較器13.比較器8で行な
う。さらに、短絡保護用の比較器13の出力は、入力信
号vINが入力されるパルス・バイ・パルス形ラッチ回
路14に入力され、短絡が発生するとその入力信号のオ
ン状態中、駆動回路2の出力電圧をゲート抵抗4と4亀
で抵抗分割して、TGBT3のゲートに印加するように
接続されている。筐た、過電流保護用の比較器8の出力
は、誘導性負荷6側のフリーホイールダイオード(図示
せず)によるリカバリー電流分を除くべく予め決められ
たデイレイ時間tdのデイレイ回路9を介して、マイコ
ン1に異常信号を出力するとともに、駆動回路2の出力
を遮断するためパルス・バイ・パルス形スイッチ回路1
0に入力されている。&Th、図中同一符号は同一また
は和蟲部分を示している。In FIG. 1, an input signal vI)1 from a microcomputer 1 is input to a drive circuit 2ε turn-off circuit 11 via a pulse 0-by-pulse type latch circuit 10, and is also input from the drive circuit 2 to a gate resistor 4. Gate G of IGBT3 via
connected to. When the input signal is off, the turn-off circuit 11 connects the gate G of the IGBT 3 to the ground (emitter potential of the IGBT 3) with low impedance. In addition, the collector current Ic of the 11GBT3 is monitored by the sense resistor 5 connected between the sense Sε emitter E of the IGBT3, and the short circuit detection is based on the reference voltage vran of the reference voltage source 12.The overcurrent detection is based on the reference voltage source T. Voltage V. fl (<Vraf
comparator 13.z) and voltage comparison respectively. This is done using comparator 8. Further, the output of the comparator 13 for short circuit protection is input to a pulse-by-pulse type latch circuit 14 to which the input signal vIN is input, and when a short circuit occurs, the output of the drive circuit 2 is output while the input signal is on. The voltage is resistance-divided by the gate resistors 4 and 4 and is connected to be applied to the gate of the TGBT 3. The output of the overcurrent protection comparator 8 is passed through a delay circuit 9 with a predetermined delay time td to remove the recovery current due to a freewheeling diode (not shown) on the inductive load 6 side. , a pulse-by-pulse type switch circuit 1 to output an abnormal signal to the microcomputer 1 and cut off the output of the drive circuit 2.
It is entered as 0. &Th, the same reference numerals in the figures indicate the same or Japanese parts.
次に上記実施例構成の動作について、第2図のタイミン
グチャートを参照して説明する。1ず通常の動作(符号
Iの部分)では、マイコン1よりの第2図(d)に示す
入力信号vINに対応して、駆動回路2の出力であるゲ
ート印加電圧VGIが+v0゜の電源レベルになシ(第
2図(b))、IGBT3はオンしてコレクタ電流Ic
が流れる(第2図(&))。Next, the operation of the configuration of the above embodiment will be explained with reference to the timing chart of FIG. 1. In normal operation (portion I), in response to the input signal vIN from the microcomputer 1 shown in FIG. (Fig. 2(b)), IGBT3 is turned on and the collector current Ic
flows (Fig. 2 (&)).
そしてコレクタ電流Icが増加して過電流検出レベル2
1をこえると(符号■の部分)、過電流保護回路を構成
する比較器8の出力信号は、そのデイレイ回路9のデイ
レイ時間tdだけ遅れて、ラッチ回路10を経て駆動回
路2を遮断し、その出力のゲート印加電圧VGIを「0
」■とし、同時に異常信号VFOをマイコン1に出力す
る。そのため、マイコン1は異常信号の発生を検知する
だけでよく、入力信号がrLJレベルになると、パルス
・バイ・パルス形ラッチ回路10によシ自動的に異常状
態のラッチはリセットされる。Then, collector current Ic increases and overcurrent detection level 2
When the value exceeds 1 (the part marked with symbol ■), the output signal of the comparator 8 constituting the overcurrent protection circuit is delayed by the delay time td of the delay circuit 9, passes through the latch circuit 10, and shuts off the drive circuit 2. The gate applied voltage VGI of the output is set to “0”.
"■, and at the same time outputs an abnormality signal VFO to the microcomputer 1. Therefore, the microcomputer 1 only needs to detect the occurrence of an abnormal signal, and when the input signal reaches the rLJ level, the pulse-by-pulse type latch circuit 10 automatically resets the latch in the abnormal state.
また、符号SHで示す短絡時に短絡電流が流れた場合(
符号■の部分)は、そのコレクタ電流Icが短絡検出レ
ベル22を越えると同時に、短絡保護回路を構成する比
較器13の出力がパルス・バイ・パルス形ラッチ回路1
4に入力される。これにより1ゲート印加電圧VCCが
VCC電源レベルからゲート抵抗4及び4aの抵抗分割
によシ低下しく第2図(b))、そのラッチ回路14に
よって入力信号がrHJレベルの間はラッチする。そし
て上記短絡保護回路が働き、コレクタ電流ICは減少す
るが、この時の電流値を過電流検出レベル21以上とす
ると、上記過電流状態と同様にrtctJの時間遅れの
後、IGBT3のゲートを遮断し、異常信号を出力する
(第2図(C))。In addition, if a short circuit current flows during a short circuit indicated by the symbol SH (
The part marked with symbol ■) indicates that at the same time the collector current Ic exceeds the short-circuit detection level 22, the output of the comparator 13 constituting the short-circuit protection circuit reaches the pulse-by-pulse type latch circuit 1.
4 is input. As a result, one gate applied voltage VCC is lowered from the VCC power supply level by the resistance division of the gate resistors 4 and 4a (FIG. 2(b)), and the input signal is latched by the latch circuit 14 while the input signal is at the rHJ level. Then, the short-circuit protection circuit operates and the collector current IC decreases, but if the current value at this time is equal to or higher than the overcurrent detection level 21, the gate of IGBT3 is cut off after the rtctJ time delay as in the overcurrent state. and outputs an abnormal signal (Fig. 2(C)).
また、駆動回路2とターンオフ回路11のタイミングは
、その駆動回路2の出力がrLJレベルからrl(Jレ
ベルとなる直前に、ターンオフ回路11はIGBT3の
ゲート・エミッタ間を高インピーダンスにし、「H」レ
ベルからrLJレベルにZつた直後に、ゲート・エミッ
タ間を低インビーダンスにする。これによ、り、IGB
T3がオフ状態では、ターンオフ回路11によ、9IG
BT3のゲート・エミッタが低インピーダンスにショー
トされる。そのため、IGBTをブリッジ構成とした場
合に発生するdマ/dtに伴iうゲート電圧変動による
誤動作を防止することができる。Furthermore, the timing of the drive circuit 2 and the turn-off circuit 11 is such that just before the output of the drive circuit 2 changes from the rLJ level to the rL (J level), the turn-off circuit 11 sets a high impedance between the gate and emitter of the IGBT 3 to "H". Immediately after going from the level to the rLJ level, the impedance between the gate and emitter is made low.As a result, the IGB
When T3 is off, the turn-off circuit 11 causes 9IG
The gate and emitter of BT3 are shorted to low impedance. Therefore, it is possible to prevent malfunctions due to gate voltage fluctuations caused by dma/dt that occur when the IGBT is configured in a bridge configuration.
なか、上記実施例では、パワーデバイスとして電流検出
内蔵IGBTについて述べたが、電圧制御形のパワーデ
バイスであれば、MOSFET等であってもよく、また
電流検出内蔵のデバイスでなくても、他の方法によりコ
レクタ電流をモニターし、電源を電圧に変換するセンサ
を用いれば、上記実施例と同様の効果を奏する。In the above embodiment, an IGBT with built-in current detection was described as a power device, but any voltage-controlled power device may be used, such as a MOSFET.Also, even if it is not a device with built-in current detection, other By using a sensor that monitors the collector current and converts the power into voltage, the same effects as in the above embodiment can be achieved.
また、短絡保護回路が動作した時、上記実施例ではコレ
クタ電流が過電流検出レベル以上である場合について述
べたが、コレクタ電流が過電流検出レベル以下になつ見
場台ご、短絡保護回路出力(パルス・バイ・パルス形ラ
ッチ回路14の出力)を過電流検出用基準電圧源7にフ
ィードバックし、短絡が発生した場合の過電流検出レベ
ルを下げれば上記実施例と同様の効果を奏する。In addition, when the short-circuit protection circuit operates, the above embodiment describes the case where the collector current is above the overcurrent detection level, but when the collector current is below the overcurrent detection level, the short-circuit protection circuit output ( If the output of the pulse-by-pulse latch circuit 14) is fed back to the overcurrent detection reference voltage source 7 and the overcurrent detection level is lowered when a short circuit occurs, the same effect as in the above embodiment can be achieved.
以上のように本発明によれば、駆動回路においてパワー
デバイスのオフ状態時にゲート・エミッタを低インピー
ダンスにしたことにより、逆バイアスが不要になり11
電源化を実現できるとともに、短絡保護回路と過電流保
護回路の組合せにより1パワーデバイスの短絡耐量を考
慮することなしに使用できる。また、マイコン等の外部
フィードバックを必要とせずに保護を行なうので、高速
動作が可能と々シ、安価な回路が得られる効果がある。As described above, according to the present invention, by making the gate and emitter of the drive circuit low impedance when the power device is in the off state, reverse bias is not required.
In addition to realizing a power supply, the combination of a short-circuit protection circuit and an overcurrent protection circuit allows use without considering the short-circuit tolerance of a single power device. Furthermore, since protection is performed without requiring external feedback from a microcomputer, high-speed operation is possible, and an inexpensive circuit can be obtained.
第1図は本発明の一実施例によるパワーデバイスの駆動
・保護回路のブロック構成図、第2図はその実施例の動
作説明に供するタイミングチャート、第3図は従来例に
よる駆動・過電流保護回路のブロック構成図、第4図は
そのタイミングチャートである。
2・O・◆駆動回路、3・・・・IGBT、 4 。
4& ・・−・ゲート抵抗、5・・・・センス抵抗、6
・・・・誘導性負荷、T、12・・・・基準電圧源、8
・・・・過電流保護用比較器、9−・・・デイレイ回路
、10,14・・・・ラッチ回路、11・・−・ターン
オフ回路、13・−・・短絡保護用比較器。Fig. 1 is a block configuration diagram of a power device drive/protection circuit according to an embodiment of the present invention, Fig. 2 is a timing chart for explaining the operation of the embodiment, and Fig. 3 is a drive/overcurrent protection circuit according to a conventional example. The block diagram of the circuit and FIG. 4 is its timing chart. 2.O.◆Drive circuit, 3...IGBT, 4. 4 & --- Gate resistance, 5 --- Sense resistor, 6
...Inductive load, T, 12...Reference voltage source, 8
... Comparator for overcurrent protection, 9--Delay circuit, 10, 14... Latch circuit, 11... Turn-off circuit, 13-- Comparator for short-circuit protection.
Claims (1)
ワーデバイスがオフ時にそのデバイスのゲートとエミッ
タ間を低インピーダンスとするターンオフ回路と、上記
パワーデバイスの電流センサよりの信号を第1の基準電
圧と比較し、その出力を遅延回路を通して上記駆動回路
に帰還する過電流保護回路と、上記電流センサよりの信
号を第2の基準電圧と比較し、その出力により上記駆動
回路の出力を低下させて上記パワーデバイスのゲートに
印加する短絡保護回路を備えたことを特徴とするパワー
デバイスの駆動・保護回路。In a drive circuit for a voltage-controlled power device, a turn-off circuit provides low impedance between the gate and emitter of the power device when the power device is off, and a signal from a current sensor of the power device is compared with a first reference voltage. , an overcurrent protection circuit whose output is fed back to the drive circuit through a delay circuit, and a signal from the current sensor is compared with a second reference voltage, and the output of the current sensor is used to reduce the output of the drive circuit, and the power device is activated. A drive/protection circuit for a power device, characterized in that it is equipped with a short-circuit protection circuit that applies voltage to the gate of the power device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1176318A JP2643459B2 (en) | 1989-07-06 | 1989-07-06 | Power device drive / protection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1176318A JP2643459B2 (en) | 1989-07-06 | 1989-07-06 | Power device drive / protection circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0340517A true JPH0340517A (en) | 1991-02-21 |
JP2643459B2 JP2643459B2 (en) | 1997-08-20 |
Family
ID=16011490
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1176318A Expired - Lifetime JP2643459B2 (en) | 1989-07-06 | 1989-07-06 | Power device drive / protection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2643459B2 (en) |
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JP2006333459A (en) * | 2005-05-23 | 2006-12-07 | Semikron Elektronik Gmbh & Co Kg | A circuit device for driving a power semiconductor switch with a fault recognition function and a method attached thereto. |
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JPS63296410A (en) * | 1987-05-27 | 1988-12-02 | Nec Ic Microcomput Syst Ltd | Drive circuit |
JPS6426250A (en) * | 1987-07-22 | 1989-01-27 | Canon Kk | Memory readout circuit for cpu |
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