JPH033986B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for recording and reproducing television signals.
It relates to a method for recording and reproducing data signals such as address signals used for cueing.

Conventionally, in video discs and the like, an address signal has been recorded superimposed on the blanking portion of the vertical synchronization signal of the video signal in order to locate the beginning of the information track, and this allows the search for the desired information track. It is. With this conventional method, the timing at which the address signal can be read is 1/60
Once per second, to shorten the search time,
When a pickup for reproducing information signals scans a group of information tracks at high speed, it takes time to search because address signals cannot be read out frequently enough. Also, the amount of data in the address signal was small.

The present invention was proposed in view of this point, and consists of converting the synchronization signal portion of a television signal into a digital signal (referred to as a SYNC word) with a certain pattern.
and a data signal such as an address signal indicating the address of the video signal, which is encoded and recorded using an appropriate method, thereby providing a large number of locations where address signals can be recorded, allowing for high-speed retrieval, and This increases the amount of data that can be used.

Hereinafter, one embodiment of the present invention will be described.

In FIG. 1, a chroma signal in a video signal to be recorded at terminal A is taken out, balanced modulated with the output of an oscillator 3 by a balanced modulator 2, and a frequency-converted chroma signal is obtained at the output of a low-pass filter 4. .
A low-pass filter 6 separates the luminance signal in the video signal, and a frequency modulator 7 modulates it into an FM signal.

A pulse generator 8 separates a synchronizing signal from the input video signal and supplies the synchronizing signal to a timing signal generating circuit 9. 10 is a read-only memory that supplies data to the timing signal generator 9, controls the random access memory circuit 11, and outputs NYNC to the synchronization signal portion of the video signal as the output of the random access memory circuit 11.
Word and address signals are generated.

Reference numeral 12 denotes an encoding circuit which encodes the output of the random access memory circuit 11 using an encoding method suitable for the recording medium, and supplies the encoded output to the switch _S1 . Here, the clock signal of the encoded output of the encoder circuit 12 is
It is also possible to maintain a synchronous relationship with the third oscillator. The switch _S1 is an electronic switch controlled by the timing signal generator 9, and operates so that the output of the frequency modulator 7 and the output of the encoding circuit 12 are sequentially input to the signal adder 5 as shown in FIG. do. That is, in FIG. 2, A is the luminance signal which is the output of the low-pass filter 4, which is frequency modulated by the frequency modulator 7 and converted into the signal shown in B. on the other hand,
The encoded output of the encoding circuit 12 is shown by C, and is combined with the frequency modulated signal B by the switch _S1 as shown by D and input to the signal adder 5. Then, it is added to the frequency-converted chroma signal by an adder 5 and recorded on a suitable recording medium.

Next, the format of the digital signal recorded in the synchronization signal portion will be explained.

The horizontal synchronization signal period is about 4μsec, and now SYNC
If 12 bits are input as a word and 20 bits are input as an address signal (Fig. 2 (e)), the time will be 4 μsec/(12+20) = 0.125 μsec/bit, which is a value sufficient for recording and reproducing.

Also, by using a 20-bit address signal, it is possible to assign addresses to 79,999 information tracks one by one.

When recording in the form of pits on an optical disc, a limiter circuit can be provided after the signal adder 5, and the chroma signal output from the low-pass filter 4 can be recorded as duty cycle modulation.

Next, the reproduction method will be described.

FIG. 3 is a block diagram showing one embodiment of the reproducing circuit.

A signal almost the same as the recording signal 2 explained in FIG. 2 is reproduced from the recording medium and inputted to the terminal A.
The bandpass filter 30 passes the low frequency converted chroma signal and inputs it to the balanced modulator 31. The chroma burst signal being output from the balanced modulator 31 is extracted by the burst sampling circuit 32, inputted to the phase comparator 33, and then input to the reference signal generator 34 (3.58M
Hz), and this phase comparator 33
The output passes through a low-pass filter 35 and then goes to 36 VCOs.
(voltage controlled oscillator), and its output is input to the balanced modulator 31, forming a so-called APC loop.

The FM demodulation circuit 37 is supplied with the frequency-modulated luminance signal component, except for the chroma signal component that has been low-frequency converted by the high-pass filter 29.
7, a luminance signal that does not include a synchronization signal is obtained.

A comparator 40 slices the encoded digital signal portion and inputs it to a clock signal generator 41 together with the output of the VCO 36.
A clock signal generator 41 generates a stable clock signal from the output of the VCO 36 and the clock signal of the encoded digital signal portion extracted from the output of the comparator 40.

42 is a decoder which uses the output of the comparator 40 and the clock signal of the clock signal generator 41 to
This is for decoding, and an NRZ signal is obtained as an output and sent to the shift register 43. The shift register 43 converts the serial output signal of the decoder 42 into a parallel signal, which is compared with a predetermined SYNC word output from the SYNC word generator 45 in a data comparator 44, and when they match, generates a pulse signal.

Therefore, the output of the data comparator 44 becomes a pulse indicating the synchronization signal of the video signal. Note that the shift register 43 transmits the address signal reproduced after the SYNC word to another control circuit (not shown) as an address signal output of the terminal C.

Note that 46 is a control circuit that controls the timing of the shift register 43 and the SYNC word generator 45.

In addition, 46 is a control circuit, and the synchronization signal pulse which is the output of the timing comparator 44 of the shift register 43 and the SYNC word generator 45 is
The signal is input to the SYNC word generator 47, which generates a synchronization signal for the video signal, and input to the synchronization signal addition circuit 38.
9, the output of the balanced modulator 31 is passed through the bandpass filter 28.
The output signal is added to the chroma signal shaped by , and is supplied to terminal B as a television signal output.

By configuring as above, the address signal can be recorded in the horizontal synchronization signal section,
Using this address signal, frame searches of video signals can be performed at very high speed.

Furthermore, in the case of an NTSC television signal, there are 525 horizontal synchronization signals in one frame, so 525 x 20 bits = 10,500 bits of data can be recorded in one frame. Therefore,
Of course, it is also possible to input not only the address signal but also other information signals, such as character information signals. It is something that can be distinguished.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a recording system of one embodiment of the television signal recording and reproducing system of the present invention, and FIG.
The figure is a waveform diagram of the same operation, and FIG. 3 is a block diagram showing the reproduction system. 1...Band filter, 2...Balanced modulator, 3
...Oscillator, 4,6...Low pass filter, 5...
Adder, 7... Frequency modulator, 8... Pulse generator, 9... Timing signal generation circuit, 10... Read only memory, 11... Random access memory circuit.

Claims (1)

[Scope of Claims] 1. Converting at least a synchronization signal portion of a television signal into a digital signal with a certain pattern, and converting a data signal related to the television signal into a digital signal with the certain pattern. arranged together, the digital signal part is encoded, the television signal other than the synchronization signal is frequency modulated, and both are recorded on a recording medium;
A recording and reproducing method for television signals characterized by reproduction. 2 Data signals related to television signals are:
Claim 1, characterized in that the address signal indicates a frame number of a television signal.
The recording and reproducing method for television signals described in . 3. A recording and reproducing system for a television signal according to claim 1, characterized in that the subcarrier of the chroma signal included in the television signal is set to have a synchronous relationship with the clock signal of the encoded digital signal. . 4 The chroma signal included in the television signal is
Claim 1, characterized in that the encoded digital signal is frequency-converted by a signal having a synchronous relationship with a clock signal and recorded on a recording medium.
The recording and reproducing method for television signals described in .