JPH0338917A - Inverter circuit - Google Patents

Abstract

PURPOSE:To suppress sudden turning on/off of a transistor(TR) while a switch is in a transient state and to reduce the generation of noise by inserting a back gate control TR between a back gate and a power terminal of a P-channel TR and an N-channel TR to shift the back gate voltage from a reference voltage. CONSTITUTION:The drain and the source of a 2nd P-channel TR QP2 and N- channel TR QN2 for back gate control are inserted respectively between a back gate terminal BGP and a power terminal TD of a 1st P-channel TR QP1 and between a back gate terminal BGN, and a power terminal TS of a 1st N-channel TR QN1 in an inverter circuit of a CMOS IC. Then a back gate power supply 1 connecting each gate to a common gate G is added. Then the 1st TRs QP1 and QN1 are not suddenly turned on at the transient time of rise and fall, the waveform of an output voltage VD is relaxed and no noise is generated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an inverter circuit.

[Conventional technology]

Conventionally, in a CMO3 type O3 inverter circuit, a pair of P-type transistors and N-type transistors having a common gate G are connected in series between the drain power supply terminal To of the drain voltage ■DD and the source power supply terminal Ts of the source voltage V9S. It had been.

The back gates of P type and N type transistors are
It was connected to each drain and source and biased to drain voltage VDD and source voltage VSS.

[Problem to be solved by the invention]

The conventional inverter circuit described above has a CMO3 type O3 P
The back gates of type transistors and N type transistors are directly connected to their respective drains and sources, and the rise and fall of the output voltage waveforms are steep, so when the circuit operates at a high frequency, noise etc. This has the drawback of causing a malfunction in the logic circuit at the next stage.

An object of the present invention is to provide an inverter circuit that generates less noise.

[Means to solve the problem]

The inverter circuit of the present invention is a CMO3 type O3 in which a first P type transistor and a first N type transistor whose common gate is connected to an input terminal are connected in series between a drain power supply terminal and a source power supply terminal. In the inverter circuit, a back gate of the first P type transistor is connected to a source of a second P (N) type transistor, and a back gate of the first N type transistor is connected to a source of a second N (P) type transistor. A drain of the transistor and a common gate of the second P and N type transistors are connected to the input terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The inverter circuit includes a first P type transistor Qp+ and a first N type transistor of a conventional CMO3 type O3 inverter circuit.
A second P-type transistor Q for back gate control is provided between the back gate and the power supply terminal of the type transistor QP2 between BG p -T o and between BGs and Ts, respectively.
It is constructed by inserting the drains and sources of P2 and N type transistors QN2, and adding a back gate power supply 1 that connects their gates to a common gate G.

FIG. 2 is an output voltage waveform diagram for explaining the operation of the circuit shown in FIG. 1.

Back gate voltage vn of transistor Qp+ and QNI
P and VBN are shifted from their respective power supply voltages VDD and VB2 by the diode voltage VF of the second transistor when the first transistor turns on.

Therefore, during rising and falling transients, the first transistors QPI and QO do not turn on abruptly, and the broken line A
The output voltage V as shown in . Compared to the conventional waveform shown by the solid line B, the waveform is gentler at the transient time points t1 to t4 and does not generate noise. Furthermore, since there is no change in switching ability, there is no effect of delay time or the like.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

Back gate power supply of this embodiment 1. are the second transistors QP2 . for back gate control of the back gate power supply 1 in FIG. The top and bottom of QN2 are swapped and combined with the first transistor.

In this case as well, the same effects as in the first embodiment can be obtained.

〔Effect of the invention〕

As explained above, the present invention inserts a backgate control transistor between the backgates and power supply terminals of each of the P type transistor and N type transistor of a CMO3 type O3 inverter circuit to adjust the backgate voltage from the reference potential. By shifting, the abrupt on/off of the transistor during switching transients can be suppressed, and the rise and fall of the output waveform can be smoothed, which has the effect of reducing noise generation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
FIG. 3 is an output voltage waveform diagram for explaining the operation of the circuit shown in the figure, and FIG. 3 is a circuit diagram of a second embodiment of the present invention. 1.1.・・・Back gate power supply, BGN BGp・
...Back gate, G...Common gate, QNI, QN
2... 1st. Second N-type transistor, QPII
QP2... 1st. Second P-type transistor, VB
N, Vap...back gate voltage, Vo...gate voltage, v(....output voltage 6

Claims (1)

[Claims] A CMOS in which a first P type transistor and a first N type transistor whose common gate is connected to an input terminal are connected in series between a drain power supply terminal and a source power supply terminal.
In the inverter circuit of type IC, the back gate of the first P type transistor is connected to the source of the second P(N) type transistor, and the back gate of the first N type transistor is connected to the second N( An inverter circuit characterized in that a drain of a P) type transistor and a common gate of the second P and N type transistors are connected to the input terminal.