JPH0334326A - Semiconductor wafer - Google Patents
Semiconductor waferInfo
- Publication number
- JPH0334326A JPH0334326A JP1169460A JP16946089A JPH0334326A JP H0334326 A JPH0334326 A JP H0334326A JP 1169460 A JP1169460 A JP 1169460A JP 16946089 A JP16946089 A JP 16946089A JP H0334326 A JPH0334326 A JP H0334326A
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial
- yield
- high concentration
- silicon substrate
- particles
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 235000012431 wafers Nutrition 0.000 claims description 24
- 238000009792 diffusion process Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 8
- 239000002245 particle Substances 0.000 abstract description 8
- 238000005247 gettering Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229910001385 heavy metal Inorganic materials 0.000 abstract description 5
- 230000007423 decrease Effects 0.000 abstract description 4
- 239000007789 gas Substances 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000005049 silicon tetrachloride Substances 0.000 abstract description 4
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 abstract description 3
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 2
- 125000004429 atom Chemical group 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 238000005137 deposition process Methods 0.000 abstract 1
- 239000001257 hydrogen Substances 0.000 abstract 1
- -1 hydrogen silicon tetrachloride Chemical class 0.000 abstract 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000005488 sandblasting Methods 0.000 description 4
- 230000005260 alpha ray Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000013074 reference sample Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000011856 silicon-based particle Substances 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体ウェーハに関し、特に半導体基板上に
エピタキシャル膜を形成した半導体ウェーハに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor wafer, and particularly to a semiconductor wafer having an epitaxial film formed on a semiconductor substrate.
第2図は従来の半導体ウェーへの一例の断面図である。 FIG. 2 is a cross-sectional view of an example of a conventional semiconductor wafer.
不純物として硼素を高濃度に添加したP型シリコン基板
上の上にエピタキシャル膜3を形成して半導体膜置製造
用ウェーハを作成する。An epitaxial film 3 is formed on a P-type silicon substrate doped with boron as an impurity at a high concentration to create a wafer for manufacturing a semiconductor film device.
このような半導体ウェーハが素子間のラッチアップやα
線ソフトエラーの防止に対して有効であることから、高
集積記憶回路素子、高集積論理回路素子や超高速記憶回
路素子などに利用されている。このとき、ラッチアップ
防止やα線ンフトエラ一対策には、P型シリコン基板は
できるだけ硼素を高濃度に含んで低抵抗であることが有
効である。このシリコン基板上に形成するエピタキシャ
ル膜3は、デバイスの形成領域となるため、実用上シリ
コン基板よりも2桁はど高い抵抗率を有する。Such semiconductor wafers are prone to latch-up between elements and α
Since it is effective in preventing line soft errors, it is used in highly integrated memory circuit elements, highly integrated logic circuit elements, ultra-high speed memory circuit elements, and the like. At this time, in order to prevent latch-up and α-ray radiation error, it is effective for the P-type silicon substrate to contain as high a concentration of boron as possible and to have a low resistance. The epitaxial film 3 formed on this silicon substrate serves as a device formation region, and therefore has a resistivity that is two orders of magnitude higher than that of the silicon substrate in practice.
しかし、硼素を含んだシリコン基板の格子定数が硼素濃
度の増加とともに縮小し、低抵抗化するとエピタキシャ
ル膜との格子定数の差が大きくなり、ウェーハの大きな
反りやミスフィツト転位が発生する。このため、従来の
この種のエピタキシャルウェーハを用いた半導体デバイ
スはこのウェ−ハの反りやミスフィツト転位の発生を防
止しようとして、硼素濃度の含有量を抑えたエピタキシ
ャルウェーハを用いた。However, the lattice constant of a silicon substrate containing boron decreases as the boron concentration increases, and as the resistance decreases, the difference in lattice constant from that of the epitaxial film increases, causing large warpage of the wafer and misfit dislocations. For this reason, conventional semiconductor devices using epitaxial wafers of this type use epitaxial wafers with a reduced boron concentration in an attempt to prevent warping of the wafers and occurrence of misfit dislocations.
また、このようなエピタキシャルウェーハは裏面にサン
ドブラストによって損傷を与えて重金属のゲッタリング
を行っている。このゲッタリング法はサンドブラストに
よってウェーハ裏面が破砕されるためデバイス形成工程
中に裏面よりシリコンのパーティクルが発生する。In addition, the back surface of such epitaxial wafers is damaged by sandblasting to getter the heavy metals. In this gettering method, the back surface of the wafer is crushed by sandblasting, so silicon particles are generated from the back surface during the device forming process.
上述した従来のシリコンエピタキシャルウェーハを用い
た半導体デバイスは、ラッチアップやα線ソフトエラー
の防止のためP型シリコン基板を低抵抗化するとミスフ
ィツト転位が発生し、これがデバイス不良原因となる欠
点がある。Semiconductor devices using conventional silicon epitaxial wafers as described above have the disadvantage that misfit dislocations occur when the resistance of the P-type silicon substrate is lowered to prevent latch-up and α-ray soft errors, and this causes device failure.
さらに、従来、エピタキシャルウェーハに用いられてき
たサンドブラストによるゲッタリング法は、デバイス形
成工程中にパーティクルが発生するためこれらがデバイ
ス不良原因となる。Furthermore, in the sandblasting gettering method conventionally used for epitaxial wafers, particles are generated during the device formation process, which causes device failure.
本発明の半導体ウェーハは、高濃度不純物拡散領域が選
択的に形成された半導体基板と、該半導体基板上にエピ
タキシャル形成され前記高濃度不純物拡散領域上にミス
フィツト転位発生領域が形成された半導体膜とを有する
ことを特徴とする。A semiconductor wafer of the present invention includes a semiconductor substrate in which a high concentration impurity diffusion region is selectively formed, and a semiconductor film epitaxially formed on the semiconductor substrate and in which a misfit dislocation generation region is formed on the high concentration impurity diffusion region. It is characterized by having the following.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)、(b)は本発明の一実施例の製造方法を
説明するための工程順に示した断面図である。FIGS. 1(a) and 1(b) are sectional views showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.
まず、第1図(a)に示すように、結晶面が(100)
で比抵抗が0.01Ω・印のP型シリコン基板1に、選
択的にlX102’原子/d程度の濃度にドーピングし
て高濃度不純物拡散領域2を形成する。First, as shown in Figure 1(a), the crystal plane is (100)
A high concentration impurity diffusion region 2 is formed by selectively doping a P-type silicon substrate 1 having a specific resistance of 0.01 Ω· to a concentration of approximately 1×10 2′ atoms/d.
次に、第1図(b)に示すように、P型シリコン基板1
の上にエピタキシャル膜3を10μmの厚さに成長させ
る。エピタキシャル成長では、成長温度1150℃、常
圧、供給ガスとして水素・四塩化シリコン(S i C
14) 、ジボラン(B2 H6)の混合ガスを用いた
。この際、エピタキシャル膜3の比抵抗はジボラン量を
調整して10Ω・Cl11とした。Next, as shown in FIG. 1(b), a P-type silicon substrate 1
An epitaxial film 3 is grown thereon to a thickness of 10 μm. In epitaxial growth, the growth temperature is 1150°C, normal pressure, and hydrogen/silicon tetrachloride (SiC) is used as the supply gas.
14) A mixed gas of diborane (B2H6) was used. At this time, the specific resistance of the epitaxial film 3 was set to 10Ω·Cl11 by adjusting the amount of diborane.
このウェーハを襞間後、欠陥選択エツチング液でエツチ
ングし、ミスフィツト転位の発生を評価した。その結果
、第1図(b)に示すようなミスフィツト転位発生領域
4がが形成されていることが確認された。また、参照試
料として上記の本発明の例と同じ比抵抗で裏面にサンド
ブラストにより歪を付けたP型シリコン基板上にエピタ
キシャル膜を上記の本発明の例と同様に10μmの厚さ
に成長させることにより第2図に示すような従来構造の
エピタキシャルウェーハを得た。After forming the folds, this wafer was etched with a defect-selective etching solution to evaluate the occurrence of misfit dislocations. As a result, it was confirmed that a misfit dislocation generation region 4 as shown in FIG. 1(b) was formed. In addition, as a reference sample, an epitaxial film was grown to a thickness of 10 μm in the same manner as in the above example of the present invention on a P-type silicon substrate with the same resistivity as in the above example of the present invention and whose back surface was strained by sandblasting. As a result, an epitaxial wafer having a conventional structure as shown in FIG. 2 was obtained.
上記2種類のエピタキシャルウェーハを用いダイナミッ
クランダムアクセスメモリ素子(以下DRAM素子と称
す)を作成し、裏面からのパーティクル発生量と素子の
歩留りを比較した。その結果、従来構造のエピタキシャ
ルウェーハではパーティクルの発生が見られたのに対し
、本発明のエピタキシャルウェーハではパーティクルの
発生が見られなかった。Dynamic random access memory devices (hereinafter referred to as DRAM devices) were created using the above two types of epitaxial wafers, and the amount of particles generated from the back surface and the yield of the devices were compared. As a result, generation of particles was observed in the epitaxial wafer of the conventional structure, whereas generation of particles was not observed in the epitaxial wafer of the present invention.
さらにDRAM素子の歩留りは、本発明のエピタキシャ
ルウェーハを用いたDRAM素子では、従来構造のエピ
タキシャルウェーハを用いたものに比べて35%向上し
た。Furthermore, the yield of DRAM devices using the epitaxial wafer of the present invention was improved by 35% compared to that using an epitaxial wafer with a conventional structure.
これは、本発明により裏面からのパーティクルの発生が
なくなったためパーティクルの影響による歩留り低下が
抑えられたためと、ゲッタリング能力の向上によりデバ
イス形成工程での重金属汚染により歩留りの低下が抑え
られたた−めである。This is because the present invention eliminates the generation of particles from the backside, which suppresses the drop in yield due to the influence of particles, and the improved gettering ability suppresses the drop in yield due to heavy metal contamination during the device formation process. It's a good thing.
以上説明したように、本発明は、部分的領域に高濃度不
純物拡散層を形成した基板上にエピタキシャル膜を形成
し、かつ高濃度不純物拡散層と該エピタキシャル膜との
格子定数の違いにより生じるミスフィツト転位を有する
エピタキシャルウェーハ上にデバイス形成することによ
りこのミスフィツト転位発生領域が高い重金属不純物の
ゲッタリング能力を有するためデバイスの歩留りを従来
技術よりも高くすることができた。As explained above, the present invention forms an epitaxial film on a substrate in which a high concentration impurity diffusion layer is formed in a partial region, and eliminates misfit caused by the difference in lattice constant between the high concentration impurity diffusion layer and the epitaxial film. By forming devices on an epitaxial wafer having dislocations, the misfit dislocation generation region has a high gettering ability for heavy metal impurities, making it possible to increase the yield of devices compared to the prior art.
第1図(a)、(b)は本発明の一実施例の製造方法を
説明するための断面図、第2図は従来の半導体ウェーハ
の一例の断面図である。
1・・・P型シリコン基板、2・・・高濃度不純物拡散
領域、3・・・エピタキシャル膜、4・・・ミスフィツ
ト転位発生領域、5・・・素子形成領域、6・・・MO
S)ランジスタ。FIGS. 1(a) and 1(b) are cross-sectional views for explaining a manufacturing method according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of an example of a conventional semiconductor wafer. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... High concentration impurity diffusion region, 3... Epitaxial film, 4... Misfit dislocation generation region, 5... Element formation region, 6... MO
S) Ranjistor.
Claims (1)
と、該半導体基板上にエピタキシャル形成され前記高濃
度不純物拡散領域上にミスフィット転位発生領域が形成
された半導体膜とを有することを特徴とする半導体ウェ
ーハ。It is characterized by having a semiconductor substrate in which a high concentration impurity diffusion region is selectively formed, and a semiconductor film epitaxially formed on the semiconductor substrate and in which a misfit dislocation generation region is formed on the high concentration impurity diffusion region. semiconductor wafers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1169460A JPH0334326A (en) | 1989-06-29 | 1989-06-29 | Semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1169460A JPH0334326A (en) | 1989-06-29 | 1989-06-29 | Semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0334326A true JPH0334326A (en) | 1991-02-14 |
Family
ID=15886992
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1169460A Pending JPH0334326A (en) | 1989-06-29 | 1989-06-29 | Semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0334326A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6524928B1 (en) * | 1999-03-04 | 2003-02-25 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
-
1989
- 1989-06-29 JP JP1169460A patent/JPH0334326A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6524928B1 (en) * | 1999-03-04 | 2003-02-25 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
US6774454B2 (en) | 1999-03-04 | 2004-08-10 | Fuji Electric Co., Ltd. | Semiconductor device with an silicon insulator (SOI) substrate |
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