JPH0332040A - Lsi-bear-chip mounting method and electronic circuit using such method - Google Patents
Lsi-bear-chip mounting method and electronic circuit using such methodInfo
- Publication number
- JPH0332040A JPH0332040A JP16750889A JP16750889A JPH0332040A JP H0332040 A JPH0332040 A JP H0332040A JP 16750889 A JP16750889 A JP 16750889A JP 16750889 A JP16750889 A JP 16750889A JP H0332040 A JPH0332040 A JP H0332040A
- Authority
- JP
- Japan
- Prior art keywords
- lsi
- bare chip
- film
- film circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 33
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 12
- 239000011810 insulating material Substances 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- 239000011888 foil Substances 0.000 claims description 5
- IZJSTXINDUKPRP-UHFFFAOYSA-N aluminum lead Chemical compound [Al].[Pb] IZJSTXINDUKPRP-UHFFFAOYSA-N 0.000 abstract description 6
- 239000011324 bead Substances 0.000 abstract 1
- 239000005001 laminate film Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明はＬＳＩベアチップ実装方法及びこれを利用した
電子回路に係り、特にパンプレスベアチップをフィルム
回路基材に接続する方法及びその方法を用いた電子回路
に関する。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an LSI bare chip mounting method and an electronic circuit using the same, and particularly to a method for connecting a pumpless bare chip to a film circuit substrate and a method using the method. Regarding electronic circuits.
〈従来の技術〉
近年、多用されているフレキシブル回路基材へのベアチ
ップの接続方法として、大体３種類の方法がある。すな
わち、■ワイヤーボンダ一方式、■ＴＡＢ方式、■フリ
ップチップ方式等がそれである。<Prior Art> There are roughly three types of methods for connecting bare chips to flexible circuit substrates that have been widely used in recent years. Namely, these include (1) one-way wire bonder method, (2) TAB method, and (2) flip-chip method.
ワイヤーボンダ一方式は、パターン配線を施した基板の
上に直接ベアチップをグイボンディングしたあと、ワイ
ヤボンディングを施して、ベアチップおよびボンディン
グワイヤ全体を樹脂で封止する方法である。また、ＴＡ
Ｂ方式とは、フィルム回路基材のインナーリードとバン
プ付ＬＳＩペアチツブのバンプを加熱接続等により接続
したあと、前記フィルム回路基材のアウタリードを回路
基板に接続する方法である。The one-way wire bonder method is a method in which a bare chip is directly bonded onto a substrate with patterned wiring, then wire bonding is performed, and the entire bare chip and bonding wires are sealed with resin. Also, T.A.
Method B is a method in which the inner leads of the film circuit base material and the bumps of the bumped LSI pair chip are connected by heat connection or the like, and then the outer leads of the film circuit base material are connected to the circuit board.
〈発明が解決しようとする課題〉
ところで、上記のワイヤーボンダ一方式では、ワイヤー
として金およびアルミニウム等を必要とすることから、
接続ピッチの微細化に問題がある他、製造工程が複雑に
なるものである。すなわち、ワイヤーボンダ一方式では
、チップと端子間の接続の際において、その構造上接続
１箇所当たりワイヤーの接続は２箇所必要である。また
、従来のワイヤーを使用するウェッジボンダ一方式は回
路基板を回転移動させる必要があるので作業の速度が遅
くなるという問題点があり、しかも大型回路基板、ロー
ル式のフィルム回路では設備上できない問題があった。<Problems to be Solved by the Invention> By the way, since the above-mentioned one-type wire bonder requires gold, aluminum, etc. as the wire,
In addition to problems with miniaturization of the connection pitch, the manufacturing process becomes complicated. That is, in the case of a one-type wire bonder, when connecting a chip and a terminal, two wire connections are required for each connection point due to its structure. In addition, the conventional one-type wedge bonder that uses wire has the problem of slowing down the work speed because it requires rotating the circuit board, and this is a problem that cannot be achieved with large circuit boards or roll-type film circuits due to equipment limitations. was there.
また■ＴＡＢ方式では、バンプ工程が必要であることお
よびインナーリードが変形しやすいという問題が残って
いた。さらに、■フリップチップ方式では、やはりバン
ブ工程が必要である。Furthermore, the TAB method still has the problems of requiring a bumping process and easily deforming the inner leads. Furthermore, (1) the flip-chip method still requires a bump process.
本発明は上記事情に鑑みて創案されたもので、新規な方
法をとることにより、前記した問題点を排除できるＬＳ
Ｉベアチップ実装方法及びその方法を利用した電子回路
を提供することを目的としている。The present invention was created in view of the above circumstances, and by adopting a new method, it is possible to eliminate the above-mentioned problems.
The purpose of this invention is to provide a bare chip mounting method and an electronic circuit using the method.
く課題を解決するための手段〉
本発明のＬＳＩベアチップ実装方法は、アルミニウム箔
をラミネートした絶縁フィルムをエツチングにより回路
パターンを作成するとともにＬＳＩ接続部の絶縁材を取
り除くことによりフィルム回路基材を作成し、前記フィ
ルム回路基材にウェッジボンダによりパンプレスベアチ
ップを接続するようにしたことを特徴としている。Means for Solving the Problems> The LSI bare chip mounting method of the present invention involves creating a circuit pattern by etching an insulating film laminated with aluminum foil, and creating a film circuit base material by removing the insulating material at the LSI connection part. The present invention is characterized in that a pump press bare chip is connected to the film circuit substrate using a wedge bonder.
また本発明の電子回路は、アルミニウム箔をラミネート
した絶縁フィルムをエツチングにより回路パターンを作
成するとともにＬＳＩ接続部の絶縁材を取り除くことに
より開口部を形成したフィルム回路基材と、フィルム回
路基材に接続したパンプレスベアチップと、パンプレス
ベアチップ上を覆うモールド部とを具備した電子回路で
あって、前記開口部においてＬＳＩベアチップの端子パ
ッドをフィルム回路基材のアルもリードに接続したこと
を特徴としている。Furthermore, the electronic circuit of the present invention includes a film circuit base material in which a circuit pattern is created by etching an insulating film laminated with aluminum foil, and an opening is formed by removing the insulating material at the LSI connection part; An electronic circuit comprising a connected breadpress bare chip and a mold part covering the breadpress bare chip, characterized in that the terminal pads of the LSI bare chip are connected to the aluminum leads of the film circuit substrate at the openings. There is.
〈実施例〉
以下、図面を参照して本発明に係る一実施例を説明する
。第１図は本発明方法によるＬＳＩベアチップを実装し
た場合の断面図、第２図はフィルム回路基材の平面図で
ある。<Example> Hereinafter, an example according to the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of an LSI bare chip mounted by the method of the present invention, and FIG. 2 is a plan view of a film circuit substrate.
１０は絶縁フィルム、１１は絶縁フィルム１０の開口部
、２０は絶縁フイルム回路上を被覆するアルξり一ドパ
ターン、３０はＬＳＩ ベアチップ、３１はＬＳＩ ベ
アチップ３０のパッド部である。なお４０は前記ＬＳＩ
ベアチップ３０上を覆うモールド部である。５０はウェ
ッジボンダのヘッドを示している。10 is an insulating film, 11 is an opening of the insulating film 10, 20 is an aluminum diagonal pattern covering the insulating film circuit, 30 is an LSI bare chip, and 31 is a pad portion of the LSI bare chip 30. Note that 40 is the LSI
This is a mold part that covers the bare chip 30. 50 indicates a head of a wedge bonder.
以下、本考案に係るＬＳＩベアチップ実装方法について
詳細に説明する。Hereinafter, the LSI bare chip mounting method according to the present invention will be explained in detail.
■絶縁フイルム回路上にアルミニウムを被覆し、絶縁材
ラミネートフィルムを作成する。■Coat aluminum on the insulating film circuit to create an insulating laminate film.
■前記ラミネートフィルムをフォ゛トシステム等により
アルミリードパターンを形成する。(2) Form an aluminum lead pattern on the laminate film using a photo system or the like.
■絶縁フィルム１０のＬＳＩ端子周辺の除去する部分以
外の領域をレジストによりマスキングし、エツチング法
でもって除去することにより、開口部１１を形成する（
ただしエツチング法以外にレーザー照射及び熱風により
絶縁材の開口部を設けてもよい）。■The area around the LSI terminal of the insulating film 10 other than the part to be removed is masked with a resist and removed by an etching method to form the opening 11 (
However, in addition to the etching method, openings in the insulating material may be created using laser irradiation and hot air).
この場合、絶縁フィルム１０の開口部１１は第２図に図
示するように、ＬＳＩの中央部は残し、アウタリード先
端を接続したパターンにしてお（ことによりアルミニウ
ムのインナーリードは変形しにくいという効果がある。In this case, as shown in FIG. 2, the opening 11 of the insulating film 10 is formed in a pattern that leaves the center of the LSI and connects the tips of the outer leads (thereby, the aluminum inner leads are less likely to deform). be.
以上の工程によりフィルム回路基材が作成される。A film circuit base material is created through the above steps.
■前記フィルム回路基材を予め位置決めし、ＬＳＩベア
チップのパッド３１をアルミリードパターン２０に位置
決めする。またウェッジボンダのヘッド５０をスタート
位置に設定する。(2) Position the film circuit substrate in advance, and position the pads 31 of the LSI bare chip on the aluminum lead pattern 20. Further, the head 50 of the wedge bonder is set at the starting position.
■前記工程の後、ウェッジボンダヘッド５０を開口部１
１に挿入し、アルミリードパターン２０とチップのパッ
ド３１を順次接続してゆく。■After the above process, insert the wedge bonder head 50 into the opening 1.
1, and successively connect the aluminum lead pattern 20 and the pad 31 of the chip.
■以上の工程を経た後、ＬＳＩベアチップ全体を樹脂で
もってモールドし、モールド部４０を形成する。(2) After the above steps, the entire LSI bare chip is molded with resin to form a molded portion 40.
〈発明の効果〉
本発明のＬＳＩベアチップ実装方法は、アルミニウム箔
をラミネートした絶縁フィルムをエツチングにより回路
パターンを作成するとともにＬＳＩ接続部の絶縁材を取
り除くことによりフィルム回路基材を作成し、前記フィ
ルム回路基材にウェッジボンダによりパンプレスベアチ
ップを接続するようにしたものであるので、従来方式に
おいて必要であったバンブ工程が必要でなくなる。また
、本願発明の方式であれば、接続箇所が１箇所ですみし
かもアルミリードパターンを直接ＬＳＩベアチップのパ
ッドに接続するので、ワイヤーが不要になるため、従来
のワイヤー使用のウェッジボンダー及びワイヤーボンダ
一方式に比較して接続の速度が１／２以下になり、それ
だけ作業の効率が向上する。<Effects of the Invention> In the LSI bare chip mounting method of the present invention, a circuit pattern is created by etching an insulating film laminated with aluminum foil, a film circuit base material is created by removing the insulating material at the LSI connection part, and the film is Since the pump press bare chip is connected to the circuit substrate using a wedge bonder, the bumping process required in the conventional method is no longer necessary. In addition, with the method of the present invention, there is only one connection point and the aluminum lead pattern is directly connected to the pad of the LSI bare chip, eliminating the need for wires. The connection speed is less than half that of the previous method, and work efficiency is improved accordingly.
第１図は本発明方法によるＬＳＶベアチップを実装した
場合の断面図、第２図はフィルム回路基材の平面図であ
る。
１０・・ ・絶縁フィルム
２０・・・アルごリードパターン
３０・・・ＬＳＩベアチップ
４０・・・モールド部
５０・・・ウェッジボンダヘッドFIG. 1 is a sectional view of an LSV bare chip mounted by the method of the present invention, and FIG. 2 is a plan view of the film circuit substrate. 10... Insulating film 20... Al lead pattern 30... LSI bare chip 40... Mold part 50... Wedge bonder head
Claims (2)
エッチングにより回路パターンを作成するとともにＬＳ
Ｉ接続部の絶縁材を取り除くことによりフィルム回路基
材を作成し、前記フィルム回路基材にウェッジボンダに
よりパンプレスベアチップを接続するようにしたことを
特徴とするＬＳＩベアチップ実装方法。(1) Create a circuit pattern by etching an insulating film laminated with aluminum foil and LS
A method for mounting an LSI bare chip, characterized in that a film circuit base material is created by removing an insulating material at an I connection part, and a pump press bare chip is connected to the film circuit base material using a wedge bonder.
エッチングにより回路パターンを作成するとともにＬＳ
Ｉ接続部の絶縁材を取り除くことにより開口部を形成し
たフィルム回路基材と、フィルム回路基材に接続したパ
ンプレスベアチップと、パンプレスベアチップ上を覆う
モールド部とを具備した電子回路であって、前記開口部
においてＬＳＩベアチップの端子パッドをフィルム回路
基材のアルミリードに接続したことを特徴とする電子回
路。(2) Create a circuit pattern by etching an insulating film laminated with aluminum foil and LS
An electronic circuit comprising a film circuit base material in which an opening is formed by removing an insulating material at an I connection part, a pump press bare chip connected to the film circuit base material, and a mold section covering the pump press bare chip. . An electronic circuit characterized in that terminal pads of an LSI bare chip are connected to aluminum leads of a film circuit substrate in the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16750889A JPH0332040A (en) | 1989-06-29 | 1989-06-29 | Lsi-bear-chip mounting method and electronic circuit using such method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16750889A JPH0332040A (en) | 1989-06-29 | 1989-06-29 | Lsi-bear-chip mounting method and electronic circuit using such method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0332040A true JPH0332040A (en) | 1991-02-12 |
Family
ID=15850982
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16750889A Pending JPH0332040A (en) | 1989-06-29 | 1989-06-29 | Lsi-bear-chip mounting method and electronic circuit using such method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0332040A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5316204A (en) * | 1991-11-08 | 1994-05-31 | Matsushita Electric Industrial Co., Ltd. | Method for bonding lead with electrode of electronic device |
| US5602419A (en) * | 1993-12-16 | 1997-02-11 | Nec Corporation | Chip carrier semiconductor device assembly |
| JP2011258818A (en) * | 2010-06-10 | 2011-12-22 | Ibiden Co Ltd | Printed wiring board, electronic device, and manufacturing method of printed wiring board |
-
1989
- 1989-06-29 JP JP16750889A patent/JPH0332040A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5316204A (en) * | 1991-11-08 | 1994-05-31 | Matsushita Electric Industrial Co., Ltd. | Method for bonding lead with electrode of electronic device |
| US5602419A (en) * | 1993-12-16 | 1997-02-11 | Nec Corporation | Chip carrier semiconductor device assembly |
| US5834338A (en) * | 1993-12-16 | 1998-11-10 | Nec Corporation | Chip carrier semiconductor device assembly and a method for forming the same |
| JP2011258818A (en) * | 2010-06-10 | 2011-12-22 | Ibiden Co Ltd | Printed wiring board, electronic device, and manufacturing method of printed wiring board |
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