JPH03295264A - Multichip semiconductor device - Google Patents
Multichip semiconductor deviceInfo
- Publication number
- JPH03295264A JPH03295264A JP2096422A JP9642290A JPH03295264A JP H03295264 A JPH03295264 A JP H03295264A JP 2096422 A JP2096422 A JP 2096422A JP 9642290 A JP9642290 A JP 9642290A JP H03295264 A JPH03295264 A JP H03295264A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- chip
- chip semiconductor
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の構造とその製造法に係り、特に、
フィルムキャリアを用いた大容量マルチチップ半導体装
置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of a semiconductor device and its manufacturing method, and in particular,
This invention relates to a large-capacity multi-chip semiconductor device using a film carrier.
半導体メモリは、大型コンピュータ、ワークスティジョ
ン、パソコン、ワープロ等の情報機器に多量に使用され
ている。今後、これらの機器の高性能化、製品拡大がさ
らに進むことがら、ここに使われている半導体メモリの
需要も加速的増大していくものと予想される。これに対
し、大容量のメモリを必要とする装置では、機器内での
半導体メモリが占める実装面積は増大する方向にあり、
これが機器の小形、軽量化を阻害する最大の要因となっ
ている。この問題の解決法として、その一つは従来から
強力に押し進められているチップ内素子の高集積化によ
るーチツプ当りのメモリ容量増大である。また、他の一
つはパッケージングされたメモリモジュールをプリント
配線板に高密度に実装する方法であり、さらに、他の一
つは、特開昭５９−１９４４６０号及び特開昭６１−１
８５９５８号公報に述べられているように、複数個の半
導体チップを厚さ方向に積み重ねて高密度化を図るもの
である。Semiconductor memories are widely used in information devices such as large computers, workstations, personal computers, and word processors. In the future, as the performance of these devices continues to improve and the number of products expanded further, demand for the semiconductor memories used in these devices is expected to increase at an accelerated pace. On the other hand, in devices that require large-capacity memory, the mounting area occupied by semiconductor memory within the device is increasing.
This is the biggest factor preventing devices from becoming smaller and lighter. One way to solve this problem is to increase the memory capacity per chip by increasing the integration of the elements within the chip, which has been strongly promoted in the past. Another method is to mount packaged memory modules on a printed wiring board with high density.
As described in Japanese Patent No. 85958, high density is achieved by stacking a plurality of semiconductor chips in the thickness direction.
これらのうち、チップ内素子の高集積化は従来技術の延
長では解決出来ない新しい局面に来ており、新技術、生
産設備の開発が必要である。プリント配線板への高密度
実装方法はモジュールの小形化。Among these, high integration of on-chip elements has reached a new situation that cannot be solved by extending conventional technology, and requires the development of new technology and production equipment. The method for high-density mounting on printed wiring boards is to miniaturize the module.
プリント板への両面実装、 Ｚ Ｔ Ｐ（Ｚｃｇｚａｇ
ｉｎ −１ｉｎｅ Ｐａｃｋａｇｅ）部品の採用等が行
なわれており、−個のチップを一パッケージングとした
モジュールを使う範囲ではこれ以上の大幅な高密度化は
難しい状況にある。これに対し、複数個のＩＣチップを
厚さ方向に積み重ねる方法が非常に有利であり、種々提
案されているが、従来の方法では、マルチチップ半導体
装置をメモリ基板に搭載するときのはんだリフ口工程で
組立用枠とフィルムキャリア装置（以下ＴＡＢ）のアウ
タリードの接合部れが生じ易く、接合強度の変動増大、
温度サイクル寿命の低下、接合端子間短絡が発生しやす
くなる等の不具合があった。Double-sided mounting on printed board, ZTP (Zcgzag
In -1ine package) components are now being adopted, and it is difficult to significantly increase the density any further within the range of using a module in which -1 chips are packaged. In contrast, a method of stacking multiple IC chips in the thickness direction is very advantageous, and various proposals have been made. During the process, the joint between the assembly frame and the outer lead of the film carrier device (hereinafter referred to as TAB) tends to come loose, resulting in increased fluctuations in joint strength.
There were problems such as a decrease in temperature cycle life and an increased tendency for short circuits to occur between bonded terminals.
本発明の目的は、上記従来の不具合点を除去した半導体
装置を提供することにある。An object of the present invention is to provide a semiconductor device that eliminates the above-mentioned conventional drawbacks.
上記目的は、組立枠に開口部の無い凹状の箱形枠とチッ
プ搭載部公金て貫通した開口形枠もしくはチップ搭載部
を除いた部分だけを貫通させた開口形枠を用い、最下層
に凹状の箱形枠を用いてフィルムキャリア半導体装置（
ＴＡＢ）、＆積層組立後、上層枠側から樹脂を適下注入
して、最上層のアウタリード接合部を含め、マルチチッ
プ半導体装置全体を樹脂封止したり、さらに、その上に
上蓋を付加してアウタリード部に押し付は荷重を作用さ
せるようにしたことにより達成される。The above purpose is to use a concave box-shaped frame with no opening in the assembly frame and an opening-shaped frame that penetrates the chip mounting area, or an opening-shaped frame that penetrates only the part excluding the chip mounting area, and a concave box-shaped frame in the bottom layer. A film carrier semiconductor device (
TAB), & After stacking and assembly, the entire multi-chip semiconductor device is encapsulated with resin, including the outer lead joint of the top layer, by injecting a small amount of resin from the upper frame side, and a top cover is added on top of it. This is accomplished by applying a load to the outer lead portion.
すなわち、フィルムキャリアテープに半導体チップを電
気的に接続したフィルムキャリア半導体装置を組立用枠
を介して、二個以上積み重ねてなるマルチチップ半導体
装置において、最下層の組立枠は開口部のない凹状の箱
形枠とし、それ以外の層のものは開口部のある開口形枠
とした。これにより、マルチチップ半導体装置の上層枠
側から、滴下注入された樹脂は、開口形枠を通過して、
最下層枠に貯留され、順に最上層表面まで満し、アウタ
リード部分も含め、マルチチップ半導体全体を封止する
。また、さらにその上に絶縁板にアウタリードに対応し
てピンが配置された上蓋を接着させ付加した。これによ
って、マルチチップ半導体装置をメモリモジュ−ル基板
にはんだリフ口で搭載しても、マルチチップ半導体装置
全体が樹脂で固定されているため、枠とアウタリード接
合部が剥離することがなく、接合の信頼性が向上し、耐
温度サイクル寿命に優れたマルチチップ半導体装置が得
られる。That is, in a multi-chip semiconductor device formed by stacking two or more film carrier semiconductor devices in which semiconductor chips are electrically connected to a film carrier tape via an assembly frame, the bottom assembly frame is a concave structure with no openings. A box-shaped frame was used, and the other layers were made into open-shaped frames with openings. As a result, the resin dripped and injected from the upper frame side of the multi-chip semiconductor device passes through the opening frame.
It is stored in the bottom layer frame and sequentially fills up to the top layer surface, sealing the entire multi-chip semiconductor including the outer lead portion. Furthermore, a top cover with pins arranged corresponding to the outer leads was attached to the insulating plate by adhering it thereon. As a result, even if a multi-chip semiconductor device is mounted on a memory module board with a solder lift port, the entire multi-chip semiconductor device is fixed with resin, so the frame and outer lead joints will not peel off, and the bond will be fixed. A multichip semiconductor device with improved reliability and excellent temperature cycle life can be obtained.
以下、本発明の一実施例を第１図ないし第６図により説
明する。第１図は本発明によるマルチチップ半導体装置
の平面図である。第２図は第１図のマルチチップ半導体
装置の断面図である。第３図はリードピン上蓋でマルチ
チップ半導体装置を密封した本発明の実施例の断面図で
ある。第４図。An embodiment of the present invention will be described below with reference to FIGS. 1 to 6. FIG. 1 is a plan view of a multi-chip semiconductor device according to the present invention. FIG. 2 is a sectional view of the multi-chip semiconductor device of FIG. 1. FIG. 3 is a sectional view of an embodiment of the present invention in which a multi-chip semiconductor device is sealed with a lead pin top cover. Figure 4.
第５図、第６図は本発明によるマルチチップ半導体装置
の組立用枠の平面図及び断面図であり、第６図は最下層
用、第５図は上層用の砕断面である。5 and 6 are a plan view and a cross-sectional view of an assembly frame for a multi-chip semiconductor device according to the present invention, with FIG. 6 being a broken cross-section for the bottom layer and FIG. 5 for the upper layer.
本実施例ではチップ搭載部分に放熱用金属がある枠を用
いた。In this embodiment, a frame with heat dissipation metal in the chip mounting portion was used.
第１図及び第２図において、マルチチップ半導体装置用
枠ｌは基材がガラスエポキシ系で第４図。In FIGS. 1 and 2, the base material of the multi-chip semiconductor device frame 1 is glass epoxy.
第５図、第６図に示すように基材を凹形に切削するとと
もに、上層用は半導体搭載部分および放熱用メタライズ
部分７．７′を除き、基板を貫通した開口部１５．１５
’が設けられているが最下層枠は底のある箱形となって
いる。これらの枠にはＴＡＢのアウタリード１０に対応
するようにアウタリード接続用端子２が設けられチップ
搭載部には放熱用メタライズ７．７′が設けられている
。アウタリード接続端子２．放熱用メタライズ７．７′
の表裏の配線パターンはスルホール５．５’、６及び３
で電気的及び熱伝導的に導通がとられている。As shown in FIGS. 5 and 6, the base material is cut into a concave shape, and for the upper layer, an opening 15.15 is formed through the substrate, excluding the semiconductor mounting area and the heat dissipation metallized area 7.7'.
', but the bottom frame is box-shaped with a bottom. Outer lead connection terminals 2 are provided on these frames so as to correspond to the outer leads 10 of the TAB, and heat dissipation metallization 7.7' is provided on the chip mounting portion. Outer lead connection terminal 2. Heat dissipation metallization 7.7'
The wiring pattern on the front and back of is through holes 5.5', 6 and 3.
Electrical and thermal conduction is maintained.
この組立枠を用いて、第１図、第２図、第３図のマルチ
チップ半導体装置の組立は大略、次の様な手順で行われ
る。まず、第４図に示すガラスエポキシ基板で作られた
最下層用の組立用枠１を組立用治具（ここでは表示せず
）に設けられたピンと枠１の組立位置合わせ用孔４，４
′を利用して、組立治具に搭載し、その上にＴＡＢ８を
乗せて位置を合わせる。更に、その上に第５図に示す上
層用枠を乗せ、ＴＡＢ８を乗せ、第１図、第２図。Using this assembly frame, the multichip semiconductor devices shown in FIGS. 1, 2, and 3 are assembled in roughly the following steps. First, the bottom layer assembly frame 1 made of a glass epoxy substrate shown in FIG.
’ to mount it on the assembly jig, place TAB8 on top of it, and adjust the position. Furthermore, the upper layer frame shown in FIG. 5 is placed on top of it, and TAB8 is placed on top of it, and FIGS.
第３図に示す様にｎ段（ここでは四段）、遂次、積層す
る。積層後、ガラス転移温度１４０°Ｃエポキシ系樹脂
を上層枠表面から注入し、最上層枠のアウタリード接続
用端子２の上まで充填したのが第２図であり、さらに、
最上層のアウタリード接合部の押え効果及び耐湿性向上
のため、樹脂封止されたものに、接合部に対応して、電
極ピン１３が配置されている絶縁性の蓋１４を取りつけ
密封したのが第３図である。尚、密封タイプのものでは
、封止樹脂が無くても同じ様な効果が得られた。As shown in FIG. 3, n stages (here, four stages) are successively laminated. After lamination, an epoxy resin with a glass transition temperature of 140° C. is injected from the surface of the upper layer frame, and is filled up to the top of the outer lead connection terminal 2 of the uppermost layer frame, as shown in FIG. 2.
In order to improve the holding effect and moisture resistance of the outer lead joint part of the top layer, an insulating lid 14 on which electrode pins 13 are arranged corresponding to the joint part is attached to the resin-sealed part and sealed. FIG. In addition, with the sealed type, similar effects were obtained even without the sealing resin.
本発明によれば、最下層の組立枠は開口部のない凹状の
箱形枠とし、上層用枠は開口部のある開口形枠とした。According to the present invention, the lowermost layer assembly frame is a concave box-shaped frame without an opening, and the upper layer frame is an open-shaped frame with an opening.
これにより、マルチチップ半導体装置の樹脂封止が可能
となり、最上層のアウタリード及び接合部分の押え固定
が出来、マルチチップ半導体装置のメモリモジュール基
板への搭載時の、枠とアウタリード接合部分の剥離が無
くなる。This makes it possible to resin-seal a multi-chip semiconductor device, to hold down and fix the top layer outer lead and the joint part, and to prevent the frame and the joint part of the outer lead from peeling off when mounting the multi-chip semiconductor device on a memory module board. It disappears.
第１図は本発明の一実施例のマルチチップ半導体装置の
上面図、第２図は同じく本発明になるマルチチップ半導
体装置の断面図、第３図は本発明になる上蓋付のマルチ
チップ半導体装置の断面図、第４図は本発明によるマル
チチップ半導体装置の組立用枠の平面図、第５図及び第
６図は本発明によるマルチチップの半導体装置の組立用
枠の断面図である。
１−・・組立用枠 ２・・・接続用端子３・・・
スルホール ４・・・位置合せ用孔５．６・・・放
熱用金属のスルホール
７・・・放熱用金属
８・・・フィルムキャリア半導体装置
１２・・・封止用樹脂 １３・・・電極ピン１４・
・・上蓋 １５・・・開ロ部デ１図
凭ｊ閃FIG. 1 is a top view of a multi-chip semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of a multi-chip semiconductor device also according to the present invention, and FIG. 3 is a multi-chip semiconductor with a top lid according to the present invention. FIG. 4 is a plan view of a frame for assembling a multi-chip semiconductor device according to the present invention, and FIGS. 5 and 6 are cross-sectional views of the frame for assembling a multi-chip semiconductor device according to the present invention. 1-... Assembly frame 2... Connection terminal 3...
Through hole 4...Positioning hole 5.6...Through hole in metal for heat radiation 7...Metal for heat radiation 8...Film carrier semiconductor device 12...Sealing resin 13...Electrode pin 14・
・・Top lid 15・Opening part 1 figure
Claims (1)
接続したフィルムキャリア半導体装置を複数個積み重ね
たマルチチップ半導体装置において、 最下層の組立用枠は凹状の箱形とし、それ以外の組立枠
は全てチップ搭載部分を除き、上下が貫通した開口部を
設け、前記組立枠と樹脂封止をしていない前記フィルム
キャリア半導体装置を用いて積層した後、上層枠側から
樹脂を滴下注入して、前記マルチチップ半導体装置の全
体を樹脂封止したことを特徴とするマルチチップ半導体
装置。 ２、フィルムキャリア半導体装置を複数個積み重ねたマ
ルチチップ半導体装置において、最下層の組立用枠は凹
状の箱形とし、それ以外の枠には上下が貫通した開口部
を設け、前記組立枠と樹脂封止後のフィルムキャリア半
導体装置を用いて積層した後、上層枠側から、樹脂を滴
下注入して、最上層のアウタリード接合部を含め、前記
マルチチップ半導体装置の全体を樹脂封止したことを特
徴としたマルチチップ半導体装置。 ３、請求項１または２において、アウタリードに対応し
てピンが配置されている絶縁板の蓋を付加したマルチチ
ップ半導体装置。[Scope of Claims] 1. In a multi-chip semiconductor device in which a plurality of film carrier semiconductor devices in which semiconductor chips are electrically connected to a film carrier tape are stacked, the assembly frame at the bottom layer is in the shape of a concave box; The assembly frame is provided with an opening through which the top and bottom are penetrated, except for the chip mounting part, and after the assembly frame and the film carrier semiconductor device that is not sealed with resin are stacked, resin is dripped from the upper frame side. A multi-chip semiconductor device, characterized in that the entire multi-chip semiconductor device is sealed with a resin by injection. 2. In a multi-chip semiconductor device in which a plurality of film carrier semiconductor devices are stacked, the bottom layer assembly frame is shaped like a concave box, and the other frames are provided with openings passing through at the top and bottom, so that the assembly frame and the resin After stacking using the sealed film carrier semiconductor device, resin is injected dropwise from the upper layer frame side to resin-seal the entire multi-chip semiconductor device including the outer lead joint of the top layer. Featured multi-chip semiconductor device. 3. The multi-chip semiconductor device according to claim 1 or 2, further comprising an insulating plate lid on which pins are arranged corresponding to the outer leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2096422A JPH03295264A (en) | 1990-04-13 | 1990-04-13 | Multichip semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2096422A JPH03295264A (en) | 1990-04-13 | 1990-04-13 | Multichip semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03295264A true JPH03295264A (en) | 1991-12-26 |
Family
ID=14164549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2096422A Pending JPH03295264A (en) | 1990-04-13 | 1990-04-13 | Multichip semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03295264A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998022980A1 (en) * | 1996-11-21 | 1998-05-28 | Hitachi, Ltd. | Semiconductor device and process for manufacturing the same |
-
1990
- 1990-04-13 JP JP2096422A patent/JPH03295264A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998022980A1 (en) * | 1996-11-21 | 1998-05-28 | Hitachi, Ltd. | Semiconductor device and process for manufacturing the same |
| US6664616B2 (en) | 1996-11-21 | 2003-12-16 | Hitachi, Ltd. | Semiconductor device and manufacturing method thereof |
| US6759272B2 (en) | 1996-11-21 | 2004-07-06 | Renesas Technology Corp. | Semiconductor device and manufacturing method thereof |
| KR100447313B1 (en) * | 1996-11-21 | 2004-09-07 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and process for manufacturing the same |
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