JPH0329186A - Multiport sram - Google Patents

Abstract

PURPOSE:To rapidly read out data written at the time of access competition by inputting the output of an access competition detecting circuit to the same address for reading and writing to a gate and short-circuiting the output of a sense amplifier and the 1st writing bit line. CONSTITUTION:The sense amplifier 18 inputs data from the 1st and 2nd reading bit lines 14, 15 and differentially amplifies their potential difference and the access competition detecting circuit 19 outputs a signal for detecting that the writing address and the reading address are the same and writing and reading compete with each other. In the case of normal reading, the output of the sense amplifier 18 is electrically disconnected from the 1st writing bit line 12, and when writing and reading are simultaneously generated to the same address, the output of the circuit 19 is inverted, the output line of the sense amplifier 18 and the bit line 12 are short-circuited and the writing data are directly inputted to an output buffer 40. Thus, rapid reading can be attained even at the time of access competition.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multi-port SRAM capable of reading and writing to the same address.
The present invention relates to a multi-port SRAM in which written values are immediately read out without causing an increase in access time even if an access conflict (access conflict) occurs. This type of multiport SRAM has promising applications as cache memory and CPU registers.

(Prior art) In a conventional multi-port SRAM (Fig. 3), when an access conflict occurs, the contents of the memory cell are first read out to the read bit line, and then the output of the write amplifier is transmitted. Therefore, the read time increases. Therefore, it was decided that access conflict would not be allowed, or that the data that had been written in the memory cell before writing would be read out.

(Problem to be solved by the invention) Multi-port memory is used for memory that is accessed simultaneously from multiple routes, but if there is a conflict between writing and reading to the same address, the written data may be read simultaneously. There are many advantages to configuring the flow to be output, not only because it is faster but also because flow control is easier. However, as described above, in the conventional example, when the contents of the memory cell and the write data are different, the time required for reading increases.

An object of the present invention is to provide a multiport SRAM in which data written during access conflict can be read out at high speed without causing an increase in access time.

(Means for Solving the Problems) A first invention includes a memory cell including a first inverter and a second inverter whose inputs and outputs are connected to each other, and a memory cell that connects the input of the first inverter and a first write bit line. First write FET to connect
a second write FET connecting the input of the second inverter and a second write bit line; a write word line connected to the gates of the first and second write FETs; a first read FET that connects one read bit line; a second read FET that connects the input of the second inverter and the second read bit line; and a read word connected to the gates of the first and second read FETs. a first write amplifier for outputting write data to the first write bit line; a second write amplifier for outputting an inverted result of the write data to the second write bit line; , a sense amplifier that detects the potential difference of the second read bit line and differentially amplifies it, an access conflict detection circuit that detects whether reading and writing are performed to the same address, and a gate input of the output of the access conflict detection circuit. The multi-port SRAM is characterized by comprising a shorting FET connecting the output of the sense amplifier and the first write bit line.

In a second aspect of the invention, in place of the shorting FET, a first shorting FET which uses the output of the access conflict detection circuit as a gate input and connects the first read bit line and the first write bit line is provided. and a second shorting FET which uses the output of the access conflict detection circuit as a gate input and connects the second read bit line and the second write bit line.

(Function) In the first invention, during normal reading, the output of the sense amplifier and the first write bit line are electrically separated by the output of the access conflict detection circuit.
It operates in the same way as M. When writing and reading occur simultaneously to the same address, the output of the access conflict detection circuit is inverted, and the output line of the sense amplifier and the first
Since the write bit line is short-circuited and write data is directly input to the output buffer, high-speed reading is possible even in the event of access conflict.

In the second invention, during normal reading, the first write bit line and the first read bit line, and the second write bit line and the second read bit line are electrically separated from each other by the output of the access conflict detection circuit. Traditional SRAM
works similarly. When writing and reading occur simultaneously to the same address, the output of the access conflict detection circuit is inverted. , first and second short circuit FE
T becomes conductive, the first write bit line and the first read bit line, and the second write bit line and the second read bit line are shorted, respectively, and the write data is input to the sense amplifier regardless of the contents of the memory cell. Because it is possible to
High-speed reading is possible even during access contention.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a 2-baud SRAM according to the first invention of the present application.

Reference numerals 1 and 2 denote a first inverter and a second inverter which input each other's outputs.

The input of the first inverter 1 and the input of the second inverter 2 are
Each has an inverted potential and is in a bistable state. This state continues until an external force is applied to bring the input of each inverter to an inverted potential, and each inverter functions as a static memory cell.

The first write FET 3 connects the input of the first inverter 1 and the first write bit line 12, and uses the write word line 10 as the input of its gate.

The first read FET 4 connects the input of the first inverter 1 and the first read bit line 14, and uses the read word line 11 as the input of its gate.

The second write FET 5 connects the input of the second inverter 2 and the second write bit line 13, and uses the write word line 10 as the input of its gate.

The second read FET 6 connects the input of the second inverter 2 and the second read bit line 15, and uses the read word line 11 as the input of its gate.

The first write amplifier 16 outputs write data to the first write bit line l2.

The second amplifier 17 outputs the inverted result of the write data to the second write bit line 13.

The sense amplifier 18 receives the first read bit line 14 and the second read bit line 15 as inputs, and differentially amplifies the potential difference therebetween.

The access conflict detection circuit 19 outputs a signal that detects that the write address and the read address are the same and there is a conflict between writing and reading.

The short-circuit FET 21 uses the output of the access conflict detection circuit 19 as a gate input, and connects the output of the sense amplifier 18 and the first write bit line.

During a write operation, the first write amplifier 16 sets the first write pit line 12 to the write data potential, and the second write amplifier 17 sets the second write bit line 13 to the inverse potential of the write data. At the same time, write word! iA10 becomes high potential, and the first write FET3 and the second write FET
5 becomes conductive. At this time, the state of the memory cell changes according to the potential of the write bit line, and even after the write operation is completed, the state of the memory cell is maintained as it is, and the write is completed.

During a read operation, the read word line 11 has a high potential, and the first read FET 4 and the second read FET 5 are rendered conductive. At this time, the potential of the first read bit line 14 is
The data potential in the memory cell changes, and the potential of the second read bit line 15 also changes to the inverted potential of the data in the memory cell. It takes a relatively long time for the potential to change because the driving ability of the first inverter 1 and the second inverter 2 is small and a larger load is connected to the read bit line than to the write bit line. However, by amplifying the minute potential difference between the first read bit line 14 and the second read bit line 15 in the sense up 18, the data of the memory cell is read out from the output of the sense amplifier.

During access conflict, both the write word line 10 and the read word line 1l become high potential, and the first and second write FETs
3, 4, and the first and second readout FETs 5 and 6 all become conductive. Therefore, the contents of the memory cell are first read out to the first read bit line 14, and then the output of the first write amplifier 16 is read out. When such an access conflict occurs, the short-circuit FET 21 becomes conductive according to the output of the access conflict detection circuit 19, and the potential of the output line of the sense amplifier is independent of the potentials of the first and second read bit lines 14 and 15. It changes according to the output of the first write amplifier 16. In other words, input data is output as is without going through the memory cells, allowing high-speed reading. If no access conflict occurs, the short-circuit FET 21 becomes open according to the output of the access conflict detection circuit 19, and outputs a memory cell signal as in the conventional system.

The access conflict detection circuit 19 is a circuit that receives n bits of a write address, n bits of a read address, and 2 bits indicating that each address is valid, and outputs a determination result as to whether or not the addresses conflict. ,
Basically, it consists of n exclusive AND gates, one AND gate, and a logical building block for narrowing down the outputs of these n+1 to one.

FIG. 2 shows an embodiment of the second invention. The difference from FIG. 1 is that there are two shorting FETs. 1st short circuit FE
T31 uses the output of the access conflict detection circuit 19 as a gate input, and connects the first read bit line 14 and the first write bit line 1.
Connect 2. The second short-circuit FET 32 receives the output of the access conflict detection circuit 19 as a gate input, and connects the second write bit line 13 and the first read bit line 15.

During access conflict, both the write word line 10 and the read word line 11 become high potential, and the first and second write FETs
3, 4, and the first and second readout FETs 5 and 6 all become conductive. Therefore, the contents of the memory cell are first read out to the first read bit line 14, and then the output of the first write amplifier 16 is about to be read out.

By increasing the speed of the present invention, if an access conflict occurs, the first short-circuit FET 21 and the second short-circuit FET 22 become conductive according to the output of the access conflict detection circuit 19,
The outputs of the first read bit line 14 and the first write amplifier 16 are short-circuited, and the outputs of the second read bit line 15 and the second write amplifier 17 are short-circuited, respectively. The output of the 2 write amplifiers is input, and the write data is read out. In other words, the input data is directly amplified by the sense amplifier without going through the memory cells, allowing high-speed reading. If no access conflict occurs, access conflict detection circuit 1
According to the output of 9, the short-circuit FETs 21 and 22 become open, and the signal of the memory cell is outputted from the memory as in the conventional system.

(Effects of the Invention) As explained above, in conventional multi-port memories, when writing and reading to the same address conflict (access conflict), the access time is longer than normal reading, and the writing The contents previously written in the memory cell are output, and the data to be written and the data to be read may be different. The present invention also provides access contention.
This has the effect of providing a multi-baud SRAM in which reading is performed in the same (or shorter) access time as normal reading.

Furthermore, the access conflict detection circuit basically consists of an exclusive AND gate that is equal to the number of bits in the address, and a logic block for narrowing down its output to one, and when the number of bits in the address, n, is 8, It occupies 2% of the area of the address decoder and can be configured with an extremely small area of 1% or less of the entire memory. Furthermore, the time required for detection is hidden in address decoding and does not affect access time.

Other circuits to be added other than the access conflict detection circuit are:
Another feature is that there is only the same number of short-circuit FETs as the number of bits of the memory (twice as many in the case of the second invention), and the area occupied by the additional portion hardly increases.

[Brief explanation of drawings]

FIG. 1 is a logic circuit block diagram showing an embodiment of the first invention of the present application, and FIG. 2 is a logic circuit block diagram showing an embodiment of the second invention of the application. FIG. 3 is a logic circuit block diagram of a conventionally used multi-port SRAM. 1, 2...first, second inverter, 3,5...first
, second write FET, 4, 6...first, second read FET
ET, 10...Write word line, 1l...Read word line, 12, 13...First and second write bit lines, 14, 15... First and second read bit lines, 16,
17... First and second write amplifiers, 18... Sense amplifiers, 19... Access conflict detection circuit, 21...
Short circuit FET, 31... first short circuit FET, 32... second short circuit FET, 40... output buffer

Claims (2)

[Claims] (1) A first inverter whose input and output are connected to each other,
a memory cell consisting of a second inverter; a first write FET that connects the input of the first inverter and the first write bit line; and a second write FET that connects the input of the second inverter and the second write bit line. , a write word line connected to the gates of the first and second write FETs, a first read FET connecting the input of the first inverter and the first read bit line, and an input of the second inverter and the second read FET. a second read FET for connecting a read bit line; a read word line connected to the gates of the first and second read FETs; and a first write amplifier for outputting write data to the first write bit line. , a second write amplifier for outputting the inverted result of write data to the second write bit line; a sense amplifier that detects and differentially amplifies the potential difference between the first and second read bit lines; an access conflict detection circuit that detects that writing is performed to the same address and outputs the result; and an access conflict detection circuit that uses the output of the access conflict detection circuit as a gate input, and connects the output of the sense amplifier and the first write bit line. A multi-port SRAM characterized by consisting of a connecting short-circuit FET. (2) Instead of the shorting FET described in item 1, the output of the access conflict detection circuit is used as a gate input, and the first read bit line and the first write bit line are connected to each other.
A multi-port SRAM comprising: a shorting FET; and a second shorting FET which uses the output of the access conflict detection circuit as a gate input and connects the second read bit line and the second write bit line. .