JPH0326673Y2 - - Google Patents
Info
- Publication number
- JPH0326673Y2 JPH0326673Y2 JP14019884U JP14019884U JPH0326673Y2 JP H0326673 Y2 JPH0326673 Y2 JP H0326673Y2 JP 14019884 U JP14019884 U JP 14019884U JP 14019884 U JP14019884 U JP 14019884U JP H0326673 Y2 JPH0326673 Y2 JP H0326673Y2
- Authority
- JP
- Japan
- Prior art keywords
- variable resistor
- comparator
- resistor
- delay capacitor
- time delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Description
【考案の詳細な説明】
<産業上の利用分野>
本考案はデユーテイ可変の無安定マルチバイブ
レータに関するものである。[Detailed Description of the Invention] <Industrial Field of Application> The present invention relates to an astable multivibrator with variable duty.
<従来の技術>
従来、デユーテイ可変の無安定マルチバイブレ
ータとして第1図に示すものがあつた。第1図に
おいて、1は直流電源、2は第1の抵抗3、第2
の抵抗4、第3の抵抗5からなる基準電圧発生回
路、6は可変抵抗7、抵抗8、時遅用コンデンサ
9からなる時遅回路、10は第1のコンパレー
タ、11は第2のコンパレータ12はフリツプフ
ロツプ、13は放電用トランジスタである。な
お、基準電圧発生回路2、第1及び第2のコンパ
レータ10,11、フリツプフロツプ12、放電
用トランジスタ13を集積したICとしてタイマ
ー用IC555がある。<Prior Art> Conventionally, there has been a variable duty astable multivibrator as shown in FIG. In Fig. 1, 1 is a DC power supply, 2 is a first resistor 3, a second resistor is
a reference voltage generation circuit consisting of a resistor 4 and a third resistor 5; 6 a delay circuit consisting of a variable resistor 7, a resistor 8, and a delay capacitor 9; 10 a first comparator; 11 a second comparator 12; 1 is a flip-flop, and 13 is a discharge transistor. Note that there is a timer IC 555 as an IC that integrates the reference voltage generation circuit 2, first and second comparators 10 and 11, flip-flop 12, and discharge transistor 13.
第1の抵抗3、第2の抵抗4、第3の抵抗5の
抵抗値を同じくし、直流電源1の電圧をE、可変
抵抗7の抵抗値をRVR(可変)、抵抗8の抵抗値
をR8、時遅用コンデンサ9の容量値をCとして
動作の説明をする。可変抵抗7、抵抗8を通じて
時遅用コンデンサ9が充電され、2E/3を越え
ると、第1のコンパレータ10が“H”レベルに
なり、フリツプフロツプ12がリセツトされて出
力QU-は“H”レベルになり、トランジスタ13
をオンし、時遅用コンデンサ9の電荷を抵抗8を
通じて放電する。時遅用コンデンサ9の電圧が放
電されてE/3以下になると、第2のコンパレー
タ11の出力が“H”レベルになり、フリツプフ
ロツプ12がセツトされて出力QU-は“L”レベ
ルになり、トランジスタ13をオフし、時遅用コ
ンデンサ9の放電は停止し、可変抵抗7、抵抗8
を通じて時遅用コンデンサ9が充電される。この
繰り返しにより発振が行われる。時遅用コンデン
サ9の充電時間(フリツプフロツプ12の出力が
“L”レベルである区間)は1n2・(RVR+R8)・
Cであり、放電時間(フリツプフロツプ12の出
力が“H”レベルである区間)は1n2・R8・Cで
ある。これにより、デユーテイDはR8/(RVR
+2・R8)となり、可変抵抗7で制御出来るデ
ユーテイ範囲はO<D<0.5と狭い。また、発振
周波数fは1/(1n2・(RVR+2・R8)・C)
となり、可変抵抗7によりデユーテイを変えると
発振周波数も変つてしまう。 The resistance values of the first resistor 3, the second resistor 4, and the third resistor 5 are the same, the voltage of the DC power supply 1 is E, the resistance value of the variable resistor 7 is RVR (variable), and the resistance value of the resistor 8 is The operation will be explained assuming that the capacitance values of R8 and the delay capacitor 9 are C. The time delay capacitor 9 is charged through the variable resistor 7 and the resistor 8, and when the voltage exceeds 2E/3, the first comparator 10 becomes "H" level, the flip-flop 12 is reset, and the output Q U- becomes "H". level, transistor 13
is turned on, and the charge in the delay capacitor 9 is discharged through the resistor 8. When the voltage of the time delay capacitor 9 is discharged and becomes less than E/3, the output of the second comparator 11 becomes "H" level, the flip-flop 12 is set, and the output Q U- becomes "L" level. , the transistor 13 is turned off, the discharge of the delay capacitor 9 is stopped, and the variable resistor 7 and the resistor 8 are turned off.
The time delay capacitor 9 is charged through the time delay capacitor 9. This repetition causes oscillation. The charging time of the time delay capacitor 9 (the period in which the output of the flip-flop 12 is at the “L” level) is 1n2・(RVR+R8)・
The discharge time (the period during which the output of the flip-flop 12 is at the "H" level) is 1n2.R8.C. As a result, the duty D is R8/(RVR
+2・R8), and the duty range that can be controlled by variable resistor 7 is narrow: O<D<0.5. Also, the oscillation frequency f is 1/(1n2・(RVR+2・R8)・C)
Therefore, if the duty is changed by the variable resistor 7, the oscillation frequency will also change.
<考案が解決しようとする問題点>
本考案の目的は、上記した従来技術の欠点をな
くすことにある。<Problems to be Solved by the Invention> The purpose of the invention is to eliminate the drawbacks of the prior art described above.
<問題点を解決するための手段、作用>
本考案は、可変抵抗とダイオードの組合せによ
り、時遅用コンデンサへの充電および放電の両方
に影響を与える抵抗がないように工夫したもので
ある。<Means and operations for solving the problems> The present invention is devised so that there is no resistance that affects both charging and discharging of the delay capacitor by combining a variable resistor and a diode.
<実施例>
第2図は本考案の無安定マルチバイブレータで
ある。図において、14は可変抵抗15、ダイオ
ード9、時遅用コンデンサ9からなる時遅回路で
ある。時遅用コンデンサ9への充電は可変抵抗1
5を通じて行われるが、可変抵抗15の摺動端子
と時遅用コンデンサ9側の可変抵抗15端子間の
抵抗による充電時定数に対する影響は、並列に接
続されるダイオード16によつて排除される。一
方、放電は時遅用コンデンサ9側の可変抵抗15
端子から摺動端子、トランジスタ13を通じて行
われる。<Example> FIG. 2 shows an astable multivibrator of the present invention. In the figure, reference numeral 14 is a delay circuit consisting of a variable resistor 15, a diode 9, and a delay capacitor 9. Charging the time delay capacitor 9 is done by variable resistor 1
However, the effect on the charging time constant due to the resistance between the sliding terminal of the variable resistor 15 and the terminal of the variable resistor 15 on the time delay capacitor 9 side is eliminated by the diode 16 connected in parallel. On the other hand, the discharge is caused by the variable resistor 15 on the time delay capacitor 9 side.
This is done from the terminal to the sliding terminal and through the transistor 13.
第1の抵抗3、第2の抵抗4、第3の抵抗5の
抵抗値を同じくし、直流電源1の電圧をE、直流
電源正側の可変抵抗15端子と摺動端子間の抵抗
値をRA(可変)、摺動端子と時遅用コンデンサ9
側の可変抵抗15端子間の抵抗値をRB(可変)、
直流電源正側の可変抵抗15端子と時遅用コンデ
ンサ9側の可変抵抗15端子間の抵抗値をR(=
RA+RB……一定)、時遅用コンデンサ9の容量値
をCとし、ダイオード16の順方向電圧降下及び
トランジスタ13のに飽和コレクターエミツタ電
圧を無視すると、時遅用コンデンサ9の充電時間
(フリツプフロツプの出力が“H”レベルである
区間)は1n2・RA・Cであり、放電時間(フリツ
プフロツプの出力が“L”レベルである区間)は
1n2・RB・Cである。これにより、デユーテイD
はRB/((RA+RB)・C)=RB/Rとなり、可変
抵抗15の摺動端子の移動により制御出来るデユ
ーテイ範囲はO<D<1と広がり、発振周波数f
は1/(1n2・(RA+RB)・C)=1/(1n2・R・
C)となり、可変抵抗15の摺動端子の移動によ
りデユーテイを変えても、発振周波数は変らな
い。 The resistance values of the first resistor 3, the second resistor 4, and the third resistor 5 are the same, the voltage of the DC power supply 1 is set to E, and the resistance value between the variable resistor 15 terminal on the positive side of the DC power supply and the sliding terminal is set to R A (variable), sliding terminal and time delay capacitor 9
The resistance value between the variable resistor 15 terminals on the side is R B (variable),
The resistance value between the variable resistor 15 terminal on the positive side of the DC power supply and the variable resistor 15 terminal on the time delay capacitor 9 side is R (=
R A + R B (constant), the capacitance value of the delay capacitor 9 is C, and if the forward voltage drop of the diode 16 and the saturated collector-emitter voltage of the transistor 13 are ignored, the charging time of the delay capacitor 9 is (the period in which the flip-flop output is “H” level) is 1n2・R A・C, and the discharge time (the period in which the flip-flop output is “L” level) is
1n2・R B・C. As a result, the duty D
is R B /((R A + R B )・C) = R B /R, and the duty range that can be controlled by moving the sliding terminal of the variable resistor 15 expands to O<D<1, and the oscillation frequency f
is 1/(1n2・(R A +R B )・C)=1/(1n2・R・
C), and even if the duty is changed by moving the sliding terminal of the variable resistor 15, the oscillation frequency does not change.
<考案の効果>
本考案によれば、周波数を変えることなくデユ
ーテイを変えることができる。さらに、デユーテ
イの可変範囲も広くとれる。<Effects of the invention> According to the invention, the duty can be changed without changing the frequency. Furthermore, the duty can be varied over a wide range.
第1図は従来のデユーテイ可変の無安定マルチ
バイブレータの回路図、第2図は本考案の無安定
マルチバイブレータの回路図である。
図において、2は基準電圧設定回路、10は第
1のコンパレータ、11は第2のコンパレータ、
12はフリツプフロツプ、13は放電用トランジ
スタ、14は時遅回路、15は可変抵抗、16は
ダイオードである。
FIG. 1 is a circuit diagram of a conventional variable duty astable multivibrator, and FIG. 2 is a circuit diagram of an astable multivibrator of the present invention. In the figure, 2 is a reference voltage setting circuit, 10 is a first comparator, 11 is a second comparator,
12 is a flip-flop, 13 is a discharge transistor, 14 is a time delay circuit, 15 is a variable resistor, and 16 is a diode.
Claims (1)
い第1乃至第3の抵抗からなる直列の基準電圧設
定回路と、直流電源に接続される可変抵抗及び時
遅用コンデンサとアノードが前記可変抵抗の摺動
端子にカソードが前記可変抵抗と時遅用コンデン
サの接続点に接続されるダイオードからなる時遅
回路と、(−)側入力端子が前記第1の抵抗と第
2の抵抗の接続点に接続され、(+)側入力端子
が前記可変抵抗と時遅用コンデンサの接続点に接
続される第1のコンパレータと、(−)側入力端
子が前記可変抵抗と時遅用コンデンサの接続点に
接続され、(+)側入力端子が前記第2の抵抗と
第3の抵抗の接続点に接続される第2のコンパレ
ータと、リセツト入力端子が前記第1のコンパレ
ータの出力に、セツト端子が前記第2のコンパレ
ータの出力に接続されるフリツプフロツプと、コ
レクタが前記可変抵抗の摺動端子に、エミツタが
直流電源の負側に、ベースがフリツプフロツプの
出力に夫々接続される放電用トランジスタにより
構成される無安定マルチバイブレータ。 A series reference voltage setting circuit connected in series to a DC power source and consisting of first to third resistors having the same resistance value, a variable resistor connected to the DC power source, a delay capacitor, and an anode of the variable resistor. A time delay circuit consisting of a diode whose cathode is connected to the connection point of the variable resistor and the time delay capacitor on a sliding terminal, and a (-) side input terminal is connected to the connection point of the first resistor and the second resistor. a first comparator that is connected to the first comparator, the (+) side input terminal of which is connected to the connection point of the variable resistor and the time delay capacitor; and the (-) side input terminal connected to the connection point of the variable resistor and the time delay capacitor. a second comparator whose (+) side input terminal is connected to the connection point of the second and third resistors; a reset input terminal connected to the output of the first comparator; and a set terminal connected to the output of the first comparator. It consists of a flip-flop connected to the output of the second comparator, and a discharging transistor whose collector is connected to the sliding terminal of the variable resistor, whose emitter is connected to the negative side of the DC power supply, and whose base is connected to the output of the flip-flop. Astable multivibrator.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14019884U JPH0326673Y2 (en) | 1984-09-17 | 1984-09-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14019884U JPH0326673Y2 (en) | 1984-09-17 | 1984-09-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6157629U JPS6157629U (en) | 1986-04-18 |
JPH0326673Y2 true JPH0326673Y2 (en) | 1991-06-10 |
Family
ID=30698554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14019884U Expired JPH0326673Y2 (en) | 1984-09-17 | 1984-09-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0326673Y2 (en) |
-
1984
- 1984-09-17 JP JP14019884U patent/JPH0326673Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6157629U (en) | 1986-04-18 |
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