JPH0325952A - Bipolar cmos hybrid semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate CMOS level wiring in a bipolar region and signal interference from a digital circuit to an analog circuit by providing a level converter in the border region between the bipolar region and a CMOS region. CONSTITUTION:There are a bonding pad 2, a CMOS region 3, a level converter region 4, and a bipolar region 5 on an IC chip 1, and circuits are interconnected by connecting wiring 6 and 7 between CMOS's. Level converters in directions both from the CMOS to an ECL and from the ECL to the CMOS are included in the level converter region 4, and the connection between the bipolar region 5 and the CMOS region 3 is effected via respective level converters. Therefore, a signal line in the CMOS level is not present in the bipolar region 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar CMOS mixed semiconductor integrated circuit, and more particularly to a bipolar CMOS mixed semiconductor integrated circuit in which bipolar transistors and CMOS transistors coexist on the same chip.

[Conventional technology]

Conventionally, such bipolar CMOS mixed semiconductor a-product circuits (hereinafter referred to as B i CMOS-IC) process small, highly accurate signals with bipolar linear circuits, and process digital signals with CMOS circuits. IC
On a chip, a bipolar section and a CMOS section are usually clearly separated and arranged.

Moreover, the bipolar part and CMOS in this type of IC
The interconnection with the department is made directly. In other words, when controlling switching or the like for a predetermined bipolar linear circuit using the output signal of a predetermined CMOS circuit, these two circuits are directly connected, and the bipolar linear circuit receives a CMOS level signal (for example, O-5V). Received directly.

Also, when converting the analog signal of a bipolar circuit into a binary value and supplying it to a digital CMOS circuit as a digital signal, convert it to a CMOS level in each analog circuit, and send the converted digital signal directly to the CMOS circuit. There is.

[Problem to be solved by the invention]

In the conventional BiCMOS-IC described above, a large number of wires carrying CMOS level signals pass through the inside of the bipolar linear circuit. However, multilayer wiring is usually used for wiring on an IC chip, which allows wiring to intersect with each other and expands the degree of freedom in design. In addition, each wiring at the intersection is coupled by a capacitance using the glabella insulating film as a dielectric.Therefore, the amplitude of a CMOS level digital signal is about the same as the power supply voltage, and its rise and fall are Because of the steepness, the differential waveform current of the CMOS level signal leaks to the wiring in other layers connected by the capacitance. Normally, analog circuits handle signals that are much smaller than those at the CMOS level, so if there is a leak from the digital signal to the analog circuit as described above, it will seriously affect the operation of the entire IC. It has the disadvantage of causing a lot of damage. Furthermore, avoiding the intersection of multilayer interconnections in order to prevent such leakage has the drawback of placing significant constraints on integrated circuit design. An object of the present invention is to provide a bipolar CMOS mixed semiconductor integrated circuit that can eliminate signal interference from digital circuits to analog circuits and improve design efficiency.

[Means to solve the problem]

The BiCMOS-IC of the present invention is a bipolar CM in which an analog circuit is formed by bipolar transistors and a digital circuit is formed by CMOS transistors on the same chip.
In the OS mixed semiconductor integrated circuit, a level converter for converting input/output levels between ECL and CMOS is arranged in a boundary area between a bipolar region and a CMOS region, and interconnections between the analog circuit and the digital circuit are connected to the level converter. It is configured to be carried out via.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit layout diagram of a BiCMOS-IC showing an embodiment of the present invention.

As shown in FIG. 1, this embodiment has a bonding pad 2, a CMOS region 3, a level converter region 4, and a bipolar region 5 on an IC chip 1, and the mutual circuits are bipolar CMOS interconnects. They are connected by wires 6 and 7. Level converter area 4 includes CMOS to ECL
and from ECL to CMOS are included, and the aforementioned bipolar region 5 and CMOS region 3 are connected via each level converter.

Therefore, no CMOS level signal line exists within the bipolar region 5.

Figure 2(a). (b) is a circuit diagram of a level converter from a CMOS level to an ECL level, and a circuit diagram of a level converter from an ECL level to a CMOS, respectively showing an example of the level converter in FIG.
FIG. 2 is a circuit diagram of a level converter;

As shown in FIG. 2(a), this level converter
Buffer amplifier 8 connected to the input terminals I1 to I4 and reference voltage REF at the OS level, resistors R, ~R&, and ECL
Level output terminal 0. ~04. For example, when the power supply voltage is 5.5V, 5Vp-p is also required for the CMOS level, but approximately 300mVp-p is sufficient for the ECL level.

Therefore, R2/(Rl+R2)=0. 3
/ 5. If it is set to 0 and R3 to R88 are also set in the same way, it will be converted to an appropriate ECL level.

Furthermore, as shown in FIG. 2(b), this level converter is a converter from the ECL level to the CMOS level, as described above, and a minute difference voltage is applied to the ECL input terminals I, I6. Then, since the voltage gain up to the CMOS level output terminal 07 is large, the CMOS level of approximately the power supply voltage VCC or ground voltage GND is obtained as an output. In addition, Q1~Q
8 is a bipolar transistor, and R9 is a resistor serving as a low current source.

By arranging both the level converters shown in FIGS. 2(a) and 2(b) in the level conversion area 4 shown in FIG. The signal is reduced to an ECL level of about -p, and the large amplitude CMOS level digital signal is wiped out. As a result, the differential waveform current flowing from the digital signal line to the analog signal line can be at a negligible level.

〔Effect of the invention〕

As explained above, the BiCMOS-IC of the present invention has
By placing a level converter in the boundary area between the bipolar area and the CMOS area, CMOS in the bipolar area
By eliminating level wiring, there is the effect of completely eliminating signal interference from digital circuits to analog circuits. Also, since there is no need to consider signal interference during design, design efficiency can be improved. Figure l shows an embodiment of the present invention.
The circuit layout diagram of C, Figure 2 (a) and (1:+) respectively show an example of the level converter in Figure 1.
They are a circuit diagram of a CL level converter and a circuit diagram of an ECL-CMOS level converter.

1... IC chip, 2... Bonding pad, 3
... CMOS area, 4... Level conversion area, 5...
・Bipolar area, 6.7...Bipolar CMOS connection wiring, 8...Buffer amplifier, ■1 to I4...C
MOS level input terminal, 01-04...ECL level output terminal, I5, I6...ECL level input terminal, 0f...
・CMOS level output terminal.

Claims (1)

[Claims] In a bipolar CMOS mixed semiconductor integrated circuit in which digital circuits are formed using CMOS transistors on the same chip in which analog circuits are formed using bipolar transistors, an ECL is applied to the boundary area between the bipolar region and the CMOS region.
- A bipolar CMOS mixed semiconductor integrated circuit, characterized in that a level converter for converting input and output levels between CMOS is arranged, and the analog circuit and the digital circuit are interconnected via the level converter.