JPH03258024A - Parallel a/d converter - Google Patents

Abstract

PURPOSE:To obtain a digital signal output without an error by employing an R-2R ladder resistance network even when malfunction takes place in a comparator. CONSTITUTION:An input voltage V1N is compared with a reference voltage VRi increasing monotonously at a 1st comparator 1 to output a current signal Y1 and its complementary current signal, the inverse of Y1 based on the relation of the quantity, the current signal Y1 is fed to a 1st ladder resistance network 2 and the complementary current signal, the inverse of Y1 are inputted to a 2nd ladder resistance network 3, and the signals are converted into signals with a smooth change. Then outputs Vn and the inverse of Vn are inputted to a 2nd comparator 4 as a comparison signal and a signal corresponding to the input current is outputted independently of the speed of a change in the input signal. Thus, a digital output without an error regardless of malfunctions generated in the comparator 1 is obtained with the simple circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a parallel AD converter which is a high speed AD converter, and more particularly to an ultra high speed parallel AD converter.

(Prior art) An AD converter allows a computer to process an analog signal.
Alternatively, it is a device that converts the signal into a digital signal for storage in a memory or the like. Among these AD converters, parallel AD converters are suitable for high-speed operation, so they have been used for sampling applications up to several hundred MH2 class.

(Problems to be Solved by the Invention) However, when considering further increasing the operating speed and considering operation at several GH2, there are problems as described below.

FIG. 9 is a diagram showing the relationship between the frequency of the input signal and the variation in operating time of each comparator of the AD converter in the AD converter during high-speed operation. In the figure, the horizontal axis represents time and the vertical axis represents the amplitude of the input signal.

Now, assume that a plurality of comparators are operated in order to compare the input signals Vl and v12 with a plurality of reference voltages at time t-To. Due to manufacturing variations, each comparator has
Assume that the operating times are slightly different, and the distribution of the variation is a normal distribution as shown in the figure, and is distributed within ±3σ with T as the center. The input signal is VI in the figure.

When performing AD conversion on a low-frequency input signal like ΔV1 is small and unlikely to cause malfunction. Here, the input signal V, is L=*5in (2rll), and the maximum value of the slew rate SR,,, is SR7□・211! ...(
1). In equation (1), if the frequency f is small, the SR
□, 1 is small, and if the frequency f is large, SR□, 8 becomes large. Therefore, if the input signal is a high frequency like v12, the maximum value of the slew rate SR,... is large, so
The error Δv2 converted into voltage becomes very large. Therefore, if Δv2 is larger than the reference voltage difference VLSB corresponding to the LSH of the AD converter, the comparator that compares it with the reference voltage close to the input signal V may malfunction.

FIG. 10 is a diagram showing the output of each comparator with respect to the input signal. In the figure, the number of comparators is 6 when the digital signal is 6.
If it is a bit, it has 26 bits. and,
A reference voltage VRn corresponding to the nth comparator is inputted to the nth comparator. When an analog signal is input to this comparator string, if the input signal is higher than the reference voltage, the comparator will “
If the comparator outputs "1" and is lower than the reference voltage, the comparator outputs "0".

When the input signal is a low frequency, the nth and n+1th comparators operate accurately because ΔV1 shown in FIG. 9 is small as described above. However, when the input signal is a high frequency, the n-th and (n+1)-th comparators do not necessarily compare the same input voltage value due to variations in the operating time of the comparators. If ΔV2 is larger than vLsB, a malfunction occurs in the n-th and n+1-th comparators as shown in the figure. When the output signal resulting from the malfunction that occurs in this way is input to an AND circuit or an encoder circuit in the AD converter, the AND circuit malfunctions, causing a very large conversion error.

For example, in the AND circuit and encoder circuit that make up a conventional AD converter as shown in Figure 11, a "1" signal is output only from the point where the "0" and "1" signals input from the comparator switch. Then, the signal is input to an encoder circuit, and the encoder circuit generates a digital code corresponding to the position of the switching point. However, if the malfunction signal shown in FIG. 10 is input to this circuit, the output signal from the AND circuit will come from two locations as shown in FIG. 12, and normal AD conversion operation cannot be expected. For example, assume that the comparator input signal is 8, and due to malfunction, 7 and 9 are output.

7+toam+-0111 -・-(2)
9°. , □-1001...(3) Due to malfunction, the output from the encoder circuit is (2) and (
3) to 1111=15++o static, ...(4)(4
), a digital signal with a large error is output.

The present invention has been made in view of the above points, and its purpose is to realize an AD converter that can provide error-free digital output despite malfunctions occurring in the comparator using a simple circuit. .

(Means for Solving the Problems) The present invention, which solves the above problems, has monotonically increasing reference voltage values and a corresponding number of comparator components, and simultaneously compares these reference voltage values with input analog signals. A first parallel AD converter that compares the voltage of the input analog signal with the reference voltage value and outputs a current signal having a value corresponding to the relationship in magnitude and a complementary current signal thereof.
a comparator, and a current output from the component of the first comparator is inputted to each resistor connection point and distributed to each resistance circuit, and the first comparator outputs the resulting potential difference at the resistor connection point. 1 of the R-2R type with a ladder resistor circuit corresponding to the number of comparator components in
Complementary current outputs from the ladder resistance network and each component of the first comparator are input to each resistance connection point and distributed to each resistance network, and the resulting potential difference at the resistance connection point is The output voltages of the output R-2R type second ladder resistance network, the first ladder resistance network, and the second ladder resistance network are inputted, and the magnitudes are compared, and the magnitude of the input voltage is determined. and a second comparator that outputs a signal corresponding to the relationship.

(Function) The first comparator compares the input voltage with a monotonically increasing reference voltage and outputs a current signal and a complementary current signal based on the relationship in magnitude, and the current signal is sent to the first ladder resistance network as a complementary current signal. The current signal is input to the second ladder resistor network to produce a smooth changing signal, and its output is input as a comparison signal to the second comparator, where it is compared and changes the input signal to a signal corresponding to the input voltage. output regardless of the speed.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In the figure, 1 represents N components CI (i −1,2,・
..., n, ..., N), the analog signal VIN is input to the A voltage of each component CI, and the reference voltage VRI corresponding to each component C1 is input to the B voltage. has been done.

The reference voltage VR1 consists of N-1 series-connected resistors R with the same resistance value, and VRII and VR applied across the group.
This is a voltage obtained by dividing the voltage difference between I and I by the resistor R1. The component C of the comparator C1 compares the input signal ■IN inputted to the A voltage with each reference voltage vR1, and the comparator C1 whose input signal VIN is higher than the reference voltage VR
In the comparator CI, "]" is output, and in the low comparator CI, "0" is output.

In this case, the output consists of two outputs, Yl and its complementary signal Y1, and is encoded, for example, as shown below.

When Y>Y, the output is “1”... (5) Y<Y
When , the output is "0'. (6) 2 is a series connected resistor R, and one end is connected to each connection point of the resistor R,
Each component C1 of the comparator C1 is composed of a resistor group consisting of resistors 2R whose other ends are all connected at a single point.
The output Y, is input to the connection point of the series resistor R-
This is a 2R type ladder resistance network A. FIG. 2 shows a connection diagram of this ladder resistance network A2. The characteristic of the ladder resistance network is the connection point A in the diagram. The resistance value when looking to the right is R1 The resistance value when looking to the left is also R
and the connection points A, , A2 . The value when looking to the right from A, and the value when looking to the left from A, , A2', A, - are also characterized as being R, respectively.

Reference numeral 3 denotes a ladder resistance network B having the same configuration as the ladder resistance network A2, and input to the connection point of the output YI of each component C1 of the comparator C1 or the series resistor R. 4 is the output Y of the comparator C1 of the ladder resistance network A2, or the input resistor R.
The output Y of the comparator C1 of the ladder resistance network B3 is input to the voltage VI or the B voltage from the connection point of the resistor R, and the voltage VI or the B voltage is input from the connection point of the resistor R. This is a comparator that compares and outputs the B voltage input.

Reference numeral 5 denotes a logic circuit and an encoder circuit composed of the AND circuit and the encoder circuit shown in FIG. Input analog signal VIN from logic circuit and encoder circuit 5
A digital signal corresponding to the output is output.

Next, the operation of the embodiment configured as described above will be explained.

When the analog signal V I N is input, its voltage is input to the A voltage of each component C constituting the comparator C1. The divided reference voltage VR1 is input to the B voltage of the component C2, and a signal as shown in FIG. 10 is output.

A circuit example of the comparator used in this embodiment and its operation will be explained with reference to FIG. FIG. 3 is a diagram showing an example of a comparator circuit. In the figure, Ql has an analog signal v1N input to its base, and a current Y. (NPN) output via transistor Q3, NPN l-transistor, Q2
has the reference voltage vRfi input to its base, and the current Y7
This is an NPN transistor that outputs the output through an NPN transistor Q4. NPN) transistor Q9 has a clock C.
A complementary signal CLK to the clock CLK is input to the NPN transistor Q+o. During the positive period of clock CLK, transistor Q9 conducts and transistors Q1 . The Q2 circuit operates. When the input signal VIN is higher than the reference voltage vRfi, a larger collector current flows through the transistor Ql than that of the transistor Q2, and the collector voltage of the transistor Q1 becomes lower than the collector voltage of the transistor Q2. Therefore, transistor Q.

The current Y1 outputted via the transistor Q4 is the current Y outputted via the transistor Q4. larger than When the reference voltage V□ is larger than the input signal VIN, the current Y flowing through the transistor Q4 is the transistor Q.

The current flowing through Y is larger than A. Next, transistor Q,
. When the complementary clock signal CLK input to the base of the transistor Q has a positive period, the transistor Q.

When the circuit consisting of Q6 and Q1o operates, in the example mentioned above, the collector voltage of transistor Q is low, so the base voltage of transistor Q7 is low, and therefore its emitter current is also low, so the base voltage of transistor Q6 is low. The current flowing through the circuit of transistors Q4r06 and QIO is also small, and the output current Y7 is further reduced. Also, since the base voltage of transistor Q6 is high, transistor Q
The emitter current of 8 is large, the base voltage of transistor Q is high, the current flowing through transistors Q3, Q5, Qlo is large, and the output current Y. becomes even larger.

In this way, the comparator C1 expands and outputs the relationship between the output current and the complementary output current as a result of comparing the input analog signal VIN and the reference voltage V□, so that the comparator CI and the comparator D4 at the boundary value This makes the comparison results even clearer.

Output current Y7 of comparator C1 is input to ladder resistance network A2. FIG. 4 shows an example of distribution of the output current Y7 of the comparator C1. In the figure, the output current Y0 is the transistor Q21+Q
221-+ Q 2+11 and resistance R6,, Ro2°・
..., Ro, ++ circuit generates m currents Yfi++
Yl12+..., Y7. FIG. The current flowing through each resistor network at the current input point to the ladder resistor network is n-i, n-i+1. ..., n+j
The total current is I tn. Figure 5 shows m-
3 is a diagram showing a state in which the current output in case 3 is connected to a ladder resistance network. FIG. For example, the comparator output of current Y5 is divided into three equal parts and connected to the connection point p4 of the ladder resistance network. p, , p6. At the left end is a constant current source to prevent edge effects. is provided.

Output current Y of comparator C1. is input to ladder resistance network B3. This Y. The ladder resistance network B3 to which is input is also m-3
Considering the case of , the output current Y is obtained by a connection similar to that shown in FIG. is input to the ladder resistance network B3, which is the constant current source I in this case.

is connected to the right end. In the circuit of the embodiment shown in FIG. 1, the output currents Y7 and Y are connected as m-1 to avoid complication of the diagram.

Output current Y of comparator C1. The current distribution in the ladder resistance network A2 when is input to the ladder resistance network A2 will be explained with reference to FIG. Output current Y of component co of comparator C1. is the connection point P of the ladder resistance network A2
, is input. Y. Due to the current output, a current distribution as shown in FIG. 6 is generated in the R-2R type ladder resistance network A2.

In the figure, all series resistances are R, and parallel resistances are 2R,, -2, 2R, -+, 2R,, 2R1 as shown in the figure.
141+2Rn+2. However, their resistance values are all 2R. Also, connect the connection point of the resistor R to Pn as shown in the figure.
-2I P++-1+ Pe + Pn++ +
Let it be Pn+2.

At this time, the current flowing through each resistor is at the connection point P,
Since the resistance values for p, , p, and 2R are all equal R, the sum of the currents flowing due to the input current Y is . If so, the resistance is 2R.

through R to the connection point P. The current flowing into is (1/3)Io
It is. Also, P from Pfi+1 point. . 2 points and resistance 2R
Since the resistance value seen in the two directions of −++ is also R, the current flowing into points P and +1 is (1/2) (1/3) I, respectively.
It is O. Furthermore, P. Resistance 2R from 2 points.

The resistance values when looking in two directions, 2 and right, are also R, so the current flowing into point P, +2 is (1/2)2
・(1/3) Io. Po-1 point, P.

P for both points. . 1 point p Same as n+2 points. Furthermore, each comparator component CI+C2+
. . . The output from +CN is Y, , Y2. −=, Y(Y
, -0 or I. ), the current value I2+1° flowing through the n-th ladder resistor 2R is expressed as (7).

The above equation has a format similar to equation (9), which is the basic equation of a digital filter.

Y(n)−Σ a+ x(n−i)
+(9) In equation (8), the coefficient is (1/2) lN-
” Therefore, equation (8) represents a spatial low-pass filter with i as a variable. From this property, the output string of “1” and “0°” from comparator C1 is smoothed by the ladder resistor network. It is reconstructed as a changing voltage. This is Vo
and complementary output V. This voltage is input to the comparator D4, and it is possible to obtain a continuous comparator output such as "1" and "0" that does not cause malfunctions as shown in FIG. This output is a logic circuit, encoder circuit 5
The signal is inputted into the circuit, and is converted into a digital signal and output as shown in FIG.

FIG. 7 is a diagram showing simulation values of the circuit operation of FIG. 5. This figure shows a case where components C and D of the comparator C1 and the comparator D4 are i-0 to 63, and a 6-bit AD converter is considered here. In the figure, the upper bar graph shows the output from the comparator C1. In this bar graph, the black portion represents the signal “1” and the white portion represents the signal “0”. Also, the curve is the output V of the ladder resistance network A2.

and the output V of the ladder resistance network B3. (vo is the complementary output of V.). The lower bar graph is a graph of the result of comparing and outputting the above outputs V, , V, by the comparator D4. FIG. 7(A) shows a case where the comparator C1 is operating normally, and in this case, the output of the comparator D4 matches the output of the comparator C1.

Figures (b) and (c) show simulation results when the comparator C1 malfunctions. As is clear in the figure,
“1” of comparator C1 caused by the malfunction shown in FIG.
The broken line part where ” and “0” appear alternately is ladder resistance network A.
2 and the ladder resistance network B3, the correction is smoothly performed, and a normal output result is obtained from the comparator D4.

Considering the normal operation of comparator D4, as shown in FIG. 3, comparator CI and comparator D4 in FIG. 1 are so-called clocked comparators, which operate in synchronization with the external clock signal CLK. Moreover, the comparator C1 and the comparator D4 are connected to operate in opposite phases to each other. In other words, when comparator C1 holds the output fixed, comparator D4
An operation is performed in which v4°Vo is input to . Therefore, a signal with a small rate of change that is approximately equal to direct current is input to the comparator D4. Therefore, malfunctions do not occur when comparing signals with a large rate of change.

As explained above, according to this embodiment, by using the R-2R type ladder resistor network, the malfunction of the comparator during high-speed operation of the AD converter is rounded up in an analog manner and passed to the next-stage comparator. This makes it possible to cancel important errors with a simple circuit. In addition, since two stages of comparators are connected in series, it is possible to reduce the metastable state of the comparator, where the output of the comparator does not clearly reach the O or 1 level even after a certain period of time has elapsed. can.

Note that the present invention is not limited to the above embodiments. The method of distributing the output from the comparator to the ladder resistor network is not the method shown in FIG. 5, but the connection shown in FIG. 8 may be used. This circuit has approximately the same ability to prevent malfunctions, and has the advantage of requiring fewer parts.

(Effects of the Invention) As explained in detail above, according to the present invention, even if a malfunction occurs in the comparator, an error-free digital signal output can be obtained by using the R-2R type ladder resistor network. Therefore, the practical effect is great.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a connection diagram of an R-2R type ladder resistor network, Fig. 3 is a diagram showing an example of a comparator circuit, and Fig. 4 is a comparator output. A diagram of an example of distribution in which the current is divided into m parts and the output is distributed to the ladder resistor network. Figure 5 is a diagram of an example of distribution of the comparator output current to the ladder resistor network when m = 3. Figure 6 is a diagram of the distribution example of the comparator output current to the ladder resistor network when m = 3. An explanatory diagram of the current in the circuit of the resistor network, Figure 7 is a diagram showing simulation values of the circuit operation of the example, and Figure 8 is another example of the method of distributing the comparator output current to the ladder resistor network. Figure 9 is a diagram showing the relationship between the frequency of the input signal of a high-speed operation AD converter and the variation in comparator operating time, Figure 1O is an explanatory diagram of the comparator output for input signals of different frequencies, and Figure 11 12 is an explanatory diagram of the operation of the AND circuit and the encoder circuit with respect to the comparator output, and FIG. 12 is an explanatory diagram of the AND circuit output when the comparator malfunctions. 1... Comparator C2... Ladder resistance network A3... Ladder resistance network 4... Comparator D5... Logic circuit, encoder circuit C1... Component D of comparator C1... Comparison Components of device D4 Figure 2

Claims (1)

[Claims] A parallel AD converter that has monotonically increasing reference voltage values and a corresponding number of comparator components, and that simultaneously compares these reference voltage values and an input analog signal, comprising: and the reference voltage value,
A first comparator (1) that outputs a current signal with a value corresponding to the magnitude relationship and its complementary current signal; and a current output from a component (C_1) of the first comparator (1). A ladder corresponding to the number of components (C_1) of the first comparator (1) whose output is input to each resistance connection point and distributed to each resistance circuit, and outputs the resulting potential difference at the resistance connection point. an R-2R type first ladder resistance network (2) having a resistance circuit; and each component (C_1) of the first comparator (1);
A complementary current output from the R-2R type second ladder resistor network (3 ), the output voltages of the first ladder resistance network (2) and the second ladder resistance network (3) are inputted and their magnitudes are compared, and a signal corresponding to the relationship between the magnitudes of the input voltages is generated. A parallel AD converter comprising: a second comparator (4) that outputs .