JPH03248558A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To provide a low-power memory with good data holding characteristics by forming a gate electrode of a driver transistor and covering the gate electrode with insulator, on which is formed a load element with the same pattern as, and in alignment with, the gate electrode. CONSTITUTION:An insulating film 16 and the gate electrodes 23a and 24a of driver transistors 23 and 24 are formed by self-aligned patterning with respect to load elements 32 and 31. In this manner, the insulating film 16 is formed on the gate electrodes 23a and 24a before the formation of source and drain regions 36a-36d of the transistors 23 and 24. Therefore, high-temperature oxidation becomes possible to improve the quality of the insulating film 16. The insulating film does not have to be thick, so that the electric fields from the gate electrodes 23a and 24a can give strong effects on the load elements 32 and 31. As a result, the power consumption of a memory is reduced while good data holding characteristics are maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory called SRAM, in which a memory cell is constructed using a flip-flop consisting of a driving transistor and a load element. It is something.

[Summary of the invention]

In the semiconductor memory as described above, the present invention uses a resistance element as a load element by stacking a load element with the same pattern as the gate electrode on the gate electrode of the driving transistor via an insulating film. Also, power consumption can be reduced while maintaining good data retention characteristics, and if the load element is a load transistor, good data retention characteristics can be obtained.

[Prior art] Resistive load type SRAM is an SRAM that can be highly integrated.
has been generally known for a long time, and recently a stacked CMO3 type SRAM has appeared (for example, "Nikkei Micro Devices J (1988, 9) p.

123-130).

[Problem to be solved by the invention]

However, in conventional resistive load type SRAMs, it is difficult to reduce power consumption while maintaining good data retention characteristics.

On the other hand, in the stacked CVD 3-type SRAM, the driving transistor and the load transistor share a gate electrode, but it is not possible to form a high-quality gate insulating film for the load transistor.

Therefore, it is necessary to thicken the gate insulating film, and the current driving capability of the load transistor is low, making it impossible to obtain good data retention characteristics.

[Means to solve the problem]

In the semiconductor memory according to the present invention, a load element 32.3 having the same pattern as the gate electrodes 23a, 24a is provided on the gate electrodes 23a, 24a of the driving transistor 23.24.
1, 45, and 46 are laminated with an insulating film 16 interposed therebetween.

[Effect]

In the semiconductor memory according to the present invention, load elements 32, 31 .
Since the insulating film 16 and the gate electrodes 23a and 24a of the driving transistors 23.24 can be patterned in a self-aligned manner with respect to the pattern of 45.46, the source and drain of the driving transistors 23.24 Area 3
Before forming gate electrodes 6a to 36d, gate electrodes 23a and 24
An insulating film 16 can be formed on a.

Therefore, high-temperature oxidation is possible, resulting in a high-quality insulating film 16.
This insulating film 16 may be thin. As a result, the electric fields of the gate electrodes 23a, 24a can have a strong influence on the load elements 32, 31, 45, 46.

Therefore, the load element 32, 31, 45, 46 is the resistor element 3.
2.31, this resistance element 32.31 can be operated as a variable resistance.

Further, if the load element 32.31.45.46 is a transistor 45.46, the transistor 45.46 for this load.
46 can be improved.

(Embodiments) Hereinafter, first and second embodiments of the present invention will be described with reference to FIGS. 1 to 5.

Figures 1 to 3 show the first example applied to a resistive load type SRAM.
An example is shown. To manufacture this first embodiment,
As shown in FIG. 2A, a SiO□ film 12 for element isolation and a SiO□ film 13 as a gate insulating film are formed on the surface of the Si substrate 11.
There are three intermembrane structures.

And contact holes 14a to 14 for buried contacts.
c between the SiO□ films 13, and in this state, the polycrystalline Si film 15a containing n-type impurities and the silicide film 15b
A polycide film 15 consisting of is deposited. However, instead of the polycide film 15, only a polycrystalline Si film may be used.

Thereafter, by oxidizing the polycide film 15 at high temperature, a thin SiO□ film 16 is formed on the surface of the polycide film 15, and contact holes 17a and 17b are formed in the SiO□ film 16.
Membrane shape 6. Then, a second layer of polycrystalline Si film 18 is deposited, and n-type impurity ions are implanted into polycrystalline Si film 18 to obtain a predetermined resistance value. And furthermore,
A Sin film 21 is formed on the polycrystalline Si film 18.

Next, as shown in FIG. 2B, the film 21 and the polycrystalline S
The i film 18, the 5iOz film 16, and the polycide film 15 are patterned at the same time in the same pattern.

As a result, the gate electrodes 23a and 24a of the transistors 23 and 24 for driving the flip-flop 22 and the gate electrodes of the transfer transistors 25 and 26, that is, the word line 2
7 are formed by the polycide film 15.

Moreover, the load resistance 31.32 of the flip-flop 22 is
Formed by polycrystalline 5ill18. Thereafter, an n- region 33 is formed in the Si substrate 11 by ion implantation of impurities using the patterned SiO□ film 21 as a mask.

Next, as shown in FIG. 2C, the gate electrodes 23a, 24 are deposited by CVD and RIE of the SiO□ film 34.
The 5t02 film 34 is left as the sidewalls of a, the word line 27, etc.

Then, by ion-implanting impurities again in this state, an n'' region 35 is formed in the Si substrate 11.
The n-type impurity diffuses in a solid phase from the gate electrode 23a 324a also into the portions that are in contact with the gate electrodes 23a and 24a via the gate electrodes 23a and 24a.

In this way, the impurity regions 36a to 36g, which are the source/drain regions of the transistors 23 to 26 of the LDD structure, are
is formed in the Si substrate 11.

Next, a glabella insulating film (not shown) is deposited, and the load resistance 3
1. Contact holes 37a and 37b are opened that reach the opposite ends of the contact holes 17a and 17b.

Then, by depositing a third layer of polycrystalline Si film in this state and patterning this polycrystalline Si film,
A power line 38 and a ground line 41 are formed.

Note that the ground line 41 is connected to the impurity regions 36a and 36c via contact holes (not shown).

After that, a glabellar insulating film (not shown) is further deposited, and contact holes 42a and 4 reaching impurity regions 36f and 36g are formed.
2b, and the bit lines 43.44 are connected to the impurity regions 36f, 36g through these contact holes 42a, 42b.
Connect to.

In the first embodiment manufactured as described above, the impurity region 3
Since the SiO□ film 16 has been formed before the films 6a to 36g, the 5iOz film 16 can be formed by high-temperature oxidation as described above. For this reason, the 5iOz film 1
The SiO□ film 16 film type 6 has good film quality. Therefore, the load resistances 31 and 32 are connected to the gate electrodes 24a and 23a.
It is strongly affected by the electric field and operates as a variable resistor.

That is, when the gate electrodes 24a, 23a are at a high potential, that is, when the storage node is at a high logic level, the load resistor 31.
32 has a slightly lower resistance. Conversely, the gate electrodes 24a, 2
When 3a is at a low potential, that is, when the storage node is at a low logic level, the load resistors 31, 32 either have a higher resistance or remain at their original resistance value.

As a result, in the first embodiment, power consumption can be reduced while maintaining good data retention characteristics.

Furthermore, since the Sing film 16 may be as thin as 6, there are fewer steps and the reliability of the bit lines 43, 44, etc. is high. Moreover, Si
The process is simple because the O□ film 21 film quality 1 resistor 31, 32, the SiO□ film 16 film type 6 electrodes 23a, 24a, and the word line 27 can be patterned at the same time.

Note that n is used to adjust the resistance value of the load resistor 31.32.
The concentration of the type impurity is also the n-type impurity concentration for forming the n-region 33.
The concentration of impurities in the mold is also 1×10'2 to 1×1013.
0 “It is on the order of 2.

Therefore, if the SiO□ film 21 film quality is 1, the load resistance 3
The impurity ion implantation for 1.32 and the impurity ion implantation for forming the n region 33 can be performed.

However, if impurity ions are implanted to form the n1 region 35 with the load resistors 31 and 32 exposed,
The resistance value of the load resistors 31 and 32 becomes too low. Therefore, at this time, it is necessary to mask the load resistors 31 and 32 with a resist.

4 and 5 show a second embodiment applied to a stacked CMO3 type SRAM. In manufacturing the second embodiment, steps up to the formation of impurity regions 36a to 36g are performed in substantially the same manner as in the first embodiment described above.

However, contact holes 17a and 17b are not formed in the 5iOz film 16. Further, since the polycrystalline Si film 18 on the gate electrodes 23a and 24a becomes the active layer 47 and 48 of the load transistor 45 and 46, P' regions 47a and 48a and n region 47b are formed in these active layers 47 and 48. , 48b and p.
° regions 47c and 48C are formed.

The transistors 23 and 45 share the gate electrode 23a, and the 5i02 film 16 serves as the gate insulating film of the transistor 45. The transistors 24 and 46 also share the gate electrode 24a, and serve as a gate insulating film of the SiO□ film 16-film type six transistor 46.

Thereafter, a glabellar insulating film (not shown) is deposited, and contact holes 51a to 51d reaching p'' regions 47a, 47c, 48a, and 48c and contact holes 51e and 51f reaching impurity regions 36b and 36d are opened. Then, in this state, a third layer of polycrystalline Si film is deposited and patterned to form the power supply line 3 days and the wiring layer 52.5.
3.

Next, a glabellar insulating film (not shown) is deposited, and contact holes 54a and 54b reaching impurity regions 36a and 36c are opened. Then, in this state, a fourth layer of polycrystalline Si film is deposited and patterned to form a ground line 41.

Thereafter, in the same manner as in the first embodiment, the bit lines 43, 44
are connected to impurity regions 36f and 36g.

In the second embodiment manufactured as described above, the film 540 and the film 16 which are the gate insulating films of the transistors 45 and 46 are also
It is good that it is thin. Therefore, the n region 47 which is the channel region
b, 48b are strongly influenced by the gate electrodes 23a, 24a. Therefore, the current driving capability of the transistors 45 and 46 is large, and this second embodiment has good data retention characteristics.

〔Effect of the invention〕

In the semiconductor memory according to the present invention, if the load element is a resistance element, this resistance element can be operated as a variable resistance, so power consumption can be reduced while maintaining good data retention characteristics.

Further, if the load element is a transistor, the current driving capability of this transistor can be improved, and thus good data retention characteristics can be obtained.

[Brief explanation of drawings]

FIG. 1 is a plan view of the first embodiment of the present invention, FIG. 2 is a side sectional view taken along the line ■-■ in FIG. 1, and FIG. FIG. 4 is an equivalent circuit diagram of the memory cell of the first embodiment, FIG. 4 is a plan view of the second embodiment, and FIG. 5 is an equivalent circuit diagram of the memory cell of the second embodiment. In addition, in the symbols used in the drawings, 16----------5 i Oz film 22--
---1...-------------1--Flip-flop 23.24-------1 Driving transistor 2
3a, 24a ----- Gate electrode 31.32 ---
−−−−−One load resistance 45.46−−・−・−−−
This is a load transistor.

Claims (1)

[Scope of Claims] In a semiconductor memory in which a memory cell is configured using a flip-flop consisting of a driving transistor and a load element, a gate electrode having the same pattern as the gate electrode is provided on the gate electrode of the driving transistor. A semiconductor memory characterized in that load elements are stacked with an insulating film interposed therebetween.