JPH03241775A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03241775A JPH03241775A JP2038628A JP3862890A JPH03241775A JP H03241775 A JPH03241775 A JP H03241775A JP 2038628 A JP2038628 A JP 2038628A JP 3862890 A JP3862890 A JP 3862890A JP H03241775 A JPH03241775 A JP H03241775A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- protective film
- photoresist
- exposure process
- back side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は透光性基板上に半導体素子等を有する半導体装
置の製造方法に関わる。たとえば、薄膜トランジスタ等
のスイッチング素子と画素電極とをマトリックス状に有
する半導体装置(この場合アクティブマトリックスアレ
イと称する)の製造方法、さらに、このアクティブマト
リックスアレイを用いて液晶を駆動する液晶表示装置や
画像読み取り用センサ等に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device having a semiconductor element or the like on a transparent substrate. For example, there are methods for manufacturing semiconductor devices that have switching elements such as thin film transistors and pixel electrodes in a matrix (referred to as active matrix arrays in this case), and liquid crystal display devices and image reading devices that use this active matrix array to drive liquid crystals. This relates to sensors for use in other applications.
以下液晶表示装置用のアクティブマトリックスアレイの
製造方法を例に説明を行なう。A method for manufacturing an active matrix array for a liquid crystal display device will be described below as an example.
従来の技術 まず、液晶表示装置について説明する。Conventional technology First, a liquid crystal display device will be explained.
第4図は信号保持用コンデンサを備えたアクティブマト
リックスアレイを用いた液晶表示装置の要部の回路図で
ある。破線ABCDで囲まれた表示部に画素(破線Iで
囲まれた部分)を多数マトリックス状に繰り返して有し
ている。各画素には薄膜トランジスタ(以下TPTと称
する)2が作り込まれており、TPTのゲート電極は走
査信号配線7、ソース電極は画像信号配線8に接続され
ており、ドレイン電極は信号保持用コンデンサ3と画素
電極4に接続されている。液晶6は対向電極5と画素電
極4の間に挟まれて駆動される。対向電極5は表示部全
体にわたる広い1枚の電極で構成されている。信号保持
用コンデンサ3は共通配線9にも接続されている(信号
保持用コンデンサ3と共通配線9は省略される場合もあ
る)。10と11と12は周辺回路である。破線ABC
Dで囲まれた表示部のうち液晶6と対向電極5以外の部
分がアクティブマトリックスアレイとしてガラス等の基
板上に作り込まれている(なお図面では配線の本数が少
ないが、TV表示等を行う場合には走査信号配線7と画
像信号配線8の数は数百本を越すものとなる)。なお上
記については例えば、松本正−;電子デイスプレィデバ
イス(1984)オーム社参照。FIG. 4 is a circuit diagram of a main part of a liquid crystal display device using an active matrix array equipped with a signal holding capacitor. The display section surrounded by the broken line ABCD has a large number of pixels (the part surrounded by the broken line I) repeated in a matrix. A thin film transistor (hereinafter referred to as TPT) 2 is built into each pixel, and the gate electrode of the TPT is connected to a scanning signal wiring 7, the source electrode is connected to an image signal wiring 8, and the drain electrode is connected to a signal holding capacitor 3. and is connected to the pixel electrode 4. The liquid crystal 6 is sandwiched between the counter electrode 5 and the pixel electrode 4 and driven. The counter electrode 5 is composed of one wide electrode that covers the entire display section. The signal holding capacitor 3 is also connected to a common wiring 9 (the signal holding capacitor 3 and the common wiring 9 may be omitted). 10, 11, and 12 are peripheral circuits. Broken line ABC
Of the display section surrounded by D, the part other than the liquid crystal 6 and the counter electrode 5 is built on a substrate such as glass as an active matrix array (note that the number of wiring is small in the drawing, but it is used for TV display etc. In some cases, the number of scanning signal wirings 7 and image signal wirings 8 exceeds several hundred). Regarding the above, see, for example, Tadashi Matsumoto, Electronic Display Device (1984) Ohmsha.
このような液晶表示装置に用いるアクティブマトリック
スアレイを作成するにあたり、性能向上や工程の簡略化
を目的として、透光性基板のおもて面〔アクティブマト
リックスアレイの構成要素(TPTや配線や電極等〕を
つくり込む基板面〕に塗着したフォトレジストを基板の
裏面側から露光する場合がある(以下この工程を裏面露
光工程と称する)。そして、この裏面露光工程の後、フ
ォトレジストを現像し、このフォトレジストを用いて基
板のおもて面側の構成材料の加工を行なうことが知られ
ている。When creating an active matrix array for use in such liquid crystal display devices, it is necessary to remove the front surface of the transparent substrate [the active matrix array components (TPT, wiring, electrodes, etc.)] for the purpose of improving performance and simplifying the process. In some cases, the photoresist coated on the substrate surface on which the substrate will be created is exposed from the back side of the substrate (hereinafter this process is referred to as the back exposure process).After this back exposure process, the photoresist is developed. It is known that this photoresist is used to process the constituent material on the front side of the substrate.
この裏面露光工程を使ったアクティブマトリックスアレ
イの製造方法の従来例を第5図を用いて説明する。この
図は模式的な工程断面図であり、1つの画素領域内のT
PTと画素電極の部分を示している。まず透光性基板2
0(コーニング社7059ガラス)上に、ゲート電極2
1と走査信号配線(図示せず)をCr薄膜を使って形威
し〔第5図(a)〕、その後プラズマCVD法を用いて
ゲート絶縁膜22(S + N x i窒化シリコン)
と半導体層23(aSi;アモルファスシリコン)と低
抵抗半導体層24 (n+a−3i ;燐ドープのアモ
ルファスシリコン)を被着する〔第5図(b)〕。その
後ポジ型フォトレジスト25を塗着し裏面露光工程を用
いてフォトレジストを露光する〔第5図(C)L この
後フォトレジストを現像し半導体層(23と24)をエ
ツチングする〔第5図(d)〕。そして透明導電膜(I
TO薄膜)によるソース電極26とドレイン電極27お
よび画素電極28と画像信号配線(図示せず)を−括し
て形威し〔第5図(e)〕、チャンネル部分の低抵抗半
導体層をエツチングする〔第5図(f)〕ことによりア
クティブマトリックスアレイを形威し、そしてこのアク
ティブマトリックスアレイを用いて非常に工程を簡略化
した液晶表示装置が実現される(上記については、たと
えば、用村他「2枚マスクa−3iTFTによるフルカ
ラーLCDJ。A conventional method of manufacturing an active matrix array using this backside exposure process will be explained with reference to FIG. This figure is a schematic cross-sectional view of the process, and T in one pixel area.
The PT and pixel electrode portions are shown. First, transparent substrate 2
0 (Corning 7059 glass), the gate electrode 2
1 and scanning signal wiring (not shown) are formed using a Cr thin film [FIG. 5(a)], and then a gate insulating film 22 (S + N x i silicon nitride) is formed using a plasma CVD method.
A semiconductor layer 23 (aSi; amorphous silicon) and a low resistance semiconductor layer 24 (n+a-3i; phosphorus-doped amorphous silicon) are deposited [FIG. 5(b)]. After that, a positive type photoresist 25 is applied and the photoresist is exposed using a back exposure process [FIG. 5(C)L] After that, the photoresist is developed and the semiconductor layers (23 and 24) are etched [FIG. 5 (d)]. And transparent conductive film (I
The source electrode 26, drain electrode 27, pixel electrode 28, and image signal wiring (not shown) are formed using a TO thin film (FIG. 5(e)), and the low-resistance semiconductor layer in the channel portion is etched. By doing so [FIG. 5(f)], an active matrix array is formed, and a liquid crystal display device with a greatly simplified process is realized using this active matrix array (for example, see Yomura et al. Other "Full color LCD DJ with 2 mask a-3i TFT.
1989年テレビジョン学会全国大会講演予講集P、7
7参照)。またこの他にもネガ型フォトレジストに裏面
露光工程を行い基板のおもて面側の構成材料を加工する
ものも提案されている。1989 Television Society National Conference Preliminary Lectures P, 7
(see 7). In addition to this, a method has also been proposed in which a negative photoresist is subjected to a backside exposure process to process the constituent material on the front side of the substrate.
発明が解決しようとする課題
裏面露光工程は利用価値の高い優れた工程である。反面
この工程を用いる場合に、基板裏面にゴξや傷があると
、その部分にフォトレジストの露光不足を招き、この露
光不足の程度によってはエツチング不良などの加工不良
を発生することになる。たとえば、第6図(a)に示し
たように透光性基板30にゴミ31やキズ32が有る状
態でポジ型フォトレジスト33に対して裏面露光工程を
行うと、これを現像したときに露光不足によるレジスト
残り34が発生する。このレジスト残りが発生した状態
でエダチングを行うと、不要な部分に半導体層35が残
ってしまう〔第6図(b)〕。このように裏面露光工程
を用いた半導体装置の製造方法を実施する場合には、基
板裏面に付いたゴξや傷を減らすための工程管理が非常
に重要な課題となる。ゴξの場合は洗浄を徹底すれば問
題回避も可能であるが、−旦発生した傷に関しては洗浄
では全く効果がない。Problems to be Solved by the Invention The backside exposure process is an excellent process with high utility value. On the other hand, when using this process, if there are gores or scratches on the back surface of the substrate, the photoresist will be underexposed in those areas, and depending on the degree of this underexposure, processing defects such as etching defects will occur. For example, if a backside exposure process is performed on the positive photoresist 33 with dust 31 and scratches 32 on the transparent substrate 30 as shown in FIG. 6(a), when it is developed, the exposure Resistance 34 occurs due to shortage. If etching is performed with this resist remaining, the semiconductor layer 35 will remain in unnecessary areas [FIG. 6(b)]. When carrying out a method of manufacturing a semiconductor device using a backside exposure process as described above, process control to reduce scratches and scratches on the backside of the substrate becomes a very important issue. In the case of scratches, it is possible to avoid the problem by thorough cleaning, but cleaning has no effect on scratches that have already occurred.
本発明はこの課題に着目し、基板裏面の傷(ゴミを含め
る場合もある)に起因する加工不良の発生を抑制するこ
とを目的としている。The present invention has focused on this problem and aims to suppress the occurrence of processing defects caused by scratches (which may include dust) on the back surface of the substrate.
課題を解決するための手段
上記課題を解決するための本発明の技術的手段は、
(a)あらかしめ透光性基板の裏面に保護膜を形威して
おき(全工程の最初に行なっておくのが望ましい)、裏
面露光工程の直前に保護膜を除去する。Means for Solving the Problems The technical means of the present invention for solving the above problems is as follows: (a) Forming a protective film on the back side of the pre-warmed translucent substrate (this is done at the beginning of the entire process). (preferably), the protective film is removed immediately before the backside exposure process.
(b)透光性基板の裏面に保護膜を形威し、保護膜を介
して裏面露光工程を行なう。(b) A protective film is formed on the back surface of the transparent substrate, and a back surface exposure process is performed through the protective film.
(C)透光性基板の裏面に液体層を形威し、液体層を介
して裏面露光工程を行なう。(C) A liquid layer is formed on the back side of the transparent substrate, and a back side exposure process is performed through the liquid layer.
である。It is.
作用
上記手段(a)によれば、基板裏面側の保護膜上にキズ
及びゴごが発生することになるので、裏面露光直前に保
護膜と共にキズ及びゴくを簡単に除去することができる
。また上記手段(b)〜(C)によれば、露光時のキズ
による反射が抑えられる(透光性基板と同程度の屈折率
を有する保護膜または液体層を用いるのが最適である)
。これらの方法により、基板裏面のキズやゴξに起因し
て起こる裏面露光工程に伴うレジスト残りが低減される
ことになり、不良の発生を抑えることができる。Effect According to the above means (a), since scratches and dents are generated on the protective film on the back side of the substrate, the scratches and dents can be easily removed together with the protective film immediately before exposure of the back side. Further, according to the above means (b) to (C), reflection due to scratches during exposure can be suppressed (it is optimal to use a protective film or liquid layer having a refractive index similar to that of the transparent substrate).
. These methods reduce the amount of resist remaining during the backside exposure process caused by scratches and gore ξ on the backside of the substrate, thereby suppressing the occurrence of defects.
実施例 以下、本発明の実施例を図面をもとに説明する。Example Embodiments of the present invention will be described below with reference to the drawings.
第1図は本発明の第1の実施例の説明図であり、アクテ
ィブマトリックスアレイの製造方法を説明するための模
式的な工程断面図(一部)を示している(第5図のアク
ティブマトリックスアレイとほぼ同様の構成のものを作
成している)。同図では裏面露光工程の前にキズ41が
透光性基板40に発生した場合を示している〔第1図(
a)〕。そこでポジ型フォトレジスト42をおもて面に
塗着する直前に保護膜43〔露光用の紫外光を透過する
膜であればよい、例えばグラスレジン(昭和電工製)、
NHC(8産化学工業製)などが使用できる〕を基板裏
面側に塗着し、裏面露光工程を行った〔第1図(b)〕
。この後フォトレジストを現像し、半導体層のエツチン
グを行った〔第1図(C)〕。そして第5図と同様にし
てソース電極・ドレイン電極・画素電極等を形威しアク
ティブマトリックスアレイを完成した。本実施例におい
て、保護膜43を塗着する事により裏面キズに起因する
レジスト残り(及びエツチング不良)の発生が低減した
。FIG. 1 is an explanatory diagram of the first embodiment of the present invention, and shows a schematic process sectional view (part) for explaining the method for manufacturing an active matrix array (the active matrix array shown in FIG. 5). (I am creating something with almost the same configuration as the array). The figure shows a case where a scratch 41 is generated on the transparent substrate 40 before the backside exposure process [Figure 1 (
a)]. Therefore, immediately before coating the positive photoresist 42 on the front surface, a protective film 43 [any film that transmits ultraviolet light for exposure may be used, such as glass resin (manufactured by Showa Denko),
NHC (manufactured by Yasan Kagaku Kogyo), etc., which can be used] was applied to the back side of the substrate, and the back side exposure process was performed [Figure 1 (b)].
. Thereafter, the photoresist was developed and the semiconductor layer was etched [FIG. 1(C)]. Then, in the same manner as shown in FIG. 5, the source electrode, drain electrode, pixel electrode, etc. were formed to complete the active matrix array. In this example, by applying the protective film 43, the occurrence of resist residue (and etching defects) caused by scratches on the back surface was reduced.
次に、本発明の第2の実施例のアクティブマトリックス
アレイの製造方法を説明するための模式的な工程断面図
(一部)を第2図に示す(第1の実施例と同様の構成の
アクティブマトリックスアレイを作成している)。本実
施例の場合には、製造工程の最初に透光性基板50の裏
面側に保護膜51を塗着した。そしてこの後、従来例の
第5図(ハ)までと同様の工程を施した。この場合、基
板の裏面側に発生するゴク52とキズ53のほとんどは
保護膜51の表面に発生することになる〔第2図(a)
〕。そこで保護膜51と共にゴミ52とキズ53を除去
してから、ポジ型フォトレジスト54を塗着し、裏面露
光工程を行った〔第2図(b)〕。この後フォトレジス
トを現像し、半導体層のエツチングを行った〔第2図(
C)〕。そして第5図と同様にしてソース電極・ドレイ
ン電極・画素電極等を形威しアクティブマトリックスア
レイを完成した。本実施例において、保護膜51を用い
る事により、裏面露光工程で発生するレジスト残り(及
びエツチング不良)の発生が低減した。Next, a schematic process sectional view (partial) for explaining the method for manufacturing an active matrix array according to the second embodiment of the present invention is shown in FIG. (creating an active matrix array). In the case of this example, a protective film 51 was applied to the back side of the transparent substrate 50 at the beginning of the manufacturing process. After this, the same steps as in the conventional example up to FIG. 5(c) were performed. In this case, most of the gobs 52 and scratches 53 that occur on the back side of the substrate will occur on the surface of the protective film 51 [Fig. 2 (a)
]. Therefore, after removing the dust 52 and scratches 53 together with the protective film 51, a positive type photoresist 54 was applied, and a backside exposure process was performed [FIG. 2(b)]. After this, the photoresist was developed and the semiconductor layer was etched [Figure 2 (
C)]. Then, in the same manner as shown in FIG. 5, the source electrode, drain electrode, pixel electrode, etc. were formed to complete the active matrix array. In this example, by using the protective film 51, the occurrence of resist residue (and etching defects) generated in the backside exposure process was reduced.
次に、本発明の第3の実施例のアクティブマトリックス
アレイの製造方法を説明するための模式的な工程断面図
(一部)を第3図に示す(第1の実施例と同様の構成の
アクティブマトリックスアレイを作成している)。第1
の実施例同様、裏面露光工程の前にキズ61が透光性基
板60に発生した場合を示している〔第3図(a)〕。Next, a schematic process sectional view (partial) for explaining the method for manufacturing an active matrix array according to the third embodiment of the present invention is shown in FIG. (creating an active matrix array). 1st
As in the embodiment shown in FIG. 3, a scratch 61 is generated on the transparent substrate 60 before the backside exposure process [FIG. 3(a)].
そこでポジ型フォトレジスト62をおもて面に塗着後、
基板全体を液体64(例えば水、他の構成材料に影響の
少ない無い液体で実施できる。)を満たした容器63中
に0
静置し、薄い液体層を介した状態で裏面露光工程を行っ
た[第3図(b)〕。この後フォトレジストを現像し、
半導体層のエツチングを行った〔第3図(C)〕。そし
て第5図と同様にしてソース電極・ドレイン電極・画素
電極等を形威しアクティブマトリックスアレイを充放し
た。本実施例において、液体64を介して露光する事に
より、裏面のキズに起因するレジスト残り(及びエツチ
ング不良)の発生が低減した。Therefore, after applying positive photoresist 62 on the front surface,
The entire substrate was left still in a container 63 filled with a liquid 64 (for example, water, which can be carried out with a liquid that has little effect on other constituent materials), and the back side exposure process was performed with a thin liquid layer interposed therebetween. [Figure 3(b)]. After this, the photoresist is developed,
The semiconductor layer was etched [FIG. 3(C)]. Then, in the same manner as in FIG. 5, the source electrode, drain electrode, pixel electrode, etc. were shaped to charge the active matrix array. In this example, by exposing through the liquid 64, the occurrence of resist residue (and etching defects) caused by scratches on the back surface was reduced.
発明の効果
以上述べたように、裏面露光工程を有する半導体装置の
製造方法において、本発明の手段を採用することにより
、裏面露光工程に伴うレジスト残りが大幅に低減され、
不用部のエツチング残りなどの不良の発生を抑えること
ができ、歩留まりが向上する。Effects of the Invention As described above, by employing the means of the present invention in a method of manufacturing a semiconductor device having a backside exposure step, the amount of resist remaining during the backside exposure step can be significantly reduced.
It is possible to suppress the occurrence of defects such as etching residue in unnecessary parts, and improve yield.
第1図、第2図、第3図はそれぞれ本発明の第1の実施
例、第2の実施例、第3の実施例の半導体装置(アクテ
ィブマトリックスアレイ)の製造方法を説明するための
工程断面図、第4図は薄膜トランジスタを有するアクテ
ィブマトリックスアレイを使用した液晶表示装置の要部
回路図、第5図は従来の半導体装W(アクティブマトリ
ックスアレイ)の工程断面図、第6図は基板裏面に発生
したゴミやキズに伴う不良発生の説明図である。
20、30.40.50.60・・・・・・透光性基板
、31.52・・・・・・ゴミ、32.4L 53.6
1・・・・・・キズ、25.33.42゜54、62・
・・・・・ポジ型フォトレジスト。FIG. 1, FIG. 2, and FIG. 3 are steps for explaining a method for manufacturing a semiconductor device (active matrix array) according to a first embodiment, a second embodiment, and a third embodiment of the present invention, respectively. 4 is a circuit diagram of a main part of a liquid crystal display device using an active matrix array having thin film transistors, FIG. 5 is a sectional view of a process of a conventional semiconductor device W (active matrix array), and FIG. 6 is a back side of a substrate. FIG. 3 is an explanatory diagram of the occurrence of defects due to dust and scratches generated in the product. 20, 30.40.50.60...Transparent substrate, 31.52...Trash, 32.4L 53.6
1... Scratch, 25.33.42°54,62.
...Positive photoresist.
Claims (4)
する工程と、前記透光性基板の裏面側からの光照射によ
り前記フォトレジストを露光する工程と、前記露光工程
を経たフォトレジストを用いて前記透光性基板のおもて
面側の構成要素を加工する工程を有し、かつ前記裏面側
からの露光工程の前に前記透光性基板の裏面側に保護膜
を形成する工程を有する半導体装置の製造方法。(1) A step of depositing a photoresist on the front side of a light-transmitting substrate, a step of exposing the photoresist by irradiating light from the back side of the light-transmitting substrate, and a step of passing through the exposure step. A step of processing components on the front side of the light-transmitting substrate using a photoresist, and applying a protective film on the back side of the light-transmitting substrate before the exposure step from the back side. A method for manufacturing a semiconductor device, comprising a step of forming a semiconductor device.
透過する材料で構成されていることを特徴とする請求項
(1)記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the protective film is made of a material that transmits light used in the exposure step from the back side.
程を有することを特徴とする請求項(1)記載の半導体
装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim (1), further comprising the step of removing the protective film before the step of exposing from the back side.
する工程と、前記透光性基板の少なくとも裏面側に液体
を接触させる工程と、前記液体を介して前記透光性基板
の裏面側から光照射を行い前記フォトレジストを露光す
る工程と、前記露光工程を経たフォトレジストを用いて
前記透光性基板のおもて面側の構成要素を加工する工程
を有する半導体装置の製造方法。(4) a step of depositing a photoresist on the front side of the light-transmitting substrate; a step of bringing a liquid into contact with at least the back side of the light-transmitting substrate; and a step of applying a photoresist to the light-transmitting substrate through the liquid. A semiconductor device comprising a step of exposing the photoresist by irradiating light from the back side of the semiconductor device, and a step of processing components on the front side of the transparent substrate using the photoresist that has undergone the exposure step. Production method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3862890A JP2767958B2 (en) | 1990-02-20 | 1990-02-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3862890A JP2767958B2 (en) | 1990-02-20 | 1990-02-20 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03241775A true JPH03241775A (en) | 1991-10-28 |
JP2767958B2 JP2767958B2 (en) | 1998-06-25 |
Family
ID=12530505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3862890A Expired - Fee Related JP2767958B2 (en) | 1990-02-20 | 1990-02-20 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2767958B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018533211A (en) * | 2015-10-10 | 2018-11-08 | 深▲せん▼市華星光電技術有限公司Shenzhen China Star Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method thereof |
US20210358536A1 (en) * | 2019-06-17 | 2021-11-18 | Micron Technology, Inc. | Interrupt-Driven Content Protection of a Memory Device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61145530A (en) * | 1984-12-19 | 1986-07-03 | Nec Corp | Manufacture of thin-film transistor array |
JPH0242761A (en) * | 1988-04-20 | 1990-02-13 | Matsushita Electric Ind Co Ltd | Active matrix substrate manufacturing method |
-
1990
- 1990-02-20 JP JP3862890A patent/JP2767958B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61145530A (en) * | 1984-12-19 | 1986-07-03 | Nec Corp | Manufacture of thin-film transistor array |
JPH0242761A (en) * | 1988-04-20 | 1990-02-13 | Matsushita Electric Ind Co Ltd | Active matrix substrate manufacturing method |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018533211A (en) * | 2015-10-10 | 2018-11-08 | 深▲せん▼市華星光電技術有限公司Shenzhen China Star Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method thereof |
US20210358536A1 (en) * | 2019-06-17 | 2021-11-18 | Micron Technology, Inc. | Interrupt-Driven Content Protection of a Memory Device |
Also Published As
Publication number | Publication date |
---|---|
JP2767958B2 (en) | 1998-06-25 |
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