JPH03238365A - Low voltage detection circuit - Google Patents
Low voltage detection circuitInfo
- Publication number
- JPH03238365A JPH03238365A JP3542990A JP3542990A JPH03238365A JP H03238365 A JPH03238365 A JP H03238365A JP 3542990 A JP3542990 A JP 3542990A JP 3542990 A JP3542990 A JP 3542990A JP H03238365 A JPH03238365 A JP H03238365A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- channel mos
- low voltage
- terminal
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/32—Compensating for temperature change
Landscapes
- Measurement Of Current Or Voltage (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、定電圧検出回路に関し、特に温度補償型低電
圧検出回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a constant voltage detection circuit, and particularly to a temperature compensated low voltage detection circuit.
第３図は、従来の低電圧検出回路の一例である。 FIG. 3 is an example of a conventional low voltage detection circuit.
第３図の電圧検出回路は１６のＣＭＯＳオペアンプ、抵
抗Ｒ１，Ｒ２，Ｒ３、及び１２のバイポーラトランジス
タのコレクタとベースをショートさせたダイオード６個
により構成されている。The voltage detection circuit shown in FIG. 3 is composed of 16 CMOS operational amplifiers, resistors R1, R2, R3, and 6 diodes whose collectors and bases of 12 bipolar transistors are short-circuited.
この第３図の回路はバンドギャップリファレンス構造を
とっており、１１，１２．１３の各抵抗Ｒ，，Ｒ２，Ｒ
３を適当に定めてやることにより、ダイオードのＶＢＨ
の温度係数による動作電圧の温度依存性を無くすことが
できる。したがって、この従来の回路の動作電圧の温度
補償特性は非常に良いものとなる。ところが、この回路
はＣＭＯＳオペアンプを使用しておりＣＭＯＳオペアン
プの特性を生かしたものとなっているが、ＣＭＯＳオペ
アンプの動作可能な最低電源電圧はこの近来の技術にお
いても３．５〜４ｖ程度であり、乾電池駆動の機器が広
く出回っている中、電源電圧が低い時には厳しい条件と
なる。The circuit shown in Fig. 3 has a bandgap reference structure, and each of the resistors 11, 12, and 13 R, , R2, R
By appropriately setting 3, the VBH of the diode
The temperature dependence of the operating voltage due to the temperature coefficient of can be eliminated. Therefore, the operating voltage temperature compensation characteristics of this conventional circuit are very good. However, although this circuit uses a CMOS operational amplifier and takes advantage of the characteristics of a CMOS operational amplifier, the minimum power supply voltage at which a CMOS operational amplifier can operate is around 3.5 to 4 V even with this recent technology. Although dry battery-powered equipment is widely available, the conditions are severe when the power supply voltage is low.
以上述べた様に、従来の低電圧検出回路は、ＣＭＯＳオ
ペアンプを使用しているため電源電圧が低い時の動作に
問題があり、また素子数が多いという問題があった。As described above, the conventional low voltage detection circuit uses a CMOS operational amplifier, so there is a problem in operation when the power supply voltage is low, and there is also a problem in that the number of elements is large.
このような課題を解決するために、本発明の低電圧検出
回路ではＣＭＯＳオペアンプを使用せずＭＯＳ）ランク
３５１個と抵抗１個のみにより低電圧を検出し、かつ、
温度補償ができるようにしており、その出力をバッファ
により波形を整形している。In order to solve such problems, the low voltage detection circuit of the present invention detects low voltage using only 351 MOS (MOS) ranks and one resistor without using a CMOS operational amplifier, and
Temperature compensation is possible, and the output waveform is shaped by a buffer.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の回路図であり、この低電圧
検出回路は１の第１のＰチャネルＭＯＳトランジスタ及
び４の抵抗の部分と、２の第２のＰチャネルＭＯ３）ラ
ンジスタと３のＮチャネルＭＯＳ）ランジスタからなる
バッファ部分とから構成されている。この回路において
低電圧を検出する部分は、１の第１のＰチャネルＭＯＳ
トランジスタ及び４の抵抗の部分である。５の電源端子
に充分高い電位が印加されていれば、１の第１のＰチャ
ネルＭＯＳトランジスタはオンしているため、４の抵抗
値がこの時のｌのＰチャネルＭＯＳトランジスタのオン
抵抗に比べて、充分大きければ７の出力端子にはローレ
ベルが出力される。しかし、５の電源端子に印加される
電位が低くなってくると、１の第１のＰチャネルＭＯＳ
トランジスタのオン抵抗は増加していき、ある電位に達
すると４の抵抗の値よりも大きくなるため、バッファ部
が動作している領域であれば７の出力端子に出力される
信号は反転しハイレベルとなり、この時の電圧値が検出
される。FIG. 1 is a circuit diagram of an embodiment of the present invention, and this low voltage detection circuit includes a first P-channel MOS transistor (1), a resistor section (4), and a second P-channel MOS transistor (2). The buffer part consists of three N-channel MOS) transistors. In this circuit, the part that detects low voltage is the first P-channel MOS
This is the transistor and the resistor part 4. If a sufficiently high potential is applied to the power supply terminal 5, the first P-channel MOS transistor 1 is on, so the resistance value of 4 is compared to the on-resistance of the P-channel MOS transistor 1 at this time. If it is large enough, a low level is output to the output terminal 7. However, when the potential applied to the power supply terminal 5 becomes low, the first P-channel MOS
The on-resistance of the transistor increases, and when it reaches a certain potential, it becomes larger than the value of the resistance of 4, so if the buffer section is in operation, the signal output to the output terminal of 7 is inverted and goes high. level, and the voltage value at this time is detected.
次に第１図の低電圧検出回路のシミュレーション結果に
ついて説明する。Next, simulation results of the low voltage detection circuit shown in FIG. 1 will be explained.
第４図は第１図の回路の５ＰＩＣＥによるＤＣ特性のシ
ミュレーションの結果であり、温度をパラメータに取っ
ている。横軸は５の電源端子に印加される電圧値であり
、縦軸は７の出力端子に出力される電圧値である。この
結果から電源電圧が約３ｖ以下になれば出力はハイレベ
ルになり、また約３ｖ以上であれば出力はローレベルに
なることから、この回路で３ｖが検出できることになる
。FIG. 4 shows the results of a simulation of the DC characteristics of the circuit shown in FIG. 1 using 5PICE, using temperature as a parameter. The horizontal axis is the voltage value applied to the power terminal 5, and the vertical axis is the voltage value output to the output terminal 7. From this result, if the power supply voltage is about 3V or less, the output will be at a high level, and if it is about 3V or more, the output will be at a low level, so this circuit can detect 3V.
また、温度を一４０℃〜１５０℃まで変化させてシミュ
レーションをしているが、この時の動作電圧の変化は２
．８８１７Ｖ （ＭＩＮ） 〜２．９９６０ Ｖ（ＭＡ
Ｘ）であり、その差！ｔＯ，１１４３Ｖ、！：小さく動
作電圧は温度について補償されている。今回のシミュレ
ーションにあたって温度特性を見るためにＭＯＳ）ラン
ジスタのモデルパラメータのレベルは２を用い、また抵
抗の１次温度係数を２０００ＰＰＭ／℃とした。In addition, the simulation is performed by changing the temperature from -40℃ to 150℃, but the change in operating voltage at this time is 2
．． 8817V (MIN) ~2.9960V (MA
X) and the difference! tO,1143V,! : Small operating voltage is compensated for temperature. In this simulation, in order to observe the temperature characteristics, the model parameter level of the MOS transistor was set to 2, and the primary temperature coefficient of resistance was set to 2000 PPM/°C.
第２図は本発明の実施例２の回路図である。第２図の低
電圧検出回路は、本発明の実施例１の回路図である第１
図の回路の１と４からなる検出部分が異っており、４の
抵抗と８の第１ＮチャネルＭＯＳトランジスタから構成
されている。第２図の回路の動作は５の電源電圧が充分
に高い時には８の第１ＮチャネルＭＯＳトランジスタは
オンしており、１１の出力端子にはハイレベルが出力さ
れ、低電圧時には実施例１と同様の考え方で出力は反転
しローレベルが出力されることになる。したがって第２
図の回路は第１図の回路に対して出力信号は論理的に逆
となるが、この低電圧検出回路の出力信号の他の回路へ
の使用法により、第１図の回路か、第２図の回路かを選
択することができる。FIG. 2 is a circuit diagram of a second embodiment of the present invention. The low voltage detection circuit shown in FIG.
The detection portions 1 and 4 of the circuit shown in the figure are different, and are composed of 4 resistors and 8 first N-channel MOS transistors. The operation of the circuit shown in FIG. 2 is that when the power supply voltage 5 is sufficiently high, the first N-channel MOS transistor 8 is on, and a high level is output to the output terminal 11, and when the voltage is low, it is the same as in the first embodiment. Based on this idea, the output will be inverted and a low level will be output. Therefore, the second
The output signal of the circuit shown in the figure is logically opposite to that of the circuit shown in Fig. 1, but depending on how the output signal of this low voltage detection circuit is used in other circuits, the circuit shown in Fig. 1 or the circuit shown in Fig. 2 You can choose the circuit shown in the figure.
以上説明したように本発明は、温度補償がされた低電圧
の検出をＣＭＯＳオペアンプを使用せずに行うことがで
きるので、低電圧時においても充分動作し、また素子数
を減らすことができるという効果がある。As explained above, the present invention can perform temperature-compensated low voltage detection without using a CMOS operational amplifier, so it can operate satisfactorily even at low voltages and can reduce the number of elements. effective.
第１図は本発明の一実施例の回路図、第２図は第２の実
施例の回路図、第３図は従来の技術を示す回路図、第４
図は第１図の回路のシミュレーション結果を示す特性図
である。
１・・・・・・第１ＰチヤネルＭＯＳトランジスタ、２
・・・・・・第２ＰチヤネルＭＯＳトランジスタ、３・
・・・・・ＮチャネルＭＯＳトランジスタ、４・・・・
・・抵抗、５・・・・・・電源端子、６・・・・・・接
地端子、７・・・・・・出力端子、８・・・・・・第１
ＮチャネルＭＯＳトランジスタ、９・・・・・・Ｐチャ
ネルＭＯＳトランジスタ、１０・・・・・・第２Ｎチャ
ネルＭＯＳトランジスタ、１１・・・・・・出力端子、
１２・・・・・・バイポーラトランジスタ、１３・・・
・・・抵抗Ｒ１，１４・・・・・・抵抗Ｒ２，１５・・
・・・・抵抗Ｒ８，１６・・・・・・ＣＭＯＳオペアン
プ、１７・・・・・・出力端子。Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a second embodiment, Fig. 3 is a circuit diagram showing a conventional technique, and Fig. 4 is a circuit diagram of an embodiment of the present invention.
The figure is a characteristic diagram showing simulation results of the circuit of FIG. 1. 1...First P channel MOS transistor, 2
...Second P channel MOS transistor, 3.
...N-channel MOS transistor, 4...
...Resistance, 5...Power terminal, 6...Ground terminal, 7...Output terminal, 8...1st
N-channel MOS transistor, 9... P-channel MOS transistor, 10... second N-channel MOS transistor, 11... output terminal,
12... Bipolar transistor, 13...
... Resistor R1, 14... Resistor R2, 15...
...Resistor R8, 16...CMOS operational amplifier, 17...Output terminal.
Claims (3)
接地端子に接続し、ソースを電源端子に接続し、ドレイ
ンを抵抗の一端に接続し、抵抗の他端を接地端子に接続
し、第１のＰチャネルＭＯＳトランジスタのドレインを
第２のＰチャネルＭＯＳトランジスタとＮチャネルＭＯ
Ｓトランジスタで構成されるＣＭＯＳインバータの入力
端子に接続することにより構成される温度補償型低電圧
検出回路。(1) The gate of the first P-channel MOS transistor is connected to the ground terminal, the source is connected to the power supply terminal, the drain is connected to one end of the resistor, the other end of the resistor is connected to the ground terminal, and the first P-channel MOS transistor is connected to the ground terminal. The drain of the P-channel MOS transistor is connected to the second P-channel MOS transistor and the N-channel MO
A temperature compensated low voltage detection circuit configured by connecting to the input terminal of a CMOS inverter configured with S transistors.
の入力端子にＮチャネルＭＯＳトランジスタのドレイン
及び抵抗の一端を接続し、前記ＮチャンネルＭＯＳトラ
ンジスタのゲートを電源端子に接続し、ソースを接地端
子に接続し、抵抗の他端を電源端子に接続することを特
徴とする温度補償型低電圧検出回路。(2) The drain of an N-channel MOS transistor and one end of a resistor are connected to the input terminal of the CMOS inverter according to claim 1, the gate of the N-channel MOS transistor is connected to a power supply terminal, and the source is connected to a ground terminal. A temperature compensated low voltage detection circuit characterized in that the other end of the resistor is connected to a power supply terminal.
成され２０００ＰＰＭ／℃程度の正の温特を持つ事を特
徴とする温度補償型低電圧検出回路。(3) A temperature compensated low voltage detection circuit characterized in that the resistor according to claim 1 is constituted by a diffused resistor and has a positive temperature characteristic of about 2000 PPM/°C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3542990A JPH03238365A (en) | 1990-02-15 | 1990-02-15 | Low voltage detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3542990A JPH03238365A (en) | 1990-02-15 | 1990-02-15 | Low voltage detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03238365A true JPH03238365A (en) | 1991-10-24 |
Family
ID=12441618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3542990A Pending JPH03238365A (en) | 1990-02-15 | 1990-02-15 | Low voltage detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03238365A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5644546A (en) * | 1992-09-11 | 1997-07-01 | Fujitsu Limited | MOS static RAM with improved soft error resistance; high-level supply voltage drop detection circuit and complementary signal transition detection circuit for the same; and semiconductor device with improved intersignal time margin |
| JP2007166685A (en) * | 2005-12-09 | 2007-06-28 | Ricoh Co Ltd | Backflow prevention circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5719676A (en) * | 1981-06-01 | 1982-02-01 | Seiko Epson Corp | Voltage detecting circuit |
| JPS6188549A (en) * | 1984-10-05 | 1986-05-06 | Citizen Watch Co Ltd | Semiconductor integrated circuit with battery life detection circuit |
| JPS61249126A (en) * | 1985-04-27 | 1986-11-06 | Toshiba Corp | Circuit for detecting fall of supply voltage |
-
1990
- 1990-02-15 JP JP3542990A patent/JPH03238365A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5719676A (en) * | 1981-06-01 | 1982-02-01 | Seiko Epson Corp | Voltage detecting circuit |
| JPS6188549A (en) * | 1984-10-05 | 1986-05-06 | Citizen Watch Co Ltd | Semiconductor integrated circuit with battery life detection circuit |
| JPS61249126A (en) * | 1985-04-27 | 1986-11-06 | Toshiba Corp | Circuit for detecting fall of supply voltage |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5644546A (en) * | 1992-09-11 | 1997-07-01 | Fujitsu Limited | MOS static RAM with improved soft error resistance; high-level supply voltage drop detection circuit and complementary signal transition detection circuit for the same; and semiconductor device with improved intersignal time margin |
| US5734622A (en) * | 1992-09-11 | 1998-03-31 | Fujitsu Limited | MOS static RAM with improved soft error resistance; high-level supply voltage drop detection circuit and complementary signal transition detection circuit for the same; and semiconductor device with improved intersignal time margin |
| JP2007166685A (en) * | 2005-12-09 | 2007-06-28 | Ricoh Co Ltd | Backflow prevention circuit |
| JP4597044B2 (en) * | 2005-12-09 | 2010-12-15 | 株式会社リコー | Backflow prevention circuit |
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