JPH03234051A - Manufacture of capacitive element - Google Patents

Abstract

PURPOSE:To increase the memory cell capacity without sacrifice of the flatness on the surface of a semiconductor substrate by forming a polycrystalline silicon film on the semiconductor substrate, implanting ions into the polycrystalline silicon film and then roughening the surface of the polycrystalline silicon film. CONSTITUTION:An LOCOS oxide film 12, and a gate oxide film 13 are formed on a P-type semiconductor substrate 11, a poly-Si gate 14 is formed on the gate oxide film 13, a source/drain diffusion layer 15 and a CVD oxide film 16 are formed thereon, a contact hole 17 is made at a predetermined position on the source/drain diffusion layer 15, a poly-Si film 18 is formed thereon and thermally diffused with phosphorus, and then argon, arsenic or silicon ions are implanted into the poly-Si film 18 thus forming an impurity injection layer 19. At this time, micro irregularities are formed on the surface of the impurity injection layer 19. A capacitive insulation layer 20 composed of a silicon nitride film and a silicon oxide film is then formed thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a capacitive element in which a capacitive insulating film is formed on a polycrystalline silicon film.

Conventional technology In large-capacity dynamic random access memory (hereinafter referred to as dynamic memory) with a megabit class storage capacity, the area per semiconductor memory element (hereinafter referred to as memory) has become smaller as the number of elements increases. It's here. As a result, in order to secure the capacity of memory cells, instead of the conventional Brehner capacitor (Brehner capacitive element) formed on the surface of the substrate, polycrystalline silicon was used as one electrode, making use of the large step difference on the semiconductor substrate. Stacked capacitors in which a capacitive insulating film is formed on polycrystalline silicon are being used.

A conventional method for manufacturing a memory element used in a semiconductor memory device or the like will be described below with reference to step-by-step cross-sectional views of FIGS. 4(a) and 4(b). The steps will be explained below in order.

A LOGO3 oxide film 12 is formed on the P-type semiconductor substrate 1 by selective oxidation. Next, the P-type semiconductor substrate 31 is oxidized to form the gate oxide film 13. Thereafter, a polycrystalline silicon gate 14 is formed on the gate oxide film 13. next,
For example, the source/drain diffusion layer 15 is formed by ion-implanting arsenic. Furthermore, after forming a CVD oxide film 16 as an insulating film by vapor phase growth, the CVD oxide film is etched using a photoresist as a mask to form contact holes 17 at predetermined locations on the source/drain diffusion layer 15. After the formation, a polycrystalline silicon film 18 is formed by a vapor phase growth method, and phosphorus is thermally diffused into this polycrystalline silicon film 18 to increase its conductivity and serve as the lower electrode of the capacitive element.
Figure 4(a)).

A silicon nitride film is deposited on the surface of this polycrystalline silicon film 18 using a vapor phase growth method, and this silicon nitride film is further thermally oxidized to form a capacitor insulating film 20. A polycrystalline silicon film 21 is formed thereon by a vapor phase growth method, and phosphorus is thermally diffused into this polycrystalline silicon film 21 to increase its conductivity and serve as the other electrode of the capacitive element. A capacitive element is formed as described above (FIG. 4(b)).

Problems to be Solved by the Invention However, in the conventional manufacturing method described above, the capacitance of the capacitor is determined by the surface area of the polycrystalline silicon film 18, so as the memory cell area is reduced, the thickness of the polycrystalline silicon film 18 is reduced. By increasing the surface area, it is necessary to thicken it.

However, in this case, there is a problem in that after the capacitor element is formed, the step difference on the surface of the semiconductor substrate due to the thick polycrystalline silicon film 18 becomes large, making it difficult to form wiring for forming the semiconductor memory element.

The present invention solves the above-mentioned conventional problems, and aims to provide a method for manufacturing a capacitive element that increases memory cell capacity without increasing the level difference on the surface of a semiconductor substrate.

Means for Solving the Problems To achieve this object, the method for manufacturing a capacitive element of the present invention involves forming a polycrystalline silicon film on a semiconductor substrate, and then ionizing, for example, argon, arsenic, or silicon into the polycrystalline silicon film. It has a process of roughening the surface of polycrystalline silicon by heating. The method also includes a step of forming a polycrystalline silicon film on a semiconductor substrate, implanting ions of oxygen, argon, or arsenic, and then etching away the surface of the polycrystalline silicon film. 5. After forming a polycrystalline silicon film on a semiconductor substrate, oxygen ions are implanted, and then epitaxial silicon is selectively grown on the polycrystalline silicon film.

Operation When the means of the present invention is used, impurity elements are ion-implanted into the polycrystalline silicon film, so that the surface roughness of the polycrystalline silicon film increases and the surface area increases. As a result, the capacitance of the capacitive element can be increased.

Further, after ion-implanting an impurity element into the polycrystalline silicon film, the surface of the polycrystalline silicon film is etched away halfway, which increases the unevenness of the surface of the polycrystalline silicon film, thereby increasing the surface area and thus the capacitance of the capacitive element. Furthermore, after oxygen ions are implanted into the polycrystalline silicon film, silicon is selectively grown on the polycrystalline silicon film, which increases the unevenness of the surface of the polycrystalline silicon film, increasing the surface area and thus the capacitance of the capacitive element.

EXAMPLE Hereinafter, a first example of the method for manufacturing a capacitive element of the present invention will be described in detail using step-by-step cross-sectional views of FIGS. 1(a) to (C). LOC is formed on the P-type semiconductor substrate 11 by selective oxidation.
An O8 oxide film 12 is formed to perform element isolation. Next, the P-type semiconductor substrate 11 is oxidized to form a gate oxide film 13, and a polycrystalline silicon gate 14 is formed on the gate oxide film 13. Thereafter, source/drain diffusion layers 15 are formed by ion-implanting, for example, arsenic. Furthermore, after forming a CVD oxide film 16 as an insulating film by vapor phase growth, the CVD oxide film is etched using a photoresist as a mask, and contact holes 17 are formed at predetermined locations on the source/drain diffusion layer 15. After forming the polycrystalline silicon film 18, a polycrystalline silicon film 18 having a thickness of, for example, 4000 Å is formed by vapor phase growth, and the conductivity is increased by thermally diffusing phosphorus into the polycrystalline silicon film 18 (FIG. 1(a)). Argon, arsenic, or silicon is ion-implanted onto this polycrystalline silicon film 18 by, for example, 1×10! 67/, J is implanted to form an impurity implantation layer 19. At this time, fine irregularities occur on the surface of the impurity implanted layer 19 due to physical damage caused by the ion implantation (FIG. 1(b)). A capacitor insulating film 20 made of a silicon nitride film and a silicon oxide film is formed by vapor phase growth on the polycrystalline silicon film 18 (impurity injection layer 19) processed into the unevenness. A third polycrystalline silicon film 21 is formed thereon by a vapor phase growth method, and phosphorus is thermally diffused into this polycrystalline silicon film 21 to increase conductivity and serve as the other electrode of the capacitive element.A capacitive element is completed ( Figure 1 (C
)).

In the case of the first embodiment according to the present invention, the surface area of the polycrystalline silicon film 18 is estimated from the electrical capacitance to be 10% when argon is implanted, 8% when arsenic is implanted, and 5% when silicon arsenic is implanted. increased. Along with this, the capacitance of capacitive elements has increased.

A second embodiment of the method for manufacturing a capacitive element of the present invention is shown in FIG.
This will be explained in detail using step-by-step sectional views of a) to (C).

Note that the polycrystalline silicon film 1 which is the lower electrode of the capacitive element
Since the steps up to the formation of 8 are completely the same as those in the first embodiment, a description of the steps will be omitted. After forming the polycrystalline silicon film 18, first, oxygen, argon, or arsenic is added, for example, lXl.
0''cd ions are implanted to form an impurity implanted layer 19 (FIG. 2(a)).

Thereafter, impurity injection layer 19 and polycrystalline silicon film 18 are etched halfway by performing a plasma etching technique using, for example, a gas containing SFs as a main component. At this time, the unevenness of the surface of the polycrystalline silicon film 18 increases significantly. This is because the distribution of impurities in the polycrystalline silicon film 18 (or impurity injection layer 19) is non-uniform, and the etching rate of the polycrystalline silicon film is significantly affected by the impurity concentration (see Fig. 2). (b)). After that, similarly to the first embodiment, a capacitive insulating film 20 and a polycrystalline silicon film 21 which will become the other electrode are formed to complete the capacitive element (see Figure (C)). In the case of the second embodiment of the present invention, the increase rate of the upper surface area of the polycrystalline silicon film 18 was 5 to 25%, depending on the impurity to be implanted and the amount of subsequent etching of the polycrystalline silicon film 18. . Along with this, the capacitance of capacitive elements has increased.

Note that the etching amount of the polycrystalline silicon film 18 is 20 to 2
An increase in the capacitance of the element was observed in the range of 000A.

A third embodiment of the method for manufacturing a capacitive element of the present invention is shown in FIG.
This will be explained in detail using step-by-step sectional views of a) to (C).

Note that the polycrystalline silicon film 1 which is the lower electrode of the capacitive element
8 is the same as that in the first embodiment, so a description of the process will be omitted. After forming the polycrystalline silicon film 18, first, oxygen ions, for example, lXl0"/cnf, are implanted, and then For example, heat treatment at 1000° C. is performed to form silicon oxide (SiO2) nuclei 22 on the surface of the polycrystalline silicon film 18, and then dry etching is used to uniformly remove the polycrystalline silicon film 18. On the surface of the crystalline silicon film 18, 5i02 nuclei 22 and exposed areas of polycrystalline silicon remain (FIG. 3(a)). After this, polycrystalline silicon is removed using dichlorosilane (S i H2Ce:) gas under reduced pressure. Eviquitous silicon 23 is selectively grown on the surface of the film 18 in areas other than the silicon oxide nuclei 22 to a thickness of, for example, 500 A. In this process, polycrystalline silicon grows in the exposed area of the polycrystalline silicon, forming a corrugated surface. A polycrystalline silicon film is formed (FIG. 3(b)).After this, as in the first embodiment, a capacitive insulating film 20 and a polycrystalline silicon film 21 which will become the other electrode are formed to complete the capacitive element. (3rd
Figure (C)).

In the case of the third embodiment according to the present invention, the increase rate of the upper surface area of the polycrystalline silicon film 18 was about 150%. As a result, the capacitance of the capacitive element also increased significantly.

Note that in all of the cases in this example, a polycrystalline silicon film was used as the upper electrode of the capacitive element, but it is clear that the same effects can be expected according to the present invention even when other conductive films such as silicide are used. .

Effects of the Invention As described above, according to the present invention, it is possible to increase the surface area without increasing the thickness of the polycrystalline silicon film that is the lower electrode of the capacitive element, and it is possible to increase the surface area of the semiconductor substrate. It is possible to prevent wiring formation problems caused by steps and to increase memory cell capacity. As a result, the memory cell area of the stacked capacitor can be further reduced while maintaining the element capacitance, which can greatly contribute to improving the degree of integration of dynamic memories.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a capacitive element according to an embodiment of the present invention in the manufacturing process, FIG. 2 is a cross-sectional view of a capacitive element according to another embodiment of the present invention in the manufacturing process, and FIG. FIGS. 4A and 4B are cross-sectional views in the order of manufacturing steps of a capacitive element showing another embodiment. FIGS. 11...P-type semiconductor substrate, 12...L
OCO8 oxide film, 13... Gate oxide film, 14
・・・・・・Polycrystalline silicon gate, 15・・・・・・
Source/drain diffusion layer, 16...CVD oxide film, 17...contact hole, 18...
...Polycrystalline silicon film, 19...Impurity injection layer, 20...Capacitive insulating film, 21...Polycrystalline silicon film, 22...Epitaxial silicon .

Claims (4)

[Claims] (1) A step of forming a polycrystalline silicon film on a semiconductor substrate, a step of ion-implanting an impurity element into the polycrystalline silicon film, a step of forming an insulating film on the surface of the polycrystalline silicon film, and a step of forming the insulating film on the surface of the polycrystalline silicon film. A method for manufacturing a capacitive element, comprising forming a conductive film on a film. (2) The impurity elements to be implanted are argon (Ar), arsenic (
The method for manufacturing a capacitive element according to claim 1, wherein the capacitive element is made of As) or silicon (Si). (3) forming a polycrystalline silicon film on a semiconductor substrate; ion-implanting an impurity element into the polycrystalline silicon film; and forming the polycrystalline silicon film to a thickness of 20 to 2000
A method for manufacturing a capacitive element, comprising: a step of removing by etching; a step of forming an insulating film on the surface of the polycrystalline silicon film; and forming a conductive film on the insulating film. (4) forming a polycrystalline silicon film on a semiconductor substrate; ion-implanting an impurity element into the polycrystalline silicon film; and selectively growing polycrystalline silicon on the polycrystalline silicon film; 1. A method of manufacturing a capacitive element, comprising: forming an insulating film on a surface of a polycrystalline silicon film; and forming a conductive film on the insulating film.