JPH03219663A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH03219663A JPH03219663A JP2015292A JP1529290A JPH03219663A JP H03219663 A JPH03219663 A JP H03219663A JP 2015292 A JP2015292 A JP 2015292A JP 1529290 A JP1529290 A JP 1529290A JP H03219663 A JPH03219663 A JP H03219663A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead frame
- semiconductor device
- wire bonding
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 238000007789 sealing Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の組立工程で用いられる半導体装置
用リードフレームの形状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the shape of a lead frame for a semiconductor device used in the assembly process of a semiconductor device.
（従来の技術）
半導体装置は集積回路から形成された半導体素子のポン
ディングパッドとこれに対応したリードフレームの各リ
ードとを接続し、ついで各リードの外側先端部以外の内
側部分をトランスファモールド等により樹脂で一体的に
成形する。そして成形された樹脂の外側において各リー
ドを切断し、必要に応じてリードを適宜折り曲げて半導
体装置を組立てている。第４図は従来の半導体装置完成
品の一例を示す斜視図である０図において、３は半導体
素子、２は半導体素子３を搭載するダイパッド、１は多
１５［設けられたリード、４は半導体素子３とこれに対
応するリードｌとを接続するワイヤー ５は半導体素子
３等を一体的に成形する封止樹脂である。ここで特にリ
ード１において、樹脂５の内部に埋まる部分をインナー
リードｌａ、封止樹脂５の外側に出る部分をアウターリ
ード１ｂと呼ぶことにする。(Prior Art) In a semiconductor device, a bonding pad of a semiconductor element formed from an integrated circuit is connected to each lead of a corresponding lead frame, and then the inner part of each lead other than the outer tip is formed by transfer molding or the like. It is integrally molded with resin. Then, each lead is cut on the outside of the molded resin, and the semiconductor device is assembled by appropriately bending the leads as necessary. FIG. 4 is a perspective view showing an example of a completed conventional semiconductor device. In FIG. A wire 5 connecting the element 3 and the corresponding lead 1 is a sealing resin that integrally molds the semiconductor element 3 and the like. In particular, in the lead 1, the portion buried inside the resin 5 will be referred to as an inner lead la, and the portion extending outside the sealing resin 5 will be referred to as an outer lead 1b.
実際の半導体装置組立作業においては、第３図に示すよ
うに前記ダイパッド２、リード１をダムバー６で連結し
、さらにその外周部に帯状枠７を設けて多連の繰返しパ
ターンとしたものを総称してリードフレームと呼ぶ、第
３図のリードフレームのうち半導体装ｒ・を搭載するダ
イパッド２、インナーリード１ａの部分の詳細図が第２
図である。In actual semiconductor device assembly work, the die pad 2 and leads 1 are connected by a dam bar 6 as shown in FIG. The second detailed view of the die pad 2 and inner lead 1a on which the semiconductor device r is mounted in the lead frame shown in FIG. 3, which is called a lead frame.
It is a diagram.
従来のリードフレームのインナーリード部は、第２図に
示すようにインナーリード１ａのワイヤーボンディング
するポイント９はダイパッド２の外周部からほぼ等距離
に一列にある形状のものが一般的に知られている。It is generally known that the inner lead portion of a conventional lead frame has a shape in which the wire bonding points 9 of the inner lead 1a are arranged in a line at approximately the same distance from the outer periphery of the die pad 2, as shown in FIG. There is.
上記半導体装置は最近の半導体素子の高集積化、高機能
化等のニーズと共に多ビン化する傾向にあるため、それ
に使用するリードフレームも多ビン化されると共に実装
密度を高くするためリード１のピッチが詰められ、アウ
ターリード１ｂのみならずインナーリード１ａのピッチ
も微細化されてきている。しかし従来のインナーリード
形状のままでピッチを小さくしていった場合、インナー
リード１本当りの幅が非常に狭くなることからリードフ
レームの加工上難しくなると同時に、半導体装置の組立
時にワイヤーボンディングする場合も狭いリードの上に
打つため、わずかな位置ずれでもワイヤーがインナーリ
ード１ａから外れてしまいワイヤーボンディング不良に
なり易くなる等の課題を有していた。The above-mentioned semiconductor devices tend to have multiple bins due to the recent needs for higher integration and higher functionality of semiconductor elements, so the lead frames used for them are also becoming more binned and the number of leads 1 is increased to increase the packaging density. The pitch has been reduced, and not only the pitch of the outer lead 1b but also the pitch of the inner lead 1a has become finer. However, if the pitch is reduced while maintaining the conventional inner lead shape, the width of each inner lead becomes extremely narrow, making it difficult to process the lead frame, and at the same time making it difficult to wire bond when assembling semiconductor devices. Also, since the wire is bonded onto a narrow lead, even a slight positional deviation causes the wire to come off from the inner lead 1a, resulting in a wire bonding failure.
そこで本発明はこのような課題を解決するためにリード
フレームのインナーリード１ａのワイヤーボンディング
するポイント９を交互に異なるように２列以上にするこ
とにより、ワイヤーボンディングするポイント９の部分
の幅を広くすることができ、安定的にワイヤーボンディ
ングができることを提供するものである。Therefore, in order to solve this problem, the present invention makes the wire bonding points 9 of the inner leads 1a of the lead frame in two or more rows in different rows, thereby increasing the width of the wire bonding points 9. This provides stable wire bonding.
上記課題を解決するため、本発明のリードフレームはイ
ンナーリードのワイヤーボンディングするポイントを交
互に異なるように２列以上にすることにより、インナー
リードのワイヤーボンディングする部分の幅を広くした
ことを特徴とする。In order to solve the above problems, the lead frame of the present invention is characterized in that the wire-bonding points of the inner leads are arranged in two or more rows so as to be alternately different, thereby increasing the width of the wire-bonding portion of the inner leads. do.
以下に本発明の実施例を図面にもとづいて説明する。基
本的な構成は従来の技術の例である第３図と同じである
が本発明の実施例の部分詳細図を第１図に示す。Embodiments of the present invention will be described below based on the drawings. Although the basic configuration is the same as that shown in FIG. 3, which is an example of the prior art, FIG. 1 shows a partially detailed view of an embodiment of the present invention.
第１図において、１ａはインナーリード、２は半導体素
子搭載部のダイパッドである。９はインナーリードのワ
イヤーボンディングポイントである。ワイヤーボンディ
ングポイント９の位置をダイパッド２の外周部からの距
離が交互に異なるようにした結果、隣１１士のワイヤー
ボンディングポイントが遠くなるため、インナーリード
１ａのワイヤーボンディングポイント９の部分の幅を広
くしたものである。In FIG. 1, 1a is an inner lead, and 2 is a die pad of a semiconductor element mounting portion. 9 is a wire bonding point of the inner lead. As a result of alternating the positions of the wire bonding points 9 at different distances from the outer periphery of the die pad 2, the adjacent wire bonding points become farther apart, so the width of the wire bonding point 9 of the inner lead 1a is increased. This is what I did.
以上述べたように本発明のリードフレームは、インナー
リードのワイヤーボンディングポイントの位置をダイパ
ッドの外周部からの距離が交互に異なるように２列以上
にすることにより、インナーリードのワイヤーボンディ
ングポイントの部分を広くすることができる。この結果
、半導体装置の組立時にワイヤーボンディングする際に
、わずかな位置ずれでもワイヤーがインナーリードから
外れてしまうような不良は少なくなり、安定的にワイヤ
ーボンディングを行なうことができる。こうして得られ
るワイヤーボンディングの安定性向上は半導体装置の組
立歩留りを向上させると共に多ビンの半導体装置の品質
、信頼性向上にも寄与する。As described above, in the lead frame of the present invention, the wire bonding points of the inner leads are arranged in two or more rows so that the distances from the outer periphery of the die pad are alternately different. can be made wider. As a result, when performing wire bonding during assembly of a semiconductor device, defects such as wires coming off from inner leads due to slight positional deviation are reduced, and wire bonding can be performed stably. The improved stability of wire bonding obtained in this manner not only improves the assembly yield of semiconductor devices but also contributes to improving the quality and reliability of multi-bin semiconductor devices.
第１図は本発明のリードフレームの実施例を示す部分詳
細平面図。
第２図は従来のリードフレームの実施例を示す部分詳細
平面図。
第３図は従来のリードフレームの実施例を示す斜視図。
第４図は従来の半導体装置完成品の実施例を示す斜視図
。
１・・・リード
１ａ・・・インナーリード
１ｂ・・・アウターリード
２・・・ダイパッド
３・・・半導体素子
４・・・ワイヤー
５・・・封止樹脂
６・・・ダムバー
７・・・帯状枠
９・・・インナーリードのワイヤーポンデイポイント
ング
以 上FIG. 1 is a partially detailed plan view showing an embodiment of the lead frame of the present invention. FIG. 2 is a partially detailed plan view showing an example of a conventional lead frame. FIG. 3 is a perspective view showing an example of a conventional lead frame. FIG. 4 is a perspective view showing an example of a conventional completed semiconductor device. 1...Lead 1a...Inner lead 1b...Outer lead 2...Die pad 3...Semiconductor element 4...Wire 5...Sealing resin 6...Dam bar 7...Strip shape Frame 9: Wire pond day pointing of inner lead or more
Claims (1)
枠より前記半導体素子搭載部近傍まで伸び複数連なるリ
ード、前記複数リードの中間に位置し前記複数リードを
各々連結するダムバー等から構成される半導体装置用リ
ードフレームにおいて、前記リードのワイヤーボンディ
ングするポイント（半導体素子搭載部からの距離）を２
列以上にすることにより、リードのワイヤーボンディン
グする部分の幅を広くしたことを特徴とする半導体装置
用リードフレーム。Consists of a rectangular band-shaped frame, a semiconductor element mounting part, a plurality of leads extending from the band-shaped frame to the vicinity of the semiconductor element mounting part, a dam bar located between the plurality of leads and connecting the plurality of leads, etc. In a lead frame for a semiconductor device, the wire bonding point of the lead (distance from the semiconductor element mounting part) is set to 2.
A lead frame for a semiconductor device, characterized in that the width of the wire bonding portion of the lead is widened by making the lead frame larger than one row.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015292A JPH03219663A (en) | 1990-01-25 | 1990-01-25 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015292A JPH03219663A (en) | 1990-01-25 | 1990-01-25 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03219663A true JPH03219663A (en) | 1991-09-27 |
Family
ID=11884764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015292A Pending JPH03219663A (en) | 1990-01-25 | 1990-01-25 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03219663A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005064076A (en) * | 2003-08-20 | 2005-03-10 | Sanyo Electric Co Ltd | Circuit device |
| JP2010074034A (en) * | 2008-09-22 | 2010-04-02 | Sanyo Electric Co Ltd | Lead frame, and resin sealed semiconductor device |
-
1990
- 1990-01-25 JP JP2015292A patent/JPH03219663A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005064076A (en) * | 2003-08-20 | 2005-03-10 | Sanyo Electric Co Ltd | Circuit device |
| JP2010074034A (en) * | 2008-09-22 | 2010-04-02 | Sanyo Electric Co Ltd | Lead frame, and resin sealed semiconductor device |
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