JPH03203886A - Oscillating circuit controller - Google Patents

Abstract

PURPOSE:To obtain an n-fold output frequency of a video frame frequency (FV) only with passage in two PLL circuits by setting the frequency division ratio of a frequency divider in accordance with the output frequency of a voltage controlled oscillator. CONSTITUTION:A frequency dividing circuit 6 is a circuit block to obtain one of plural frequency division ratios in accordance with a control signal S, and the frequency division ratio is set to 1/2<m>-fold value when sampling frequencies fs1=48kHz and fs2=44.1kHz are selected by a first selecting circuit 1, and it is set to 2/3.2<m>-fold value when fs3=32kHz is selected. Values (x) and (y) of the denominator of the frequency division ratio of a third frequency divider 11 are so set that one frequency is selected which is 30-K-fold frequency of a n.Fv-fold output frequency C obtained by a second PLL circuit 12 and is a common measure between the output frequency C and the 2<m>.fs-fold frequency of a voltage controlled oscillator output A of a first PLL circuit 2. Thus, the Fv-fold output frequency of the NTSC color frame frequency synchronized with the master clock of a PCM audio system is obtained only with passage in two PLL circuits.

Description

Detailed Description of the Invention [Industrial Applicability] The present invention provides an oscillation system capable of synchronizing three types of sampling frequencies fs output from a PCM audio device and an NTSC color frame frequency Fv=29.97Hz. This invention relates to a circuit control device.

[Conventional technology]

For example, digital audio tape recorder (DAT)
The system frequency is 512Fs (2m・fs:m
is an integer: m = 9) Two frequencies are required at minimum: the double frequency and 9.408MHz, which is necessary for DAT recording and playback. When it is necessary to playback in synchronization with video, SEMPTE time code is generally used as a time management means, so a frequency n times Fv (n is a natural number) is also required.

At least these three types of frequencies are useful for systems that require vari-pitch playback function or external clock synchronization.
It is necessary to synchronize 9.408 MHz with the frequency n times Fv with respect to the (2m-fs) times frequency of the CM audio system master clock.

FIG. 3 shows the configuration of a conventional oscillation circuit control device. In Figure 3, (21) has three types of sampling frequencies fsl = 48kHz 1fs2 = 44.1kHz
z, fs3=32kHz can be switched by a control signal (S'), (22) is a PCM generation PLL circuit, (24) is a DAT master clock generation PLL circuit, (26) is an NTSC color frame generation PLL circuit ,
(23) and (25) are frequency dividers that can obtain one of a plurality of frequency division ratios according to the control signal (S), and are fs1, fs2, fs3 output from the PCM audio device.
is switched and selected by the control signal (S') in the selection circuit (21) and input to the PLL circuit (22).

One of the output frequencies of the voltage controlled oscillator (not shown) in the PLL circuit (22) is supplied to the signal processing means, A/D converter, and D/A converter as the master clock frequency of the PCM audio system. The other one is to obtain the 9.408MHz output frequency required for DAT recording and playback.
It is input to the PLL circuit (24) via the frequency divider (23). The voltage controlled oscillator (
The output frequency of the frequency divider (2
5) to the PLL circuit (2B).

For example, as shown in FIG. 2, the PLL circuit (22) (2G) is a phase comparison circuit (27) that uses the output frequency (D) of the selection circuit (21) as a reference manual and compares the phase with a reference frequency (E). , a low-pass filter (28) that smoothes the difference signal of the phase comparison circuit (27), a voltage-controlled oscillator (30) that generates a frequency according to the output voltage of the low-pass filter (28), and a voltage-controlled oscillator (30). The output (A゛) of the frequency is (2m-fs)
9) has a basic configuration in which the frequency division ratio is set to (1/2m) times.

The operation of the conventional oscillation circuit control device configured as described above will be explained below. Three types of PCM audio sampling frequencies fsl=48kHz 1
fs2=44.1kHz 1fs3=32kHz is input to the selection circuit (21), and its output is the control signal (S゛)
Then, one of fsl, fs2, or fs3 is selected. Therefore, for example, if fjl is selected by the control signal (S'), 48kHz is PL
It will be input to the L circuit (22).

Now, if fsl is input to the PLL circuit (22), the output of the frequency divider (29) shown in FIG. 2 constitutes a closed loop as the reference frequency (E) of the phase comparison circuit (27),
The output frequency (A') of the voltage controlled oscillator (30) of the PLL circuit (22) is supplied to the signal processing means, A/D converter, and D/A converter as the master clock frequency of the PCM audio system.

9.408MH required for recording and reproducing the DAT shown in Figure 3
In systems that require a vari-pitch playback function or external clock synchronization, the output frequency (F) of z must be set to (2) in order to synchronize with the sampling frequency fs of the PCM audio system.
A PLL circuit (24) that generates a frequency of 9.408 MHz from a frequency multiplied by (m-fs) is required, and its configuration is the same as that of the PLL circuit (22), and the reference input frequency (D) shown in Fig. 2 is 48 kHz. The only basic differences are the characteristics of the low-pass filter (28), the output frequency of the voltage-controlled oscillator (30), and the frequency division ratio of the frequency divider (2B).

The output (A゛) of the PLL circuit (22) and the PLL circuit (24)
) can be selected by the control signal (S') as described above, and its output frequency is set to a frequency that can generate 9.408 MHz. . Specifically, the output frequency of this frequency divider (23) is fsl = 48kHz, fs3 = 44.1kHz
In the case of 192kHz1fs2 =44. In the case of IkHz, the frequency division ratio (1/32.4) and (+/32.3), which is 235.2kHz, is the respective control signal (S'
) is set.

At the same time, the setting value of the frequency divider of the PLL circuit (24) is also fsl=
48kHz, fs3 = 32kHz, (1/
49) Set times, (■/40) times. The output (F) of the PLL circuit (24) is controlled by the control signal (
Even if S") is switched, a frequency of 9.408 MHz is obtained.

Furthermore, Fv synchronized with the fs frequency of PCM audio system
In order to obtain the n-times frequency (C') of
Frequency divider (25) from 9.408MHz independent of S゛)
PL that divides the frequency by and uses that frequency as the reference input.
When generated by the L circuit (26), the n-times frequency (C') of Fv is obtained at the output of the PLL circuit (26) in synchronization with the fs frequency of the PCM audio system.

In addition, Fv is (30・(1000/1001)) =
Since it is 29.97 -------Hz, it is n times (30
・(1000/1001) ) Hz output frequency (C
When trying to obtain 1, the frequency division ratio of the frequency divider (25) is set to ((8·+001)15n) times.

[Problem to be solved by the invention]

However, in the conventional configuration as described above, at least three PLL circuits ( 22)(24)(
2G), and depending on the performance of the PLL circuit, three types of frequency jitter are integrated, and SEMPTE
There was a problem in that the time code output became large.

The present invention can obtain at least three times Fv synchronized with fs from three types of fs frequency input of PCM audio.
Compared to the conventional example which goes through two PLL circuits, two PLL circuits are used.
It is an object of the present invention to provide a control device for an oscillation circuit that can obtain an output frequency n times the video frame frequency Fv just by passing through the circuit.

[Means to solve the problem]

In order to achieve the above object, the oscillation circuit control device of the present invention divides the frequency of a frequency division block of a PLL circuit for frequency multiplication using three types of sampling frequencies of PCM audio selected by a control signal as input signals. ratio fsl=48kHz
z, fs2=44.1kHz, (+/2”
) times, and when fs3 = 32kHz, ((2/
3) - 2m) times, and in the case of fs11fs2, connect directly between the output frequency of the voltage controlled oscillator of the PLL circuit and the input of a selection circuit that switches the output of this voltage controlled oscillator according to the sampling frequency. , f
In the case of s3, a first frequency divider of 2/31 times is provided.

a second frequency divider capable of switching the output frequency of the voltage controlled oscillator of the PLL circuit according to the sampling frequency;
The output of the frequency divider is set to the NTSC color frame frequency Fv=2
A third frequency divider set according to 9.91Hz and a second P for frequency multiplication that receives the divided output of this third frequency divider as input.
LL circuit is provided, and the output of the second PLL circuit is (n −F
v) In order to obtain twice the frequency, the output frequency of the second frequency divider is (30·K) times the frequency of (n·Fv) times, and (2m-fs) of the voltage-controlled oscillator output of the first PLL circuit.
) The frequency division ratio of the second frequency divider is switched according to fsl and fs2 so as to select one frequency that satisfies the condition of being a common divisor of the double frequency.

[For production]

With the above configuration, the present invention provides an output frequency n times the NTSC color frame frequency Fv synchronized with the PCM audio sampling frequency fs, when the sampling frequency fs=48kHz (fs1) or 44.1k.
When H2 (fs2) is selected by the first selection circuit with each control signal, the voltage controlled oscillation of the first PLL circuit! Output force (2m-fs1) times 4:! When the frequency division ratio of the (2m-fs2) times ninal frequency divider circuit is set to (+/2m) times and fs3=32k)lz is selected, the output power of the voltage controlled oscillator ((3/2) The frequency division ratio of the 2rn-fS1) times ninal frequency divider circuit is (2/3) ・(1/2m)
In addition, the output of the voltage controlled oscillator is set to three types of f.
fsl between the inputs of the selection circuits, which can each be switched according to s.
or directly connected if fs2 is selected, fs3
is selected, the second selection circuit is supplied with an output frequency (2m-fs) times by the control signal by interposing the (2/3) times the first frequency divider. Fourth, a second frequency divider capable of switching the output frequency of the voltage controlled oscillator according to fs11fs2, and a second frequency divider to obtain a frequency (n-Fv) times the output of the second PLL circuit whose output is input. The second PLL circuit selects one frequency that satisfies the condition that the output frequency of the frequency divider is (30-K) times the frequency of (n-Fv) times and is a common divisor of the output of the first PLL circuit.
By switching the frequency division ratio of the frequency divider using a control signal, it is possible to obtain an output frequency n times the NTSC color frame frequency Fv synchronized with the PCM audio system frequency Fs.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a control device for an oscillation circuit according to this embodiment. In FIG. 1, this control device has three types of sampling frequencies output from the PCM audio device: fsl=48kHz, 1fs2=4
A first selection circuit (1) whose input is 4.1kHz 1fs3=32kHz can be switched by a control signal (S), and a first PLL circuit (2) for frequency multiplication whose output is used as a reference input are provided. ing.

The first PLL circuit (2) includes a phase comparison circuit (3) that compares the phases of the output frequency of the first selection circuit (1) and a reference frequency and outputs a difference signal, and a low-pass circuit that smooths the difference signal. A filter (4), a voltage controlled oscillator (5) that generates a frequency according to the output voltage of the low pass filter (4), and a frequency dividing circuit (6) that divides the output frequency of the voltage controlled oscillator (5). A closed loop is constructed in which the frequency divided output of the frequency dividing circuit (8) is used as the reference frequency of the phase comparator circuit (3).

The frequency dividing circuit (B) is a circuit block that can obtain one of a plurality of frequency division ratios according to the control signal (S), and the frequency division ratio is selected by the first selection circuit (1) as fsl or fs2. If fs3 is selected, it is set to (1/2 m) times, and if fs3 is selected, it is set to ((2/3) 2 m 1 times.

Therefore, the voltage controlled oscillator output (G) has fsl,
fs2 (1) case C(2m-fs1) times, (2m-f
s2) times the output frequency is obtained, and in the case of fs3, ((
3/2) 2"-fsl> times the output frequency is obtained.

(7) is a second selection circuit which can switch the output of the voltage controlled oscillator (5) by a control signal (S) according to three types of sampling frequencies fsl - fs3;
The output frequency obtained from the LL circuit (2) is input,
A first frequency divider (8) that is directly connected for fsl and fs2, and set to a division ratio of (2/3) times for fs3.
The signal is inputted to the second selection circuit (7) via.

Therefore, the output when fs3 is selected is (2
m-fs) times the frequency is the output (A) of the second selection circuit (7).
) and is supplied to signal processing, A/D converters, and D/A converters as the master clock frequency of the PCM audio system.

(9) is the output frequency of the voltage controlled oscillator (5) fs1,
A second frequency divider that can be switched according to fs2, in which the voltage controlled oscillator output (G) is manually input, and the frequency division ratio in the case of fsl is (1/x) times - and the division ratio in the case of fs2 is The circumference ratio is (
1/y) times, and its output (B) is sent to the NT via the third selection circuit (10) which is switched by the control signal (S).
SC color frame frequency Fv== 29.9711z
The signal is input to a third frequency divider (11) set to a frequency division ratio according to (n −F
v) Obtain twice the output frequency (C).

At this time, the value of X+y, which is the denominator of the frequency division ratio in the third frequency divider (11), is (30 - K) times the output frequency (C) and the frequency that is (2" - fs) times the voltage-controlled oscillator output (A) of the first PLL circuit (2). is set to

Each frequency division ratio set under the above conditions is (2m-fs) times the PCM audio system or (2m・fs2).
) times the output frequency (G) is the control signal (S), and a certain specific frequency can be obtained as the output (B) regardless of fs.

As a specific example, if the output (A) is 512Fs, the output (
G) is the sampling frequency fsl = 48kHz,
When fs3=32kHz, 24.57 [iMHz,
22.5792MH when fs2=44.1kHz
z is obtained. NTSC color frame frequency Fv n
If the multiplied output frequency is 29.97.
Hz is obtained.

Furthermore, to obtain the n-times frequency (C) of the NTSC color frame frequency Fv, the output (B) is divided by (1/
If the frequency is divided by 1001) and generated by a second PLL circuit (12) with a configuration similar to that of the PLL circuit shown in Figure 2, which uses that frequency as a reference input, the output of the second PLL circuit (12) will be is the NTSC color frame frequency Fv
is obtained in synchronization with the sampling frequency fs of the PCM audio system.

[Effects of the Invention] As explained above, according to the present invention, when obtaining an output frequency n times the NTSC color frame frequency Fv synchronized with the PCM audio system master clock, in the conventional example, three PLL circuits are used. Compared to the device, 2
This can be achieved by simply passing through PLL circuits, and the SE for the NTSC color frame frequency Fv
This has the excellent effect of reducing the output of MPTE time code.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a control device for an oscillation circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a PLL circuit configuration, and FIG. 3 is a block diagram showing a control device for a conventional oscillation circuit. FIG. (1)...First selection circuit, (2)...First PLL circuit, (3)...Phase comparison circuit, (4)...Low pass filter, (5)...Voltage controlled oscillator, (6)...
Frequency divider circuit, (7)...second selection circuit, (8)...first frequency divider, (3)...second frequency divider, (11)...third frequency divider , (12)...second PLL circuit, (S)...
・Sampling frequency switching control signal. Figure 2

Claims (1)

[Claims] Three types of sampling frequencies fs1 of PCM audio
=48kHz, fs2=44.1kHz, fs3=32
Sampling frequency switching control signal (
A first selection circuit that can switch one of the three sampling frequencies using a control signal (hereinafter abbreviated as a control signal), and a phase comparison circuit that compares the phase of the output frequency of this first selection circuit and a reference frequency. The difference signal is smoothed by a low-pass filter, a voltage-controlled oscillator generates a frequency corresponding to the output voltage of this low-pass filter, and the output frequency of this voltage-controlled oscillator is divided by a frequency dividing circuit to generate the divided output. a first PLL circuit for frequency multiplication configured to form a closed loop using as a reference frequency of the phase comparison circuit;
and a second selection circuit capable of switching the output of the voltage controlled oscillator according to the three types of sampling frequencies, and when fs1 or fs2 is selected by the first selection circuit, the output frequency of the voltage controlled oscillator is changed. is (2^m・fs
1) If fs3 is selected, the output frequency of the voltage controlled oscillator is {
(3/2)・2^m・fs1} times the frequency division ratio of the frequency dividing circuit is set to (2/3)・(1/2^m) times, and the output of the voltage controlled oscillator A first frequency divider that directly connects the frequency and the input of the second selection circuit when fs1 and fs2 are selected, and sets a frequency division ratio of (2/3) times when fs3 is selected. Via (2^m・f
s) a second frequency divider configured to supply a double frequency to a second selection circuit and capable of switching the output frequency of the voltage controlled oscillator according to fs1 and fs2; The output of NTSC color frame frequency Fv = 29.97Hz
A third frequency divider set to a frequency division ratio according to
In order to obtain a frequency that is n・Fv) times, the output frequency of the second frequency divider is (30・K) times the frequency that is (n・Fv) times and is a common divisor of the output of the first PLL circuit. 1. A control device for an oscillation circuit, characterized in that the frequency division ratio of the second frequency divider is switched by a control signal so as to select one satisfying frequency.