JPS5881337A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To simplify constitution by switching and using variable frequency dividers and a phase comparator in common for phase-lock loops. CONSTITUTION:A microprocessor performs control on the basis of clock pulses from a reference oscillator FO. A selector SEL and switch SW operate synchronously and frequency division ratios of variable frequency dividers VD1 and VD2 are changed synchronously. When a voltage-controlled oscillator VO1 is selected, the output signal of a phase comparator CP is supplied to a holding circuit HD1. As a result, the 1st loop is set up. Even when the selector SEL, etc., is switched synchronizing with the clock to select a voltage-controlled oscillator VO2, the holding circuit HD1 holds the last voltage to carry on oscillation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency synthesizer that uses a common reference oscillator and generates multiple frequencies simultaneously.

Such frequency synthesizers are used when simultaneously obtaining a transmitting frequency source and a receiving side local oscillation frequency source for a wireless transceiver, and conventionally, the configuration shown in the block diagram in Figure 1 has generally been adopted. In other words, the output of a reference oscillator FO having a stable oscillation frequency, such as a crystal oscillator, is divided into frequencies by frequency dividers DVl and DVx, and comparators cp, , cp, using phase comparators are used. On the other hand, the voltage controlled oscillator (hereinafter referred to as VCO) VO+, Vow+7) output is sent to a variable division divider such as a programmable division divider VDI,
vD, divide the frequency by υ and send these outputs to the comparator CPI
, CPz, and a comparator CPI according to the phase difference between each output.

Each output of Cps is passed through a loop filter LF such as a low-frequency r-wave filter.
VCO・vO as a control voltage after passing through I-LFl
l, given to vO mushroom, comparator C20 to vCO・VOs
A phase-locked circuit based on comparators Ch to vCO@vO is connected to a frequency obtained from a common reference oscillator FO by a divider DV.

The frequency divided by Dv mushroom and the variable frequency divider VDI
, vDx, and the reference oscillator FO
After obtaining a stable output frequency fl*fl synchronized with the output of the variable frequency divider VDI, vp, the control signal C8
Since the frequency division ratio is determined according to t and C8, the output frequency fl + f is individually determined according to these frequency division ratios.

However, the output frequency fl+f! If the frequency of Since a frequency divider and a frequency divider with a low response speed must be used in combination, the structure becomes complicated and the whole system becomes expensive and large.

The purpose of the engine is to fundamentally solve the drawbacks of the conventional system, and the comparator and variable frequency divider are shared by each phase locking circuit, and the control voltage for the VCO is held by a hold circuit. The present invention provides an extremely effective frequency synthesizer that can be simplified in configuration, and at the same time made compact and inexpensive by sequentially switching and using the shared portion for each phase-locked circuit.

Hereinafter, the present invention will be explained in detail with reference to the block diagram of FIG. 2 showing an embodiment.

In the same figure, each phase-locked circuit is a hold circuit) I
D, , HD, , loop filters LFt, LF, and VcO・VOt, VOl are each individually configured, whereas the reference oscillator Fo, variable divider VD, , VD, and comparator CP are common. These are sequentially switched and connected to each phase synchronized circuit by a selector SEL and a switch SW such as a high frequency switch.

In addition, a control unit CT such as a microprocessor performs control operations based on clock pulses from a clock generator CLG that frequency-divides the output of the reference oscillator FO. operate in synchronization and, in accordance with these operations, the variable branchers VD, , VD.

The frequency division ratio of is also controlled.

Therefore, when the switch SW selects the output of vCO·VOl and the selector SEL distributes the output of the comparator CP to the hold circuit MDI, the variable frequency divider VD1. The frequency division ratio of VD is determined, the phases of the output of the variable divider MDI and the output of the variable divider VDs are compared by the comparator CP, and an output corresponding to the frequency and phase error is given to the hold circuit HD. Therefore, this output is held by the hold circuit HDt and is applied to the VCO/VOI as a control voltage via the loop filter LFs.

Furthermore, when the switch SW selects the output of vCO-vOl and the selector SEL distributes the output of the comparator CP to the hold circuit HDI, the division ratio of the variable dividers VD, VDI is adjusted according to the output frequency fm. The phase of the output of the variable divider MDI and the output of the variable divider vD1 is compared by the comparator CPK, and the output corresponding to the frequency and phase error is sent to the hold circuit HD! Since this output is held by the hold circuit HD, it is passed through the loop filter LFI and used as a control voltage.

・Given to VD.

Therefore, by sequentially repeating the above operations at a predetermined period, vco-vOl, vol gradually become synchronized, resulting in stable output frequencies f, , f.

, and if it becomes an asynchronous state, the asynchronous state is corrected as the operation is repeated.

However, depending on the conditions, the variable frequency divider VDl may be a fixed divider or may be omitted. The same effect can be achieved even if the variable divider VDl is a multi-stage one. A dedicated control circuit with multiple configurations may also be used.

Also, hold circuit HD! , HDt may be a sample hold circuit using a capacitor or the like, but
The present invention may be modified in various ways by incorporating loop filters LF, LF, and LF.

Claims (1)

[Claims] a plurality of phase-locked circuits each having a voltage controlled oscillator and using a common reference oscillator; a switch that sequentially selects the output of each of the voltage controlled oscillators; and a variable division divider that divides the selected output of the switch. a comparator that performs a phase comparison between the output of the variable splitter and the output of the reference oscillator; a selector that distributes the output of the comparator in synchronization with the operation of the switch; A hold circuit provided for each of the phase synchronized circuits which holds and then applies a control voltage to the voltage controlled oscillator via a loop filter, and a hold circuit which operates based on the output of the reference oscillator and controls the switch, variable branching unit and selector. A frequency synthesizer having four characteristics: a control section for controlling the frequency synthesizer;