JPH03195113A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To stabilize the gate voltage of an FET for data holding against temperature fluctuation, to enlarge a noise margin and to make a characteristic stable by inserting a level shift element between each source of a current source FET and a power source. CONSTITUTION:In the flip-flop circuit of SCFL(Source Coupled FET Logic) configuration, between the sources of FET Q10 and Q11 to be the current sources of source follower and the power source, level shift elements D3 and D4 are provided to be the same as level shift elements D1 and D2 used for returning signals to FET Q3 and Q4 for data holding. Thus, the characteristic of the circuit caused by a temperature characteristic is compensated and the characteristic is practically stabilized against the temperature fluctuation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to flip-flop circuits. More specifically, the present invention relates to a novel configuration of a flip-flop circuit, which is one of the components of a semiconductor integrated circuit configured with FETs.

SCF L is a differential logic gate circuit using conventional technology FET.
(Source Coupled FET Lo
A flip-flop circuit can be constructed using .gic) as a basic element. Typical examples of such flip-flop circuits include IEE Trans,
Electron.

Devices, Vol, ED-32Na3 pp, 1
114-1118 June 1985.

The circuit shown in FIG. 2 is also a configuration example of a flip-flop circuit based on an SCFL circuit.

That is, this circuit includes FETQ, which constitutes a differential input circuit.
and Q2, FETs QI and Q2 for data retention, Q5 and Q6 forming a clock signal input circuit, source follower FETs Q8 and Q3, etc.
This is a differential circuit with an SCFL configuration made up of ETs.

Note that FETQ, .

In order to achieve high-speed operation while maintaining sufficient operating margin in such flip-flop circuits,
In particular, it is desired that FETQ, -Q6 operate in the saturation region. That is, in this circuit, the drain-gate voltage V of FETQ+ to Q6. In other words, the lever, CVnc>Vth (Vth
is the threshold voltage)] It is necessary to design the circuit so that the following condition is satisfied.

Therefore, in such flip-flop circuits, generally,
Level conversion elements D1 and D2 are inserted between the sources of source follower FETs Qs and Q, and the gates of data holding FETs Q, , Q, respectively.

Problems to be Solved by the Invention However, diodes, which are typical as the level conversion elements D1 and D2, have temperature characteristics, and the amount of level shift changes due to temperature fluctuations, causing the drains of FETs Q3 and Q4 to change.
There is a problem that the gate voltage VDG decreases.

Therefore, the present invention solves the above-mentioned problems of the prior art, and eliminates characteristic fluctuations caused by temperature characteristics of the level conversion element.
Its purpose is to provide a novel flip-flop circuit.

According to a means for solving the problem, that is, according to the present invention, the sources are commonly connected to each other,
a pair of first and second FETs whose gates are connected to a non-inverting input and an inverting input of a data signal, respectively, whose sources are commonly connected to each other, and whose drain is connected to the drain of the first or second FET; a pair of third and fourth FETs, a gate connected to the drain of the third FET, a source connected to the gate of the third FET via a first level shift element, a source of the third FET; a fifth FET operating as a follower; a gate connected to the drain of the fourth FET; and a second FET connected to the gate of the fourth FET;
The source is connected via a level shift element, and the fourth F
a sixth FET that operates as a source follower of the ET;
A seventh FET whose drain is connected to the source of the fifth FET through the first level shift element and whose source is connected to the power supply to function as a current source; and a seventh FET which functions as a current source through the second level shift element; An SCFL-configured flip-flop circuit comprising an eighth FET whose drain is connected to the source of the seventh FET and whose source is connected to the power source to function as a current source, the flip-flop circuit further comprising an eighth FET connected between the source of the seventh FET and the power source. a third level shift element, and the eighth FE.
a fourth level shift element connected between the source of T and the power supply, the third and fourth level shift elements having the same characteristics as the first and second level shift elements; A flip-flop circuit is provided.

Operation The circuit according to the present invention provides a level shift function that is used for returning a signal to a data holding FET between the source of an FET that serves as a current source of a source follower and a power supply in a flip-flop circuit having an SCFL configuration. Its main feature is that it is equipped with the same level shift element.

Therefore, in this flip-flop circuit, circuit characteristics caused by temperature characteristics are compensated for by the level shift element connected to the gate of the data holding FET and the level shift element connected to the source of the source follower FET. Therefore, the characteristics are substantially stable against temperature fluctuations.

Hereinafter, the present invention will be described in more detail with reference to the drawings, but the following disclosure is only one embodiment of the present invention, and does not limit the technical scope of the present invention in any way.

Embodiment FIG. 1 is a circuit diagram showing a specific example of the configuration of a flip-flop circuit according to the present invention.

The circuit shown in FIG. 1 is different from the conventional flip-flop circuit shown in FIG.
Level shift elements D3 and Q4 are inserted between the sources of FETQ and FETQ, and the power supply. The level shift elements D3 and Q4 used here are source follower FETQ.

A level shift element connected to the sources of and Q, and the same element as Q2 is used. In particular one or more diodes can be used.

In the flip-flop circuit configured as above, the level conversion element is now -1.2mV/
Considering that a Schottky barrier diode having a temperature characteristic of t is used, the level conversion amount of each level shift element D+, Q2Ds, and Q4 decreases as the temperature increases. Therefore, the source follower FETs Qs and Q.

In the level conversion elements D1 and Q2 connected to the sources of , the potential on the cathode side increases.

Therefore, the gate voltage applied to the gates of data holding FETs Q3 and Q4 increases.

On the other hand, at the same time, the source potentials of current sources FETQlo and Qll decrease due to the action of level shift elements D3 and D40, and the gate-source voltage v9S of each FETQ, oSQ, . increases. Therefore, FETQ,,S
The current flowing through Q increases, and the gate-source voltage Vgs of FETs Qa and Q increases.

Such an increase in the gate-source voltage V9m of FETQs and Q9 is due to the increase in the gate-source voltage V9m of FETQs and Q9.
It acts to lower the gate voltage of 4.

The actions of these level shift elements D1 and Q2 and the actions of level shift elements RI and RI are FETQ,
, Qs, QIO, and Q, if their gate widths are equal, they cancel each other out, so in this circuit, the gate voltages of FETs Q3 and Q4 are held substantially constant regardless of temperature variations.

As described in detail, although the flip-flop circuit according to the present invention uses a level shift element having a temperature characteristic such as a diode, the gate voltage of the data holding FET changes with respect to temperature fluctuations. Since it is stable, it can be widely used as a flip-flop circuit with a large noise margin and stable characteristics, and as one of the basic blocks of SCFL-configured digital ICs such as logic game ICs.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a specific configuration example of a flip-flop circuit constructed according to the present invention, and FIG. 2 is a typical configuration of a conventional flip-flop circuit corresponding to the circuit shown in FIG. FIG. 2 is a circuit diagram showing an example. [Main reference symbols] Qa, Qa, Q3, Qa, Qs, Q, , Q,
,Q, ,Q, ,Q, ,. Q...FET. D11D2, Ds,

Claims (1)

[Scope of Claims] A pair of first and second FETs whose sources are commonly connected to each other and whose gates are connected to a non-inverting input and an inverting input of a data signal, respectively; first or second FE
a pair of third and fourth FETs whose drains are connected to the drain of the third FET, and a gate of which is connected to the drain of the third FET;
a fifth FET whose source is connected to the gate of the ET via the first level shift element and which operates as a source follower of the third FET; a fifth FET whose gate is connected to the drain of the fourth FET and whose source is connected to the gate of the fourth FET; , a sixth FET whose source is connected via the second level shift element and operates as a source follower of the fourth FET, and whose drain is connected to the source of the fifth FET via the first level shift element, a seventh FET whose source is connected to the power source and functions as a current source; and a seventh FET whose drain is connected to the source of the sixth FET via the second level shift element and whose source is connected to the power source and functions as a current source. 8FET
A flip-flop circuit having an SCFL configuration, further comprising: a third level shift element connected between the source of the seventh FET and the power supply; and a third level shift element connected between the source of the eighth FET and the power supply. a fourth level shift element, wherein the third and fourth level shift elements are level shift elements having the same characteristics as the first and second level shift elements. .