JPH03192729A - Manufacture of thin film transistor array of active matrix display - Google Patents

Abstract

PURPOSE:To enable an active matrix display in high precision and stable display quality to be manufactured by a method wherein semiconductor films and a transparent conductive film are patterned by selfmatching process using the rear exposure while a drain wiring and a source wiring are liftoff formed using a resist for the display electrode patterning process. CONSTITUTION:Etching resists of semiconductor films S4, S5 and a transparent conductive film C6 are formed in self-aligned manner in offset state on a gate wiring provided with a gate electrode 2 using the rear exposure with the semiconductor films S4, S5 and the transparent conductive film C6 respectively formed on the gate electrode 2 and the gate wiring. Furthermore, a drain wiring provided with a drain electrode part 8 as well as a source electrode wiring are liftoff formed using the etching resist of the transparent conductive film C6 further exposure-processed. Through these procedures, respective patterns can be formed by etching and liftoff processes using substantially the same resist so that the highly precise display electrode 6, the drain wiring and a source electrode wiring subjected to no adverse effect of a photomask and an exposure device may be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a thin film transistor array for an active matrix display device.

(b) Conventional technology In recent years, active matrix display devices have been developed in which thin film transistors (hereinafter referred to as TPTs) functioning as switching transistors are connected to each display electrode of a large number of pixels arranged in a matrix, and these TPTs are used as drive circuits. ing. This device supplies pixel information to each display electrode via TPT, and optical changes occur in the liquid crystal layer, EL layer, or EC layer provided on the display electrode by electric field, current, or power according to this pixel information. [Japanese Patent Publication No. 62-6674].

In particular, active matrix liquid crystal display devices using the above-mentioned liquid crystal layer are currently attracting attention as displays for portable TVs.

FIG. 5(a) shows a plan view of each pixel of a TFT array in a conventional active matrix liquid crystal display device.
FIG. 5B shows a cross-sectional view taken along line A-A of the TFT position.

These TPTs in the same figure are attached to one insulating substrate 1 of the liquid crystal cell.
An ohmic contact is made to the gate formed on the top and forming a part of the gate line 20 as the pole 2, the gate insulating film 3 provided on the entire surface of the substrate, the localized semiconductor film 4, and the source and drain positions of the semiconductor film 4, respectively. It has a so-called inverted stagger type structure consisting of a stack of impurity semiconductor films 5, 5, a source electrode 7, and a drain electrode 8, and a display electrode 6 for each pixel is connected to the source electrode 7.

TP of such a conventional active matrix display device
The method for manufacturing the T-array will be outlined below in order of steps.

(1) Step of forming a metal film for wiring on the insulating substrate 1 and forming a gate line 20 including the gate electrode 2 using an otomask and a photoresist.

(2) Using a P-CVD device or the like, the gate insulating film 3,
Step of sequentially forming a non-single crystal semiconductor film 4 and a non-single crystal impurity semiconductor film 5.

(3) A step of etching the semiconductor film 4 and the impurity semiconductor film 5 using a photomask and a photoresist.

(4) A step of forming a transparent conductive film and forming display electrodes 6 using an oto mask and a photoresist.

(5) A step of forming a metal film for wiring and forming a drain line 8o including a source electrode 7 and a drain electrode 8 using a photomask and a photoresist.

(6) Etching the impurity semiconductor film 5 at the channel position between the picture electrodes 7 and 8.

(c) Problems to be Solved by the Invention According to the method of manufacturing a TPT array for an active matrix display device as described above, the processing accuracy of the TPT pattern is determined by the capabilities of the photomask and the exposure device.

Generally, the pitch error of the current 7 otomasks is ±1μm,
! Since the alignment error of the optical device is ±1 μm, according to the conventional manufacturing method described above, the alignment error is ±2 μm, that is, 0 to 0.
A shift in the pattern position of 4 μm occurred, and a pattern design with sufficient margin to account for this position shift was required.

Therefore, when manufacturing a display device with a high pixel density, such as an ultra-high-definition liquid crystal display device compatible with high-definition television, with a pixel size of about 30 μm to 50 μm square, there is a problem that the pixel occupation area ratio is significantly reduced. Ta. That is, a reduction in the pixel occupation area results in the disadvantage that the display screen becomes darker as a whole and the display quality deteriorates.

(d) Means for Solving the Problems The method for manufacturing a TFFT of an active matrix display device of the present invention includes forming a plurality of gate wirings made of opaque metal on a transparent substrate, and forming a transparent gate insulating film. After forming a layer, a transparent conductive film is formed, and with a resist applied to the upper surface of the transparent conductive film, a resist forming an inverted pattern of the gate wiring is left by back exposure using the gate wiring as a mask, Using the remaining resist as a mask, a patterning process is performed to separate the transparent conductive film along the gate wiring, and then a resist is applied again, and an exposure process is performed to remove the resist at positions other than the drain wiring with the drain electrode part and the source electrode position. By leaving the remaining resist as a mask and performing a patterning process to separate the transparent conductive film along the drain wiring, a large number of display electrodes made of the transparent conductive film are obtained in pixel units, and then the remaining resist is removed. A resist is created in which the display electrode is exposed by performing an exposure process to further extend the opening at the source electrode position toward the display electrode. In this state, metal is deposited on the entire surface, and the drain wiring with the drain electrode part and the source electrode This is what forms the lift-off.

(E) Function According to the method for manufacturing a TPT array of an active matrix display device of the present invention, the etching resist of the semiconductor film and the etching resist of the transparent conductive film are self-aligned to the gate wiring including the gate electrode using back exposure. Therefore, the semiconductor film is formed on the gate electrode and the transparent conductive film is formed offset from the gate wiring with high precision. Furthermore, the drain wiring including the drain electrode portion and the source electrode wiring are formed by lift-off using an etching resist for a transparent conductive film that has been further exposed to light. In other words, etching and lift-off are performed using substantially the same resist. Since each pattern is formed, display electrodes, drain wirings, and source electrode wirings made of the above-mentioned transparent electrodes can be obtained with high precision without being influenced by a photomask and an exposure device.

(f) Example FIG. 1 shows a plan view of each pixel of a TPT array of an active matrix display device obtained by the manufacturing method of the present invention.

A method for manufacturing the TPT array shown in FIG. 1 will be described below with reference to manufacturing process diagrams shown in FIGS. 2(i) to (vi) taken along line B-B.

(1) First step in the same figure (i) A gate line 20 locally provided with a gate electrode portion 2 made of Cr, Ta, etc. is formed on a transparent substrate 1 made of glass using a 7-oto mask. Form into the shape of.

A plurality of gate lines 20 are formed so as to extend horizontally between pixels, and the gate electrode portion 2 of each gate line 20 is arranged at a TPT forming position for each pixel. Note that by anodizing the surface of the gate line 20, it is possible to avoid a gate short-circuit accident.

(2), the second step in Figure (ii), the gate insulating film 3 made of a silicon nitride film or silicon oxide film, the amorphous silicon semiconductor film S4, and the phosphorus-doped amorphous silicon impurity semiconductor film S5 are P-C.
Films are sequentially formed using a VD device or the like.

(3), 3rd step of the same figure (iii) Apply a positive resist and expose the gate to the extreme part 2.
The resist other than the gate line 20 position is exposed to light, and then the resist is exposed to light again from the front side using a photomask to leave the resist R1 in an island shape on the gate electrode portion 2. The semiconductor film S4 and the impurity semiconductor film s5 are patterned using the remaining resist R1 as a mask to obtain the semiconductor film 4 of the TFT and the impurity semiconductor film 351 laminated thereon in the same pattern.

(4), 4th step in the same figure (iv) After forming a transparent conductive film made of ITO on the entire surface by a method such as sputtering and applying a negative resist, the gate line with the gate electrode part 2 is formed by back exposure. A resist R2 having a reverse pattern of 20 is formed, and the transparent conductive film is patterned. Note that the above-mentioned reversal pattern formation can also be produced by an image reversal method using a positive resist.

As a result, the transparent conductive film has multiple gate lines 20...
- It is divided into a plurality of transparent conductive films C6 extending horizontally in a band shape with a width slightly narrower than the interval.

(5) Apply the resist shown in the fifth step (v) of the same figure, and connect the drain to the edge 8 using a photomask.
A resist R3 having an inverted pattern of a plurality of drain lines 8°... and a source electrode 7... is formed, and each line divided into a plurality of lines in the horizontal direction in the fourth step is formed. By patterning the transparent conductive film C6 to further divide it in the vertical direction, a large number of display electrodes 6 are formed for each unit pixel.
．． Form 6... Display electrode 6.6 at this time...
As shown in the figure, the etching is performed so that over-etching of about 1 μm occurs.

Note that the resist R remaining on the TPT channel will determine the channel length during the subsequent lift-off formation of the drain electrode 8 and source electrode 7.

(6) In the sixth step of the same figure (vi), the remaining resist from the fifth step is removed by a second exposure process.
Inverted pattern resist R for a large number of source electrodes 7
3 is further removed to obtain a remaining resist R3' in which the display electrodes are partially exposed.

The exposure process at this time is to expand the opening of the resist R3' corresponding to the source electrode 7 toward the display electrode 6 side, so the display electrode is Only the edge portion on the 6th side is exposed.

(7), 7th step in Figure (vii) The resist R3' from the above 6th step remains, and in this state a film of a second metal such as titanium or aluminum is formed by a method such as sputtering, and the resist R3' is 'by drain electrode 8
A plurality of drain lines 80 . . . and a large number of source electrodes 7 . . . are formed by lift-off. Therefore, due to the over-etching in the fifth step, the drain lines 80... are separated by 1 μm from the adjacent display electrodes 6,6...
The drain electrodes 8 and 8 are separated by a narrow interval of about m.
... is bonded onto the impurity semiconductor film S5'. Furthermore, part of the source electrode 7... is an impurity semiconductor film S5.
The display electrodes 6, 6, .

(8), 8th step in FIG. 4(vi): The impurity semiconductor film S51 in the channel part of each TPT exposed as a result of the seventh step is removed by etching, and the drain electrode part 8 and the source electrode with respect to the semiconductor film 4 are removed. Impurity semiconductor film 5 that realizes ohmic contact in 7
．． form 5.

However, this impurity semiconductor film 5.5 is not necessarily necessary, and even if the semiconductor film 4 and the picture electrode 7.8 are directly bonded, TPT
The impurity semiconductor film 5.5 may be omitted if a junction state that does not impede the switching operation can be obtained. In this case, it is unnecessary to form the impurity semiconductor film S5 in the second step described above.

Through the steps up to the eighth step, the structure of each wiring, TPT, and display electrode is obtained, and the manufacturing process of the additional capacitance electrode 9 shown in FIG. 1 is further explained in FIG. Additional explanation will be provided using .

The additional capacitance electrode 9 is formed by lift-off of the source electrode 7 and the drain electrode 8 at the same time in the sixth and seventh steps shown in FIG. That is, as shown in FIG. 3 (φ), in the exposure process of the sixth step, a part of the display electrode 6 and the adjacent date tracer 4 are exposed.
A resist R3' having an opening at the 0 position is obtained. Subsequently, in a seventh step, as shown in FIG. 13(vii), the second metal is lifted off to obtain an island-shaped additional capacitance electrode 9 that overlaps a part of the adjacent gate line 20 with the gate insulating film 3 interposed therebetween.

Such additional capacitance electrodes 9... are connected to each display electrode 6 as described above.
. . , the charge storage capacity of each display electrode 6 is increased due to the capacitance between adjacent gate lines 20, and this contributes to suppressing a decrease in the potential of the display electrode 6 due to power consumption.

Further, as a method for providing such an additional capacitor, in addition to the above-mentioned method in which adjacent gate electrodes are used as counter electrodes, a method in which an additional capacitor counter electrode having an independent counter potential is provided can be considered. When this method is adopted in the present invention, the above-mentioned first
At the time of the process, an additional capacitor line having an additional capacitor counter electrode made of a first metal is formed to extend in parallel with the gate wire at the same time as the gate wire, and in the sixth and seventh parts, the additional capacitor electrode 9 is formed. It is only necessary to arrange the additional capacitance not on the adjacent gate line 20 but on the additional capacitance counter electrode.

Through the steps of the method according to the embodiment of the present invention described above, the number of photomasks used is reduced and the shift of pattern position due to the use of photomasks is suppressed, so that as shown in the plan view of FIG. , each display electrode 6... is shown in FIG. 5(a).
A TPT array of an active matrix display device that is enlarged with higher precision can be created using the conventional display electrode 6 shown in the plan view.

Furthermore, the steps of another embodiment of the method of the present invention are shown in FIG.

Figures (ii) and (vui) are respectively the same as the above-mentioned figure 2 (ii).
, (vi) corresponds to the steps of the embodiment of the present invention, and the other steps of this embodiment are similar to the other steps shown in FIG. 2, so their description will be omitted here.

FIG. 4(ii) shows the second step, in which a gate insulating film 3 made of a silicon nitride film or a silicon oxide film and an amorphous silicon semiconductor film S4 are sequentially formed using a P-CVD apparatus or the like.

Subsequently, the TP on the gate electrode part 2 is removed using a photomask.
A channel protection insulating film 10 is patterned into a predetermined shape at the T channel position. As for the patterning method at this time, it is preferable to use a mask to etch a resist formed by back exposure and front exposure using a photomask, as in the third step described above.

Thereafter, an impurity semiconductor film S5 is formed using a P-CVD device or the like. As the channel protection insulating film 10, for example, a silicon nitride film or a silicon oxide film can be used.

FIG. 4 (vni) shows the eighth step. In this step, when the impurity semiconductor film S5' in the channel part of each TPT is removed by etching, the channel protection insulating film 10 is removed from the channel part of the semiconductor film 4. Prevents etching.

As described above, by employing the manufacturing method of the present invention, for example, even when manufacturing an ultra-high definition liquid crystal display device with high pixel integration and compatible with high-definition vision, the display electrodes 6...
By enlarging the pixel area, the pixel occupation area ratio increases.
A bright, high-quality display is possible on the display screen. Further, the present invention is not limited to liquid crystal display devices, and even if it is applied to EL or EC display devices, the manufacturing effect will be the same.

(G) Effects of the Invention The method for manufacturing a TPT array of an active matrix display device of the present invention uses a self-alignment method using back exposure for patterning a semiconductor film and a transparent conductive film,
Furthermore, since the drain wiring is formed by lift-off using the resist used for display tS patterning, it is possible to reduce the number of photomasks used, and as a result, it is not affected by photomask accuracy or its alignment error, and in particular, it is possible to reduce the number of photomasks used. This makes it possible to form extremely high-precision patterns for display electrodes and drain wiring. Furthermore, the source electrode can be lift-off formed at the same time as the drain electrode provided on the drain wiring, and the resist exposure that determines the distance between these two electrodes can be achieved with a single mask, so the dimensional accuracy of the channel length will not deteriorate. A highly reliable TPT with uniform characteristics can be manufactured.

Therefore, according to the present invention, a high-definition active matrix display device with stable display quality can be obtained.

[Brief explanation of drawings]

FIG. 1 is a plan view of each pixel of a TPT array of an active matrix display device obtained by the manufacturing method of the present invention, and FIGS. 2(i) to (vim) show the manufacturing process of the TPT array of FIG. Process sectional view shown along line B, 3rd
Figures (vi) and (vii) are cross-sectional views showing the process of forming the additional capacitance electrode 9 shown in Figure 1 along line C-C in the same figure, and Figures 4 (ii) and (vui) are cross-sectional views showing the process of forming the additional capacitance electrode 9 shown in Figure 1. FIGS. 5(a) and 5(b), which are process cross-sectional views showing still another embodiment, are a plan view of each pixel of a conventional TPT array, and a cross-sectional view thereof taken along the line A--A. DESCRIPTION OF SYMBOLS 1... Transparent substrate, 2... Gate electrode part, 3...
Gate insulating film, 4... Semiconductor film, 5... Impurity semiconductor film, 6... Display electrode, 7... Source electrode, 8...
・Drain electrode, 9...Additional capacitance electrode, 10...Channel protection insulating film, 20...Gate line, 8
0...Drain line.

Claims (3)

[Claims] (1) Thin film transistors are arranged together with display electrodes at numerous intersections between a plurality of gate wirings and a plurality of drain wirings that intersect with the gate wirings, the gates of the thin film transistors are used as gate wirings, the drains are used as drain wirings, In addition, in a method for manufacturing a thin film transistor array for an active matrix display device in which a source is coupled to a display electrode, a plurality of gate wirings made of opaque metal are formed on a transparent substrate, and a transparent gate insulating film is laminated. After the formation, a transparent conductive film is formed, and with a resist applied to the upper surface of the transparent conductive film, a resist forming an inverted pattern of the gate wiring is left by back exposure using the gate wiring as a mask, and the remaining resist is removed. Using the resist as a mask, perform a patterning process to separate the transparent conductive film along the gate wiring, then apply the resist again, and use exposure to leave the resist in areas other than the drain wiring with the drain electrode part and the source electrode position. By using the remaining resist as a mask and performing a patterning process to separate the transparent conductive film along the drain wiring, a large number of display electrodes made of the transparent conductive film are obtained in pixel units, and then the source electrode position of the remaining resist is separated. A resist that exposes the display electrode is created by performing an exposure process to extend the opening further toward the display electrode. In this state, metal is deposited on the entire surface, and the drain wiring with the drain electrode part and the source electrode are lifted off. 1. A method for manufacturing a thin film transistor array for an active matrix display device. (2) A first step of forming a plurality of gate wirings each including a gate electrode portion using a first metal on a light-transmitting substrate, a second step of forming a gate insulating film and a semiconductor film, and applying a resist to form a gate wiring. The resist at the gate wiring positions other than the gate wiring positions is exposed by exposure from the back side of the substrate using a plurality of gate wirings having electrode parts as a mask, and the resist at the gate wiring positions other than the gate electrode parts is exposed by exposure processing from the substrate surface. The third step is to leave an island-shaped resist on the gate electrode portion and pattern the semiconductor film using the resist as a mask. After forming the transparent conductive film, a resist is applied, and a plurality of gates with the gate electrode portion are formed. A fourth step in which a resist forming an inverted pattern of the gate wiring remains by exposure from the back side of the substrate using the wiring as a mask, and a patterning process is performed to separate the transparent conductive film along the gate wiring using the remaining resist as a mask. A resist with an inverted pattern for the plurality of drain wirings having drain electrode portions and a large number of source electrodes is left by a first exposure process, and a transparent conductive film is applied along the drain wirings using the remaining resist as a mask. A fifth step in which a separating patterning process is performed to obtain a large number of display electrodes made of transparent conductive films in pixel units; the remaining resist from the fifth step is subjected to a second exposure process;
A sixth step of depositing a second metal and removing a portion of the resist with an inverted pattern for the plurality of source electrodes to obtain a remaining resist that partially exposes the display electrodes;
A method for manufacturing a thin film transistor array for an active matrix display device, comprising a sixth step of lift-off forming a drain wiring including a drain electrode portion and a source electrode using the residual resist obtained in the step. (3) Lift-off forming an island-shaped additional capacitor electrode made of a second metal independent of the drain wiring and source electrode having a drain electrode part, and connecting a part of the additional capacitor electrode to the display electrode and other 2. The method of manufacturing a thin film transistor array for an active matrix display device according to claim 1, wherein the thin film transistor array of an active matrix display device extends over an adjacent gate wiring.