JPH03192731A - Manufacture of thin film transistor array of active matrix display - Google Patents

Abstract

PURPOSE:To enable an active matrix display in high precision and stable display quality to be manufactured by a method wherein semiconductor films and a transparent conductive film are patterned by selfmatching process using the rear exposure while a drain wiring and a source wiring are liftoff formed using a resist for the display electrode patterning process. CONSTITUTION:Multiple gate wirings 20 comprising an opaque metal are formed on a transparent substrate 1; after laminately forming a phototransmitting gate insulating film 3, transparent conductive films S4, S5 are formed into films; resist R1 in inverse pattern of the gate wirings 20 is left by the rear exposure using the gate wirings 20 as masks on the surfaces of the transparent films S4, S5 coated with the resist R1. Next, the transparent conductive films S4, S5 are patterned to be isolated along the gate wirings 20 using the remaining resist R1 as a mask to be coated with another resist R2 repeatedly; the resist R2 is left on the positions excluding a drain wiring position provided with a drain electrode and a source electrode position by exposure process; and a transparent conductive film C6 is patterned to be isolated along the drain wiring. Through these procedures, a highly precise display electrode, the drain wiring and the source electrode wiring can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method of manufacturing a thin film transistor array for an active matrix display device.

(b) Conventional technology In recent years, active matrix display devices have been developed in which thin film transistors (hereinafter referred to as TPTs) functioning as switching transistors are connected to each display electrode of a large number of pixels arranged in a matrix, and these TPTs are used as drive circuits. ing. This device supplies pixel information to each display electrode via TPT, and optical changes occur in the liquid crystal layer, EL layer, or EC layer provided on the display electrode by electric field, current, or power according to this pixel information. [Japanese Patent Publication No. 62-6674].

In particular, active matrix liquid crystal display devices using the above-mentioned liquid crystal layer are currently attracting attention as displays for portable TVs.

FIG. 6(a) shows a plan view of each pixel of a TPT array in a conventional active matrix liquid crystal display device,
Figure (b) shows a cross-sectional view taken along line A-A at the TPT position.

These TPTs in the same figure are attached to one insulating substrate 1 of the liquid crystal cell.
Ohmic contacts are formed on the gate electrode 2 forming a part of the gate line 20, the gate insulating film 3 provided on the entire surface of the substrate, the localized semiconductor film 4, and the source and drain positions of the semiconductor film 4. It has a so-called inverted stagger type structure consisting of a stacked structure of impurity semiconductor films 5, 5, a source electrode 7, and a drain electrode 8, and a display electrode 6 for each pixel is connected to this source electrode 7.

TP of such a conventional active matrix display device
The method for manufacturing the T-array will be outlined below in order of steps.

(1) Step of forming a metal film for wiring on the insulating substrate 1 and forming the gate line 20 including the gate electrode 2 using a metal mask and photoresist.

(2) Using a P-CVD device or the like, the gate insulating film 3,
Step of sequentially forming a non-single crystal semiconductor film 4 and a non-single crystal impurity semiconductor film 5.

(3) A step of etching the semiconductor film 4 and the impurity semiconductor film 5 using a photomask and a photoresist.

(4) Step of forming a transparent conductive film and forming display electrodes 6 using a photomask and photoresist.

(5) A step of forming a metal film for wiring and forming a drain line 80 including the source electrode 7 and the drain electrode 8 using a photomask and photoresist.

(6) Etching the impurity semiconductor film 5 at the channel position between the picture electrodes 7 and 8.

(c) Problems to be Solved by the Invention According to the method of manufacturing a TPT array for an active matrix display device as described above, the processing accuracy of the TPT pattern is determined by the capabilities of the photomask and the exposure device.

Generally, the pitch error of current photomasks is ±1 μm.
Since the alignment error of the exposure device is ±1 μm, according to the conventional manufacturing method described above, the alignment error is ±2 μm, that is, 0 to 0.
A shift in the pattern position of 4 μm occurred, and a pattern design with sufficient margin to account for this position shift was required.

Therefore, when manufacturing a display device with a high pixel density, such as an ultra-high-definition liquid crystal display device compatible with high-definition television, with a pixel size of about 30 μm to 50 μm square, there is a problem that the pixel occupation area ratio is significantly reduced. Ta. That is, a reduction in the pixel occupation area results in the disadvantage that the display screen becomes darker as a whole and the display quality deteriorates.

(d) Means for Solving the Problems The method for manufacturing a TPT array of an active matrix display device of the present invention is to form a plurality of gate wirings made of opaque metal on a transparent substrate, and to insulate the transparent gates. After the films are laminated, a transparent conductive film is formed, and with a resist applied to the upper surface of the transparent conductive film, a resist forming an inverted pattern of the gate wiring is left by back exposure using the gate wiring as a mask. Using the remaining resist as a mask, a patterning process is performed to separate the transparent conductive film along the gate wiring, and then a resist is applied again, and an exposure process is performed to remove the resist at the drain wiring position with the drain electrode and other than the source electrode position. By leaving the remaining resist as a mask and performing a patterning process to separate the transparent conductive film along the drain wiring, a large number of display electrodes made of the transparent conductive film are obtained in pixel units, and then the resist is left behind. In this state, metal is deposited on the entire surface, drain wiring with a drain electrode and source electrode are lift-off formed, and a large number of new metals are used to electrically connect a large number of display electrodes and a large number of source electrodes. This forms source wiring.

(E) Function According to the method for manufacturing a TPT array of an active matrix display device of the present invention, the etching resist of the semiconductor film and the etching resist of the transparent conductive film are self-aligned to the gate wiring including the gate electrode using back exposure. Therefore, the semiconductor film is formed on the gate electrode and the transparent conductive film is formed offset from the gate wiring with high precision. Furthermore, since the drain wiring including the drain electrode portion and the source electrode are formed by lift-off using an etching resist of a transparent conductive film, that is, each pattern is formed by etching and lift-off using substantially the same resist. 7. Display electrodes, drain wiring, and source electrode wiring made of the above-mentioned transparent electrodes can be obtained with high precision without being influenced by the otomask and the exposure device.

(f) Example FIG. 1 shows a plan view of each pixel of a TPT array of an active matrix display device obtained by the manufacturing method of the present invention.

A method for manufacturing the TPT array shown in FIG. 1 will be described below with reference to manufacturing process diagrams shown in FIGS. 2(i) to (vui) taken along line B-B.

(1) First step in Figure (i) A gate line 20 locally provided with a gate electrode portion 2 made of Cr, Ta, etc. is formed on a transparent substrate 1 made of glass using a photomask. Form into the shape of.

A plurality of gate lines 20 are formed so as to extend horizontally between pixels, and the gate electrode portion 2 of each gate line 20 is arranged at a TPT forming position for each pixel. Note that by anodizing the surface of the gate line 20, it is possible to avoid a gate short-circuit accident.

(2) In the second step of the same figure (ii), the gate insulating film 3 made of a silicon nitride film or silicon oxide film, the amorphous silicon semiconductor film S4, and the phosphorus-doped amorphous silicon impurity semiconductor film S5 are P-C.
Films are sequentially formed using a VD device or the like.

(3), the third step of the same figure (iii): Applying a positive resist, and exposing the gate electrode part 2 by back exposure.
The resist other than the gate line 20 position is exposed to light, and then the resist is exposed to normal light again from the front side using a 7-oto mask to leave the resist R1 in an island shape on the gate electrode portion 2. The semiconductor film S4 and the impurity semiconductor film S5 are patterned using the remaining resist R1 as a mask to obtain a TPT semiconductor film 4 and an impurity semiconductor film S5' laminated thereon in the same pattern.

(4), 4th step in the same figure (iv) After forming a transparent conductive film made of ITO on the entire surface by a method such as sputtering and applying a negative resist, the gate line with the gate electrode part 2 is formed by back exposure. A resist R2 having a reverse pattern of 20 is formed, and the transparent conductive film is patterned. Note that the above-mentioned reversal pattern formation can also be produced by an image reversal method using a positive resist.

As a result, the transparent conductive film has multiple gate lines 20...
- It is divided into a plurality of transparent conductive films C6 extending horizontally in a band shape with a width slightly narrower than the interval.

(5) Apply the fifth step resist shown in FIG.
A resist R3 having an inverted pattern of a plurality of drain lines 80... and a source electrode 7... is formed, and each transparent line divided into a plurality of lines in the horizontal direction in the fourth step is formed. By patterning the conductive film C6 to further divide it in the vertical direction, a large number of display electrodes 6 are formed for each unit pixel.
．． Form 6... Display electrode 6.6 at this time...
As shown in the figure, the etching is performed so that over-etching of about 1 μm occurs.

Note that the resist R remaining on the TPT channel will determine the channel length during the subsequent lift-off formation of the drain electrode 8 and source electrode 7.

(6), 6th step of the same figure (vi) The resist R3 in the above fifth step remains, and in this state, a second metal such as titanium or aluminum is formed into a film by a method such as sputtering, and the resist R3 is Yori drain electrode 8...
. A plurality of drain lines 80 . . . and a large number of source electrodes 7 . . . are formed by lift-off. Therefore, due to the over-etching in the fifth step, the drain lines 80... are separated by 1 μm from the adjacent display electrodes 6,6...
The drain electrodes 8...
. A part of it is bonded onto the impurity semiconductor film S5'. On the other hand, a part of the source electrode 7... is an impurity semiconductor film S.
5', but in this state there is no electrical connection between the source electrode 7 and the display electrodes 6, 6, . . . .

(7), Step 7 in Figure (vii) A third metal such as aluminum or titanium is deposited by a method such as sputtering, a resist is applied, and this is further exposed using a photomask to remove the remaining resist. As a mask, the third
By patterning the metal, a large number of display electrodes 6 can be formed.
... and a large number of source electrodes 7... are obtained.

(8), 8th step in the same figure (yii) The impurity semiconductor film S5' in the channel part of each TPT exposed as a result of the above seventh step is removed by etching, and the drain electrode part 8 and the source with respect to the semiconductor film 4 are removed. Impurity semiconductor film 5 that realizes ohmic contact of electrode 7
．． form 5.

However, this impurity semiconductor film 5.5 is not necessarily necessary, and even if the semiconductor film 4 and the picture electrode 7.8 are directly bonded, TPT
The impurity semiconductor film 5.5 may be omitted if a junction state that does not impede the switching operation can be obtained. In this case, it becomes unnecessary to form the impurity semiconductor film S5 in the second step described above.

Through the steps up to the eighth step, the structure of each wiring, TPT, and display electrode is obtained, and additional capacitance electrode 9 shown in FIG.
The manufacturing process will be additionally explained with reference to FIG. 3, which shows the cross-sectional process taken along the line C--C in the figure.

The additional capacitance electrode 9 is connected to the fifth, sixth, and seventh electrodes in FIG.
In the process, a drain line 80 including a source electrode 7 and a drain electrode 8 is simultaneously formed by lift-off.

That is, as shown in FIG. 3(v), in the fifth step, when obtaining a resist R3 having an inverted pattern of the positions of the drain line 80 and the source electrode 7, the resist R3 is placed on the gate line. An opening is provided at the position of the additional capacitance electrode 9 on the island. By etching the display electrode 6 in this state, over-etching of about 1 μm occurs even at this opening position.

Subsequently, as shown in FIG. 6(vi), in the sixth step [second metal lift-off treatment], the additional layer made of the second metal is separated from the display electrode 6 by the above-mentioned overetching. Capacitive electrode 9... is obtained.

After that, as shown in the same figure (vii), the seventh step [third
[Metal patterning process] At the same time as the source bridge wiring 11 is formed, the display electrode 6 and the adjacent gate line 2 are
An additional capacitance bridge 12 is obtained which electrically connects and wires the additional capacitance electrode 9 on the additional capacitance electrode 9.

The additional capacitance electrodes 9 connected in this way are formed for each display electrode 6 as described above, and the charge of each display electrode 6 is increased by the capacitance between the adjacent gate line 20. It increases the storage capacity and contributes to suppressing a potential drop in the display electrode 6 due to power consumption.

Further, as a method for providing such an additional capacitor, in addition to the above-mentioned method in which adjacent gate electrodes are used as counter electrodes, a method in which an additional capacitor counter electrode having an independent counter potential is provided can be considered. When this method is adopted in the present invention, the above-mentioned first
At the time of the process, an additional capacitor line having an additional capacitor counter electrode made of the first metal is formed to extend in parallel with the gate wiring at the same time as the gate wiring, and the fifth, sixth, and seventh steps are performed as described above. Then, the additional capacitor electrode 9 may be placed and connected not on the adjacent gate line 20 but on the additional capacitor counter electrode.

Through the steps of the method according to the embodiment of the present invention described above, the number of photomasks used is reduced and the shift of pattern position due to the use of photomasks is suppressed, so that as shown in the plan view of FIG. , each display electrode 6... is shown in FIG. 6(a).
A TPT array of an active matrix display device that is enlarged with higher precision can be created using the conventional display electrode 6 shown in the plan view.

In addition, in the embodiment of the method of the present invention described above, the source bridges 11... and the additional capacitance bridges 12 are formed by the third metal.
However, as shown in FIG.
1 can be stacked to prevent disconnection of the line. In this case, by making the line width of the auxiliary drain line 81 narrower than that of the drain line 80, it is possible to avoid the possibility that the channel length will be distorted or that an unnecessary short circuit with the adjacent display electrode 6 will occur due to patterning errors at this time.

Furthermore, the steps of another embodiment of the method of the present invention are shown in FIG.

Figures (ii) and (vim) are the same as the above-mentioned figure 2 (ii), respectively.
, (vui) corresponds to the steps of the embodiment of the present invention, and the other steps of this embodiment are similar to the other steps shown in FIG. 2, so their description will be omitted here.

FIG. 4(ii) shows the second step, in which a gate insulating film 3 made of a silicon nitride film or a silicon oxide film and an amorphous silicon semiconductor film S4 are sequentially formed using a P-CVD apparatus or the like.

Subsequently, the TP on the gate electrode part 2 is removed using a 7-oto mask.
A channel protection insulating film 10 is patterned into a predetermined shape at the T channel position. As for the patterning method at this time, it is preferable to etch a resist formed by back exposure and front exposure using a 7-oto mask into a mask, as in the third step described above.

Thereafter, an impurity semiconductor film S5 is formed using a P-CVD device or the like. As the channel protection insulating film 10, for example, a silicon nitride film or a silicon oxide film can be used.

FIG. 4(vii) shows the eighth step. In this step, when the impurity semiconductor film S5' in the channel portion of each TPT is removed by etching, the channel protective insulating film IO is removed from the channel portion of the semiconductor film 4. Prevents etching.

As described above, by employing the manufacturing method of the present invention, for example, even when manufacturing an ultra-high definition liquid crystal display device with high pixel integration and compatible with high-definition vision, the display electrodes 6...
By enlarging the pixel area, the pixel occupation area ratio increases.
A bright, high-quality display is possible on the display screen. Further, the present invention is not limited to liquid crystal display devices, and even if it is applied to EL or EC display devices, the manufacturing effect will be the same.

(G) Effects of the Invention The method for manufacturing a TPT array of an active matrix display device of the present invention uses a self-alignment method using back exposure for patterning a semiconductor film and a transparent conductive film,
Furthermore, since the drain wiring is formed by lift-off using the resist used for patterning the display electrodes, the number of photomasks used can be reduced, and as a result, it is not affected by the accuracy of the photomasks or their alignment errors. This makes it possible to pattern display electrodes and drain wiring with extremely high precision. Furthermore, the source electrode can be lift-off formed at the same time as the drain electrode provided on the drain wiring, and the resist exposure that determines the distance between these two electrodes can be achieved with a single mask, so the dimensional accuracy of the channel length will not deteriorate. A highly reliable TPT with uniform characteristics can be manufactured.

Therefore, according to the present invention, a high-definition active matrix display device with stable display quality can be obtained.

[Brief explanation of drawings]

FIG. 1 is a plan view of each pixel of a TPT array of an active matrix display device obtained by the manufacturing method of the present invention, and FIGS. 2(i) to (vni) show the manufacturing process of the TPT array of FIG. Process sectional view shown along line B, 3rd
Figures (V), (Acceptable), and (vii) are cross-sectional views showing the process of forming the additional capacitance electrode 9 shown in Figure 1 along line C--C in the same figure, and Figure 4 is a cross-sectional view showing another method of the present invention. 5(i) and (inert) are process sectional views showing still another embodiment of the method of the present invention, and FIG. 6(a) and (b) are conventional T
FIG. 2 is a plan view of each pixel of the PT array, and a cross-sectional view taken along the line AA of the PT array. l... Transparent substrate, 2... Gate electrode portion, 3...
Gate insulating film, 4... Semiconductor film, 5... Impurity semiconductor film, 6... Display electrode, 7... Source electrode, 8...
・Drain electrode, 9... Additional capacitance electrode, 10... Channel protection insulating film, 11... Source bridge, 12
...Additional capacitance bridge, 20...Gate line, 8
0... Rain line.

Claims (4)

[Claims] (1) Thin film transistors are arranged together with display electrodes at numerous intersections between a plurality of gate wirings and a plurality of drain wirings that intersect with the gate wirings, the gates of the thin film transistors are used as gate wirings, the drains are used as drain wirings, In addition, in a method for manufacturing a thin film transistor array for an active matrix display device in which a source is coupled to a display electrode, a plurality of gate wirings made of opaque metal are formed on a transparent substrate, and a transparent gate insulating film is laminated. After the formation, a transparent conductive film is formed, and with a resist applied to the upper surface of the transparent conductive film, a resist forming an inverted pattern of the gate wiring is left by back exposure using the gate wiring as a mask, and the remaining resist is removed. Using the resist as a mask, perform a patterning process to separate the transparent conductive film along the gate wiring, then apply the resist again, and use exposure to leave the resist in areas other than the drain wiring position with the drain electrode and the source electrode position. By using the remaining resist as a mask and performing a patterning process to separate the transparent conductive film along the drain wiring, a large number of display electrodes made of the transparent conductive film were obtained in pixel units, and then the resist was allowed to remain. In this state, metal is deposited on the entire surface, a drain wiring with a drain electrode and a source electrode are lift-off formed, and a large number of source wirings are formed to electrically connect a large number of display electrodes and a large number of source electrodes using new metal. 1. A method for manufacturing a thin film transistor array for an active matrix display device, characterized by forming a thin film transistor array. (2) A first step of forming a plurality of gate wirings each including a gate electrode portion using a first metal on a light-transmitting substrate, a second step of forming a gate insulating film and a semiconductor film, and applying a resist to form a gate wiring. The resist at the gate wiring positions other than the gate wiring positions is exposed by exposure from the back side of the substrate using a plurality of gate wirings having electrode parts as a mask, and the resist at the gate wiring positions other than the gate electrode parts is exposed by exposure processing from the substrate surface. The third step is to leave an island-like resist only on the gate electrode portion and pattern the semiconductor film using the resist as a mask. A fourth step in which a resist forming an inverted pattern of the gate wiring remains by exposure from the back side of the substrate using the gate wiring as a mask, and a patterning process is performed to separate the transparent conductive film along the gate wiring using the remaining resist as a mask; A resist is applied and a first exposure process is performed to leave a resist with an inverted pattern for a plurality of drain wirings including drain electrode portions and a large number of source electrodes, and a transparent conductive film is applied along the drain wirings using the remaining resist as a mask. A fifth step in which a plurality of display electrodes made of transparent conductive films for each pixel are obtained by patterning the electrodes to separate them, and a second metal is deposited, and the remaining resist from the fifth step is used as a mask to form a plurality of display electrodes each having a drain electrode. A sixth step of lift-off forming the drain wiring and a large number of source electrodes. A method for manufacturing a thin film transistor array for an active matrix display device, comprising a seventh step of forming a number of source bridge wirings electrically coupling a number of display electrodes and a number of source electrodes using a third metal. (3) In the sixth step, an island-shaped additional capacitance electrode made of a second metal independent of the drain electrode wiring and the source electrode is placed on the adjacent gate wiring at the same time as the drain electrode wiring and the source electrode. Lift-off formation,
3. The thin film transistor of the active matrix display device according to claim 2, wherein, in said seventh step, an additional capacitance bridge wiring made of a third metal that connects said additional capacitance electrode and said display electrode is formed simultaneously with said source bridge wiring. Array manufacturing method. (4) In the seventh step, simultaneously with the source bridge wiring, an auxiliary drain wiring made of a third metal is laminated on the drain wiring made of a second metal independently of the source bridge wiring. 3. A method for manufacturing a thin film transistor array for an active matrix display device according to item 2.