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JPH03190265A - Semiconductor chip carrier - Google Patents

Semiconductor chip carrier

Info

Publication number
JPH03190265A
JPH03190265A JP1330255A JP33025589A JPH03190265A JP H03190265 A JPH03190265 A JP H03190265A JP 1330255 A JP1330255 A JP 1330255A JP 33025589 A JP33025589 A JP 33025589A JP H03190265 A JPH03190265 A JP H03190265A
Authority
JP
Japan
Prior art keywords
metal plate
insulating layer
metal sheet
semiconductor chip
terminal pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1330255A
Other languages
Japanese (ja)
Other versions
JP2658451B2 (en
Inventor
Koji Minami
浩司 南
Hitoshi Arai
荒井 斉
Akitsugu Maeda
晃嗣 前田
Takeshi Kano
武司 加納
Toru Higuchi
徹 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP1330255A priority Critical patent/JP2658451B2/en
Publication of JPH03190265A publication Critical patent/JPH03190265A/en
Application granted granted Critical
Publication of JP2658451B2 publication Critical patent/JP2658451B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To make it possible to cope with the generation of heat ever increasing as a result of higher integration, more enhanced functions and higher-speed operation of semiconductor chips by extending the size of a metal sheet inserted into an insulation layer up to a region of the metal sheet where thermal pins are installed. CONSTITUTION:The size of a metal sheet 2 inserted into an insulation layer 1 is extended up to a region of the metal sheet 2 where thermal pins 3 are installed in order to improve its heat dissipation performance. In order that the metal sheet 2 must be extended up to the region where the terminal pins 3 are installed, a hole 8 larger than the terminal pins 3 are bored on the metal sheet 2 in positions equivalent to the installation position of the terminal pins 3 so that the terminal pins 3 may not come off from the metal plate 2. Therefore, the portion of the metal sheet 2 which is engaged with an outside heat radiation body 6 is enlarged, it is possible to relieve the restrictions imposed to the shape of the outside heat radiation body 6 and to mount the outside heat radiation body 6 with ease. This construction makes it possible to cope with higher integration, more enhanced functions and higher-speed operation of semiconductor chips.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体チップ搭載に用いられる半導体チッ
プキャリアに関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor chip carrier used for mounting a semiconductor chip.

〔従来の技術〕[Conventional technology]

半導体チップキャリアを構成する絶縁層にはガラス布を
基材としたエポキシ樹脂積層板などのプリント配線板が
最近用いられるようになってきている。しかし、このよ
うなプリント配線板では熱の伝導性が悪く、良好に放熱
をすることができない。先に本発明者らは、特開昭62
−52992において、絶縁層に金属板を挿入して配設
し、この金属板の一部を外部に露出させ、放熱性を良好
にした樹脂積層板のプリント配線板から構成された第4
図に示す半導体チップキャリアを提供した。
Printed wiring boards such as epoxy resin laminates based on glass cloth have recently come to be used as insulating layers constituting semiconductor chip carriers. However, such printed wiring boards have poor thermal conductivity and cannot dissipate heat well. Previously, the present inventors published Japanese Patent Application Laid-Open No. 62
-52992, a fourth structure is constructed of a resin laminated printed wiring board in which a metal plate is inserted into an insulating layer and a part of the metal plate is exposed to the outside to improve heat dissipation.
The semiconductor chip carrier shown in the figure was provided.

このものは、絶縁層1が金属板2の周縁部から中央より
の部分まで被覆し、金属板2の中央部分を中心に絶縁層
のない凹部が形成され、この凹部の底面には前記金属板
2が露出してなり、一方の第1の凹部4は放熱用に、他
方の第2の凹部5は半導体チップ7搭載用にそれぞれ設
けられてなることを特徴とする半導体チップキャリアで
、金属板2が凹部で外部に露出しているために良好な放
熱性と絶縁層1が金属板2の周縁部より中央よりの部分
まで被覆していることによりプリント配線板の絶縁層1
に配設された端子ピン3の領域より内側に挿入された金
属板2の動きを阻止し、さらに絶縁層1と金属板2に生
ずる隙間を密閉して耐湿性を高めた半導体チップキャリ
アとしたところに特徴があった。
In this device, an insulating layer 1 covers a metal plate 2 from the peripheral edge to the center, and a recess without an insulating layer is formed around the center of the metal plate 2, and the bottom of this recess is covered with the metal plate 2. 2 is exposed, one first recess 4 is provided for heat dissipation, and the other second recess 5 is provided for mounting a semiconductor chip 7. The insulating layer 1 of the printed wiring board has good heat dissipation properties because the insulating layer 2 is exposed to the outside through the recess, and the insulating layer 1 covers the metal plate 2 from the periphery to the center.
This semiconductor chip carrier has improved moisture resistance by blocking the movement of the metal plate 2 inserted inside the area of the terminal pins 3 arranged in the area, and further sealing the gap between the insulating layer 1 and the metal plate 2. There was something special about it.

ところが、半導体チップの高速化、高集積化、高機能化
による半導体チップの発熱量の増大に伴って熱放散性の
一層優れた半導体チップキャリアの造出かますます大き
く期待される中で、絶縁層に挿入された金属板の拡大化
には、同じ絶縁層に配設される端子ピンとの接触と言う
制限があった。また、外部放熱体を前記半導体チップキ
ャリアに取り付けるのに、金属板2が絶縁層1の表面よ
り窪んでいるために外部放熱体6の形状に制限が加わり
、取り付は部が放熱用の凹部4より小さな外部放熱体6
に制限され、放熱量の増大をはかる外部放熱体6の形状
の自由度が小さなものであった。
However, with the increase in the amount of heat generated by semiconductor chips as they become faster, more highly integrated, and more highly functional, there are increasing expectations for the creation of semiconductor chip carriers with even better heat dissipation properties. The expansion of the metal plate inserted into the layer was limited by contact with terminal pins disposed in the same insulating layer. In addition, when attaching the external heat sink to the semiconductor chip carrier, since the metal plate 2 is recessed from the surface of the insulating layer 1, there are restrictions on the shape of the external heat sink 6. External heat sink smaller than 4 6
The degree of freedom in the shape of the external heat radiator 6, which aims to increase the amount of heat dissipated, was small.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

熱放散性をさらに一層高めるために、絶縁層に挿入され
る金属板の大きさを、端子ピンが配設される領域にまで
拡大した金属板を使用できるようにし、外部放熱体の形
状に加わった制限を解除するとともに、外部放熱体を簡
単に取り付けできる構造の半導体チンプキャリアを提供
することにある。
In order to further improve heat dissipation, the size of the metal plate inserted into the insulating layer has been expanded to include the area where the terminal pins are arranged, and the size of the metal plate inserted into the insulating layer has been expanded to include the area where the terminal pins are arranged. It is an object of the present invention to provide a semiconductor chimp carrier having a structure in which an external heat dissipation body can be easily attached while also eliminating the above restrictions.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は前記課題を解決するために、絶縁層に埋入され
た金属板、この金属板の両表面の周縁部から中央よりに
絶縁層を残し、絶縁層の両面に形成された凹部、これら
凹部の底面に露出する前記金属板、この金属板に形成さ
れた端子ピンの外径より大きな複数個の穴、この複数個
設けられた穴より小さな径でこの穴と同じ位置に形成さ
れた絶縁層の貫通穴に配設された端子ピンを有すること
を特徴とする半導体チップキャリアを提供するものであ
る。
In order to solve the above problems, the present invention provides a metal plate embedded in an insulating layer, an insulating layer left on both surfaces of the metal plate from the periphery to the center, and recesses formed on both sides of the insulating layer. The metal plate exposed at the bottom of the recess, a plurality of holes formed in this metal plate that are larger than the outer diameter of the terminal pin, and an insulator formed at the same position as the holes with a smaller diameter than the plurality of holes. The present invention provides a semiconductor chip carrier characterized in that it has terminal pins disposed in through-holes in the layers.

〔実施例〕〔Example〕

以下に、本発明を図面に基づいて詳しく説明する。第1
図は本発明の一実施例の斜視図、第2図は外部放熱体を
取り付けた第1図のX−Y断面図である。第2図の半導
体チップキャリアは絶縁層1に埋入された金属板2.こ
の金属板の両表面の周縁部から中央よりに絶縁層1を残
して、絶縁層1の両面に形成された凹部を有する。一方
の凹部である第1の凹部4は、外部放熱体6を取りつけ
るためのもので、金属板2が絶縁層1からはずれない程
度に絶縁層1が金属板2の周縁部から中央よりに残って
いれば良く、放熱性を向上させるのにはできるだけ広い
金属板2の露出面積を確保する形状が望ましい。他方の
凹部である第2の凹部5は、半導体チップ7を搭載する
ためのもので、この第2の凹部5の底面に露出する金属
板2に半導体チップ7を搭載すると半導体チップ7から
発生する熱は金属板2に吸収され、さらに、熱伝導性に
優れた金属板2の反対側において、第1の凹部4の底面
に取付けられた側面にフィンを有する外部放熱体6へと
移動し、熱が金属板2内にこもることな(空気中に放熱
されることになって半導体チップ7の高集積化、高機能
化、高速化に対応可能となる。
The present invention will be explained in detail below based on the drawings. 1st
The figure is a perspective view of one embodiment of the present invention, and FIG. 2 is an XY cross-sectional view of FIG. 1 with an external heat sink attached. The semiconductor chip carrier shown in FIG. 2 includes a metal plate 2 embedded in an insulating layer 1. This metal plate has recesses formed on both sides of the insulating layer 1, leaving the insulating layer 1 from the periphery to the center of both surfaces. The first recess 4, which is one of the recesses, is for attaching an external heat sink 6, and the insulating layer 1 remains from the periphery of the metal plate 2 toward the center to the extent that the metal plate 2 does not come off the insulating layer 1. In order to improve heat dissipation, it is desirable to have a shape that ensures as wide an exposed area of the metal plate 2 as possible. The second recess 5, which is the other recess, is for mounting the semiconductor chip 7. When the semiconductor chip 7 is mounted on the metal plate 2 exposed on the bottom surface of the second recess 5, the semiconductor chip 7 generates dust. The heat is absorbed by the metal plate 2 and further transferred to the external heat radiator 6 having fins on the side surface attached to the bottom of the first recess 4 on the opposite side of the metal plate 2 having excellent thermal conductivity, Since the heat is not trapped in the metal plate 2 (it is radiated into the air), it becomes possible to support higher integration, higher functionality, and higher speed of the semiconductor chip 7.

第2の凹部5の底面の金属板2に搭載された半導体子ツ
ブ7と絶縁層1の表面に形成された導体回路11は金属
線12を介して接続され、さらに、この導体回路11は
外部端子として働く端子ピン3を挿入するための絶縁層
1に形成された貫通穴9のスルホールメツキ層に接続し
ている。
The semiconductor chip 7 mounted on the metal plate 2 on the bottom of the second recess 5 and the conductor circuit 11 formed on the surface of the insulating layer 1 are connected via a metal wire 12. It is connected to a through hole plating layer of a through hole 9 formed in the insulating layer 1 into which a terminal pin 3 serving as a terminal is inserted.

なお、第1の凹部4や第2の凹部5としての形状は 周
知の如く四角柱状が一般的であるが、特に制限する趣旨
ではなく円柱などでもよい。
As is well known, the shapes of the first recess 4 and the second recess 5 are generally rectangular prisms, but there is no particular limitation and they may be cylindrical or the like.

上記構成の半導体チップキャリアにおいて、金属板2を
端子ピン3の配設される領域にまで拡大させるために、
端子ピン3が金属板2と接触しないように端子ピン3が
配設される位置に相当する金属板2の位置に端子ピン3
より大きな径の六8を設ける。この穴は第2図に示した
貫通穴でもよく、第3図の他の実施例を示す拡大図の未
貫通穴10でもよく、その形状も円柱でも、四角柱でも
よく、特に限定するものではなく、端子ピン3と接触し
ない大きさであれば十分である。
In the semiconductor chip carrier having the above configuration, in order to expand the metal plate 2 to the area where the terminal pins 3 are arranged,
The terminal pin 3 is placed at a position on the metal plate 2 corresponding to the position where the terminal pin 3 is arranged so that the terminal pin 3 does not come into contact with the metal plate 2.
68 with a larger diameter is provided. This hole may be a through hole shown in FIG. 2, or may be a non-through hole 10 shown in an enlarged view showing another embodiment in FIG. 3, and its shape may be a cylinder or a square prism, and is not particularly limited. It is sufficient if the size is such that it does not come into contact with the terminal pin 3.

半導体チップキャリアの形態としては、端子ピン3を外
部放熱体6の取りつく面と反対の絶縁層1に形成された
貫通穴9に配設されたものが、放熱を高めるのには好ま
しい。
As for the form of the semiconductor chip carrier, one in which the terminal pins 3 are disposed in through holes 9 formed in the insulating layer 1 opposite to the surface to which the external heat radiator 6 is attached is preferable in order to improve heat radiation.

また、外部放熱体6の形状も角柱で側面フィンを有する
もの、あるいは円柱で上面フィンを有するものなど一般
に放熱体、放熱フィンとして用いられているものを用い
ることができる。
Further, the shape of the external heat radiator 6 may be a prism with side fins, or a cylinder with top fins, which are generally used as a heat radiator or heat radiator fin.

次に、使用材料について述べると、第2図の半導体チッ
プキャリアを構成する絶縁層1は、基材に樹脂を含浸乾
燥して得られたプリプレグの樹脂を硬化した絶縁材料が
用いられる。ここで絶縁層lの樹脂としては耐熱性、耐
湿性に優れかつ樹脂純度、特にイオン性不純物の少ない
ものが好ましい。具体的には、エポキシ樹脂、ポリイミ
ド樹脂、フンソ樹脂、フェノール樹脂、不飽和ポリエス
テル樹脂、PPO樹脂などが適している。なお絶縁層1
の基材としては、紙よりガラス繊維などの無機材料の方
が耐熱性、耐湿性などに優れ好ましい。
Next, regarding the materials used, the insulating layer 1 constituting the semiconductor chip carrier shown in FIG. 2 is made of an insulating material obtained by curing the resin of a prepreg obtained by impregnating a base material with a resin and drying it. Here, the resin for the insulating layer 1 is preferably one that has excellent heat resistance and moisture resistance, and has high resin purity, particularly low ionic impurities. Specifically, epoxy resin, polyimide resin, Funso resin, phenol resin, unsaturated polyester resin, PPO resin, etc. are suitable. Note that insulating layer 1
As the base material, an inorganic material such as glass fiber is preferable to paper because of its superior heat resistance and moisture resistance.

絶縁層lに挿入される金属板2や金属板2に取り付けら
れる外部放熱体6としては、例えば銅板、銅合金板、銅
−インバー−銅合金板、鉄−ニッケル合金板、その他制
板、鉄板、アルミニウム板などを使用することができる
Examples of the metal plate 2 inserted into the insulating layer 1 and the external heat sink 6 attached to the metal plate 2 include copper plates, copper alloy plates, copper-invar-copper alloy plates, iron-nickel alloy plates, other control plates, and iron plates. , aluminum plate, etc. can be used.

〔発明の効果〕〔Effect of the invention〕

本発明に係る半導体チップキャリアは叙述の如く、絶縁
層に挿入される金属板の大きさを、端子ピンが配設され
る領域にまで拡大した金属板とすることができ、露出し
て外部放熱体と接合する金属板の部分が大きくなるため
、外部放熱体の形状に加わった制限を解除することがで
きると伴に、外部放熱体を簡単に取り付けできる構造の
半導体チップキャリアとなり、半導体チンプの高集積化
、高機能化、高速化によって増大する発熱に対応可能な
半導体チップキャリアとなるものである。
As described above, in the semiconductor chip carrier according to the present invention, the size of the metal plate inserted into the insulating layer can be enlarged to the area where the terminal pins are arranged, and the metal plate is exposed to dissipate heat from the outside. Since the part of the metal plate that joins with the body becomes larger, it is possible to remove the restrictions placed on the shape of the external heat sink, and it becomes a semiconductor chip carrier with a structure that allows the external heat sink to be easily attached, making it possible to improve the structure of the semiconductor chip. This is a semiconductor chip carrier that can cope with increased heat generation due to higher integration, higher functionality, and faster speeds.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す斜視図、第2図はその
X−Y断面図に外部放熱体が取り付けられたもの、 第3図は他の実施例を示す部分拡大の断面図、第4図は
一従来例の断面図をそれぞれ示す。 1・・・絶縁層    2・・・金属板3・・・端子ピ
ン   4・・・第1の凹部5・・・第2の凹部  6
・・・外部放熱体7・・・半導体チンプ 8・・・穴 9・・・貫通穴 第1W1 11!2図
Fig. 1 is a perspective view showing one embodiment of the present invention, Fig. 2 is an X-Y sectional view of the same with an external heat sink attached, and Fig. 3 is a partially enlarged sectional view showing another embodiment. , and FIG. 4 respectively show cross-sectional views of a conventional example. 1... Insulating layer 2... Metal plate 3... Terminal pin 4... First recess 5... Second recess 6
...External heat sink 7...Semiconductor chimp 8...Hole 9...Through hole 1st W1 11!2 Fig.

Claims (1)

【特許請求の範囲】[Claims] (1)絶縁層に埋入された金属板、この金属板の両表面
の周縁部から中央よりに絶縁層を残し、絶縁層の両面に
形成された凹部、これら凹部の底面に露出する前記金属
板、この金属板に形成された端子ピンの外径より大きな
複数個の穴、この複数個設けられた穴より小さな径でこ
の穴と同じ位置に形成された絶縁層の貫通穴に配設され
た端子ピンを有することを特徴とする半導体チップキャ
リア。
(1) A metal plate embedded in an insulating layer, recesses formed on both sides of the insulating layer with the insulating layer left from the periphery to the center on both surfaces of the metal plate, and the metal exposed at the bottom of these recesses. A plate, a plurality of holes larger than the outer diameter of the terminal pin formed in this metal plate, and a through hole in an insulating layer formed at the same position as the hole with a smaller diameter than the plurality of holes. A semiconductor chip carrier characterized by having terminal pins.
JP1330255A 1989-12-20 1989-12-20 Semiconductor chip carrier Expired - Lifetime JP2658451B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1330255A JP2658451B2 (en) 1989-12-20 1989-12-20 Semiconductor chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1330255A JP2658451B2 (en) 1989-12-20 1989-12-20 Semiconductor chip carrier

Publications (2)

Publication Number Publication Date
JPH03190265A true JPH03190265A (en) 1991-08-20
JP2658451B2 JP2658451B2 (en) 1997-09-30

Family

ID=18230596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1330255A Expired - Lifetime JP2658451B2 (en) 1989-12-20 1989-12-20 Semiconductor chip carrier

Country Status (1)

Country Link
JP (1) JP2658451B2 (en)

Also Published As

Publication number Publication date
JP2658451B2 (en) 1997-09-30

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