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JP2658451B2 - Semiconductor chip carrier - Google Patents

Semiconductor chip carrier

Info

Publication number
JP2658451B2
JP2658451B2 JP1330255A JP33025589A JP2658451B2 JP 2658451 B2 JP2658451 B2 JP 2658451B2 JP 1330255 A JP1330255 A JP 1330255A JP 33025589 A JP33025589 A JP 33025589A JP 2658451 B2 JP2658451 B2 JP 2658451B2
Authority
JP
Japan
Prior art keywords
metal plate
insulating layer
semiconductor chip
chip carrier
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1330255A
Other languages
Japanese (ja)
Other versions
JPH03190265A (en
Inventor
浩司 南
斉 荒井
晃嗣 前田
武司 加納
徹 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP1330255A priority Critical patent/JP2658451B2/en
Publication of JPH03190265A publication Critical patent/JPH03190265A/en
Application granted granted Critical
Publication of JP2658451B2 publication Critical patent/JP2658451B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体チップ搭載に用いられる半導体チ
ップキャリアに関するものである。
Description: TECHNICAL FIELD The present invention relates to a semiconductor chip carrier used for mounting a semiconductor chip.

〔従来の技術〕[Conventional technology]

半導体チップキャリアを構成する絶縁層にはガラス布
を基材としたエポキシ樹脂積層板などのプリント配線板
が最近用いられるようになってきている。しかし、この
ようなプリント配線板では熱の伝導性が悪く、良好に放
熱をすることができない。先に本発明者らは、特開昭62
−52992において、絶縁層に金属板を挿入して配設し、
この金属板の一部を外部に露出させ、放熱性を良好にし
た樹脂積層板のプリント配線板から構成された第4図に
示す半導体チップキャリアを提供した。
A printed wiring board such as an epoxy resin laminate using a glass cloth as a base material has recently been used for an insulating layer constituting a semiconductor chip carrier. However, such a printed wiring board has poor heat conductivity and cannot radiate heat well. First, the present inventors disclosed in
At -52992, a metal plate is inserted and arranged in the insulating layer,
A part of this metal plate was exposed to the outside to provide a semiconductor chip carrier shown in FIG. 4 composed of a printed wiring board of a resin laminate having good heat dissipation.

このものは、絶縁層1が金属板2の周縁部から中央よ
りの部分まで被覆し、金属板2の中央部分を中心に絶縁
層のない凹部が形成され、この凹部の底面には前記金属
板2が露出してなり、一方の第1の凹部4は放熱用に、
他方の第2の凹部5は半導体チップ7搭載用にそれぞれ
設けられてなることを特徴とする半導体チップキャリア
で、金属板2が凹部で外部に露出しているために良好な
放熱性と絶縁層1が金属板2の周縁部より中央よりの部
分まで被覆していることによりプリント配線板の絶縁層
1に配設された端子ピン3の領域より内側に挿入された
金属板2の動きを阻止し、さらに絶縁層1と金属板2に
生ずる隙間を密閉して耐湿性を高めた半導体チップキャ
リアとしたところに特徴があった。
In this device, the insulating layer 1 covers the metal plate 2 from the periphery to the center, and a concave portion without the insulating layer is formed around the central portion of the metal plate 2. 2 is exposed, and the first concave portion 4 is used for heat dissipation.
The other second recesses 5 are provided for mounting the semiconductor chip 7, respectively, and are semiconductor chip carriers. Since the metal plate 2 is exposed to the outside in the recesses, good heat dissipation and an insulating layer are provided. 1 covers the metal plate 2 from the peripheral edge to the center of the metal plate 2 to prevent the metal plate 2 inserted inside the region of the terminal pins 3 arranged on the insulating layer 1 of the printed wiring board from moving. Further, there is a feature in that a gap formed between the insulating layer 1 and the metal plate 2 is sealed to provide a semiconductor chip carrier having improved moisture resistance.

ところが、半導体チップの高速化、高集積化、高機能
化による半導体チップの発熱量の増大に伴って熱放散性
の一層優れた半導体チップキャリアの造出がますます大
きく期待される中で、絶縁層に挿入された金属板の拡大
化には、同じ絶縁層に配設される端子ピンとの接触と言
う制限があった。また、外部放熱体を前記半導体チップ
キャリアに取り付けるのに、金属板2が絶縁層1の表面
より窪んでいるために外部放熱体6の形状に制限が加わ
り、取り付け部が放熱用の凹部4より小さな外部放熱体
6に制限され、放熱量の増大をはかる外部放熱体6の形
状の自由度が小さなものであった。
However, with the increasing heat generation of semiconductor chips due to the speeding up, higher integration, and higher functionality of semiconductor chips, the creation of semiconductor chip carriers with even better heat dissipation is expected to grow more and more. The enlargement of a metal plate inserted in a layer has a limitation of contact with a terminal pin provided on the same insulating layer. In addition, when the external heat radiator is attached to the semiconductor chip carrier, the shape of the external heat radiator 6 is limited because the metal plate 2 is recessed from the surface of the insulating layer 1, and the mounting portion is formed by the heat radiating recess 4. The external heat radiator 6 is limited to a small external heat radiator 6, and has a small degree of freedom in the shape of the external heat radiator 6 for increasing the heat radiation amount.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

熱放散性をさらに一層高めるために、絶縁層に挿入さ
れる金属板の大きさを、端子ピンが配設される領域にま
で拡大した金属板を使用できるようにし、外部放熱体の
形状に加わった制限を解除するとともに、外部放熱体を
簡単に取り付けできる構造の半導体チップキャリアを提
供することにある。
In order to further enhance the heat dissipation, the size of the metal plate inserted into the insulating layer can be increased to the area where the terminal pins are provided. It is another object of the present invention to provide a semiconductor chip carrier having a structure in which the restriction can be released and an external radiator can be easily attached.

〔課題を解決するための手段〕[Means for solving the problem]

本発明は前記課題を解決するために、絶縁層に埋入さ
れた金属板、この金属板の両表面の周縁部から中央より
に絶縁層を残し、絶縁層の両面に形成された凹部、これ
ら凹部の底面に露出する前記金属板、この金属板に形成
された端子ピンの外径より大きな複数個の穴、この複数
個設けられた穴より小さな径でこの穴と同じ位置に形成
された絶縁層の貫通穴に配設された端子ピンを有するこ
とを特徴とする半導体チップキャリアを提供するもので
ある。
The present invention, in order to solve the above problems, a metal plate embedded in the insulating layer, leaving the insulating layer from the center from the peripheral edge of both surfaces of the metal plate, concave portions formed on both sides of the insulating layer, The metal plate exposed on the bottom surface of the concave portion, a plurality of holes larger than the outer diameter of the terminal pin formed in the metal plate, and an insulation formed at the same position as the hole with a smaller diameter than the plurality of holes provided. A semiconductor chip carrier having a terminal pin disposed in a through hole of a layer.

〔実施例〕〔Example〕

以下に、本発明を図面に基づいて詳しく説明する。第
1図は本発明の一実施例の斜視図、第2図は外部放熱体
を取り付けた第1図のX−Y断面図である。第2図の半
導体チップキャリアは絶縁層1に埋入された金属板2,こ
の金属板の両表面の周縁部から中央よりに絶縁層1を残
して、絶縁層1の両面に形成された凹部を有する。一方
の凹部である第1の凹部4は、外部放熱体6を取りつけ
るためのもので、金属板2が絶縁層1からはずれない程
度に絶縁層1が金属板2の周縁部から中央よりに残って
いれば良く、放熱性を向上させるのにはできるだけ広い
金属板2の露出面積を確保する形状が望ましい。他方の
凹部である第2の凹部5は、半導体チップ7を搭載する
ためのもので、この第2の凹部5の底面に露出する金属
板2に半導体チップ7を搭載すると半導体チップ7から
発生する熱は金属板2に吸収され、さらに、熱伝導性に
優れた金属板2の反対側において、第1の凹部4の底面
に取付けられた側面にフィンを有する外部放熱体6へと
移動し、熱が金属板2内にこもることなく空気中に放熱
されることになって半導体チップ7の高集積化、高機能
化、高速化に対応可能となる。
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a perspective view of one embodiment of the present invention, and FIG. 2 is an XY cross-sectional view of FIG. 1 to which an external heat radiator is attached. The semiconductor chip carrier shown in FIG. 2 has a metal plate 2 embedded in an insulating layer 1 and concave portions formed on both sides of the insulating layer 1, leaving the insulating layer 1 from the peripheral edges of both surfaces of the metal plate to the center. Having. The first concave portion 4, which is one concave portion, is for mounting the external heat radiator 6, and the insulating layer 1 is left from the peripheral edge of the metal plate 2 to the center to the extent that the metal plate 2 does not separate from the insulating layer 1. In order to improve the heat dissipation, it is desirable that the shape of the metal plate 2 be as large as possible so that the exposed area of the metal plate 2 is ensured. The second concave portion 5 serving as the other concave portion is for mounting the semiconductor chip 7, and is generated from the semiconductor chip 7 when the semiconductor chip 7 is mounted on the metal plate 2 exposed on the bottom surface of the second concave portion 5. The heat is absorbed by the metal plate 2 and further moves to the external radiator 6 having fins on the side surface attached to the bottom surface of the first concave portion 4 on the opposite side of the metal plate 2 having excellent heat conductivity. The heat is radiated into the air without remaining in the metal plate 2, so that the semiconductor chip 7 can cope with high integration, high functionality, and high speed.

第2の凹部5の底面の金属板2に搭載された半導体チ
ップ7と絶縁層1の表面に形成された導体回路11は金属
線12を介して接続され、さらに、この導体回路11は外部
端子として働く端子ピン3を挿入するための絶縁層1に
形成された貫通穴9のスルホールメッキ層に接続してい
る。
The semiconductor chip 7 mounted on the metal plate 2 on the bottom surface of the second recess 5 and the conductor circuit 11 formed on the surface of the insulating layer 1 are connected via a metal wire 12, and the conductor circuit 11 is connected to an external terminal. It is connected to a through-hole plating layer of a through hole 9 formed in the insulating layer 1 for inserting the terminal pin 3 serving as a terminal.

なお、第1の凹部4や第2の凹部5としての形状は周
知の如く四角柱状が一般的であるが、特に制限する趣旨
ではなく円柱などでもよい。
The shape of the first concave portion 4 and the second concave portion 5 is generally a quadrangular prism shape as is well known, but may be a cylindrical column without any particular limitation.

上記構成の半導体チップキャリアにおいて、金属板2
を端子ピン3の配設される領域にまで拡大させるため
に、端子ピン3が金属板2と接触しないように端子ピン
3が配設される位置に相当する金属板2の位置に端子ピ
ン3より大きな径の穴8を設ける。この穴は第2図に示
した貫通穴でもよく、第3図の他の実施例を示す拡大図
の未貫通穴10でもよく、その形状も円柱でも、四角柱で
もよく、特に限定するものではなく、端子ピン3と接触
しない大きさであれば十分である。
In the semiconductor chip carrier having the above structure, the metal plate 2
In order to extend the terminal pin 3 to the area where the terminal pin 3 is provided, the terminal pin 3 A larger diameter hole 8 is provided. This hole may be the through hole shown in FIG. 2 or the non-through hole 10 in an enlarged view showing another embodiment of FIG. 3, and the shape may be a column or a square column. However, it is sufficient if the size does not contact the terminal pins 3.

半導体チップキャリアの形態としては、端子ピン3を
外部放熱体6の取りつく面と反対の絶縁層1に形成され
た貫通穴9に配設されたものが、放熱を高めるのには好
ましい。
As the form of the semiconductor chip carrier, the one in which the terminal pins 3 are provided in the through holes 9 formed in the insulating layer 1 opposite to the surface to which the external heat radiator 6 is attached is preferable for improving heat radiation.

また、外部放熱体6の形状も角柱で側面フィンを有す
るもの、あるいは円柱で上面フィンを有するものなど一
般に放熱体、放熱フィンとして用いられているものを用
いることができる。
In addition, the shape of the external heat radiator 6 that is generally used as a heat radiator or heat radiator, such as a prism having a side surface fin or a column having a top fin, can be used.

次に、使用材料について述べると、第2図の半導体チ
ップキャリアを構成する絶縁層1は、基材に樹脂を含浸
乾燥して得られたプリプレグの樹脂を硬化した絶縁材料
が用いられる。ここで絶縁層1の樹脂としては耐熱性、
耐湿性に優れかつ樹脂純度、特にイオン性不純物の少な
いものが好ましい。具体的には、エポキシ樹脂、ポリイ
ミド樹脂、フッソ樹脂、フェノール樹脂、不飽和ポリエ
ステル樹脂、PPO樹脂などが適している。なお絶縁層1
の基材としては、紙よりガラス繊維などの無機材料の方
が耐熱性、耐湿性などに優れ好ましい。
Next, the materials used will be described. For the insulating layer 1 constituting the semiconductor chip carrier of FIG. 2, an insulating material obtained by curing a prepreg resin obtained by impregnating and drying a base material with a resin is used. Here, the resin of the insulating layer 1 has heat resistance,
Those having excellent moisture resistance and a low resin purity, particularly low ionic impurities, are preferred. Specifically, epoxy resin, polyimide resin, fluorine resin, phenol resin, unsaturated polyester resin, PPO resin and the like are suitable. Insulating layer 1
As a base material, an inorganic material such as glass fiber is more preferable than paper in terms of heat resistance and moisture resistance.

絶縁層1に挿入される金属板2や金属板2に取り付け
られる外部放熱体6としては、例えば銅板、銅合金板、
銅−インバー−銅合金板、鉄−ニッケル合金板、その他
鋼板、鉄板、アルミニウム板などを使用することができ
る。
Examples of the metal plate 2 inserted into the insulating layer 1 and the external radiator 6 attached to the metal plate 2 include a copper plate, a copper alloy plate,
Copper-invar-copper alloy plates, iron-nickel alloy plates, other steel plates, iron plates, aluminum plates, and the like can be used.

〔発明の効果〕〔The invention's effect〕

本発明に係る半導体チップキャリアは叙述の如く、絶
縁層に挿入される金属板の大きさを、端子ピンが配設さ
れる領域にまで拡大した金属板とすることができ、露出
して外部放熱体と接合する金属板の部分が大きくなるた
め、外部放熱体の形状に加わった制限を解除することが
できると伴に、外部放熱体を簡単に取り付けできる構造
の半導体チップキャリアとなり、半導体チップの高集積
化、高機能化、高速化によって増大する発熱に対応可能
な半導体チップキャリアとなるものである。
As described above, the semiconductor chip carrier according to the present invention can be a metal plate in which the size of the metal plate inserted into the insulating layer is enlarged to the area where the terminal pins are provided, and the metal plate is exposed to external heat radiation. Since the size of the metal plate that joins the body becomes larger, the restriction imposed on the shape of the external heat radiator can be released, and the semiconductor chip carrier has a structure that allows the external heat radiator to be easily attached. It is a semiconductor chip carrier that can cope with heat generated by high integration, high functionality, and high speed.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の一実施例を示す斜視図、 第2図はそのX−Y断面図に外部放熱体が取り付けられ
たもの 第3図は他の実施例を示す部分拡大の断面図、 第4図は一従来例の断面図をそれぞれ示す。 1……絶縁層、2……金属板 3……端子ピン、4……第1の凹部 5……第2の凹部、6……外部放熱体 7……半導体チップ、8……穴 9……貫通穴
FIG. 1 is a perspective view showing one embodiment of the present invention, FIG. 2 is an XY cross-sectional view in which an external heat radiator is attached, FIG. 3 is a partially enlarged cross-sectional view showing another embodiment, FIG. 4 is a sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1 ... Insulating layer, 2 ... Metal plate 3 ... Terminal pin 4, 4 ... First concave part 5 ... Second concave part, 6 ... External radiator 7 ... Semiconductor chip, 8 ... Hole 9 ... … Through hole

───────────────────────────────────────────────────── フロントページの続き (72)発明者 加納 武司 大阪府門真市大字門真1048番地 松下電 工株式会社内 (72)発明者 樋口 徹 大阪府門真市大字門真1048番地 松下電 工株式会社内 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Takeshi Kano 1048 Odakadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Works, Ltd. (72) Inventor Toru Higuchi 1048 Odaka, Kadoma, Osaka Prefecture

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁層に埋入された金属板、この金属板の
両表面の周縁部から中央よりに絶縁層を残し、絶縁層の
両面に形成された凹部、これら凹部の底面に露出する前
記金属板、この金属板に形成された端子ピンの外径より
大きな複数個の穴、この複数個設けられた穴より小さな
径でこの穴と同じ位置に形成された絶縁層の貫通穴に配
設された端子ピンを有することを特徴とする半導体チッ
プキャリア。
1. A metal plate embedded in an insulating layer, concave portions formed on both surfaces of the insulating layer, leaving the insulating layer from the peripheral edge of both surfaces of the metal plate toward the center, and exposed on the bottom surfaces of these concave portions. The metal plate, a plurality of holes larger than the outer diameter of the terminal pins formed in the metal plate, and a through hole of the insulating layer formed at the same position as the hole with a smaller diameter than the plurality of holes. A semiconductor chip carrier having provided terminal pins.
JP1330255A 1989-12-20 1989-12-20 Semiconductor chip carrier Expired - Lifetime JP2658451B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1330255A JP2658451B2 (en) 1989-12-20 1989-12-20 Semiconductor chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1330255A JP2658451B2 (en) 1989-12-20 1989-12-20 Semiconductor chip carrier

Publications (2)

Publication Number Publication Date
JPH03190265A JPH03190265A (en) 1991-08-20
JP2658451B2 true JP2658451B2 (en) 1997-09-30

Family

ID=18230596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1330255A Expired - Lifetime JP2658451B2 (en) 1989-12-20 1989-12-20 Semiconductor chip carrier

Country Status (1)

Country Link
JP (1) JP2658451B2 (en)

Also Published As

Publication number Publication date
JPH03190265A (en) 1991-08-20

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