JPH0318817A - Active matrix array - Google Patents
Active matrix arrayInfo
- Publication number
- JPH0318817A JPH0318817A JP15336089A JP15336089A JPH0318817A JP H0318817 A JPH0318817 A JP H0318817A JP 15336089 A JP15336089 A JP 15336089A JP 15336089 A JP15336089 A JP 15336089A JP H0318817 A JPH0318817 A JP H0318817A
- Authority
- JP
- Japan
- Prior art keywords
- picture element
- signal line
- potential
- adjacent
- active matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 title claims description 14
- 230000003071 parasitic effect Effects 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims abstract description 4
- 239000010409 thin film Substances 0.000 abstract description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、液晶表示パネル、或いは液晶ライトバルブな
どに用いることのできるアクティブマトリックスアレイ
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an active matrix array that can be used in liquid crystal display panels, liquid crystal light valves, and the like.
従来の技術
従来アクティブマトリックスアレイの基本的な構成は第
3図に示すように、多数の走査線Xnと信号線Ymとそ
の交差点に配置された絵素電極Pnm、及び各絵素電極
に接続され、走査線で制御されるスイッチ素子Tnm(
同図では薄膜トランジスタ)より成る。絵素電極と対向
共通電極の間には液晶が挿入されており絵素電極に与え
られる電位で液晶の電気光学特性が制御される。また、
各絵素電極Pnmは対向共通電極との間に静電容lcn
mを形成しており(同図では示していない)、この容量
により絵素電極の電位がある時間にわたって保持される
ことがアクティブマトリックス方式の要件のひとつであ
る。つまり、スイッチング素子Tnmが走査線Xnによ
って選択され、信号線Ymの電位が絵素Pnmに与えら
れた後、スイッチング素子Tnmの非遺沢時の抵抗(同
図ではトランジスタのオフ抵抗)と、静電容量Cnmと
によって決まる時定数τで絵素の電位は変化していくこ
とになる。したがって、走査線の非選択時間に対して時
定数が十分大きけれは絵素の電位は保持される。2. Description of the Related Art As shown in FIG. 3, the basic configuration of a conventional active matrix array is as shown in FIG. , the switching element Tnm (
In the figure, it consists of a thin film transistor). A liquid crystal is inserted between the picture element electrode and the opposing common electrode, and the electro-optical characteristics of the liquid crystal are controlled by the potential applied to the picture element electrode. Also,
Each picture element electrode Pnm has a capacitance lcn between it and the opposing common electrode.
One of the requirements of the active matrix method is that the potential of the picture element electrode is maintained for a certain period of time by this capacitance. In other words, after switching element Tnm is selected by scanning line The potential of the picture element changes with a time constant τ determined by the capacitance Cnm. Therefore, as long as the time constant is sufficiently large for the non-selection time of the scanning line, the potential of the picture element is maintained.
しかし、実際のアクティブマトリックスアレイでは、ス
イッチング素子の構造や製造プロセスなどにより、いろ
いろな寄生容量が発生し、上記の絵素電圧を変動させる
原因となる。特に信号線Ymと絵素電極Pnm間に発生
する寄生容置Cspは、信号線Ymの電位変化Δ■に対
して、ΔVX(Csp/Cnm)だけ絵素電位を変動さ
せることになるため、表示画像の品質に大きな影響を与
える。第4図は、Cspの表示画像の上下輝度差への影
響を説明する為の絵素電位のタイミングチャートである
。この同図は、薄膜トランジスタアレイを有する液晶素
子を駆動するときの一般的なタイミングチャートであり
、駆動方法である。つまり、液晶は交流で駆動する必要
があるため、信号線電位は共通電極に対して一画面毎に
極性を反転する方法である。同図では、信号として一定
電圧を与えた場合の走査線選択時間の差による各画素の
電位変化を示している。Cspを考慮した場合、同図か
ら解るように信号線電位の極性が一画面毎に反転したと
き、その変化に応じて前述した計算式の分だけ絵素電位
に変化を与える。However, in an actual active matrix array, various parasitic capacitances occur due to the structure of the switching elements, manufacturing process, etc., which causes the above-mentioned pixel voltage to fluctuate. In particular, the parasitic capacitor Csp that occurs between the signal line Ym and the picture element electrode Pnm causes the picture element potential to fluctuate by ΔVX (Csp/Cnm) with respect to the potential change Δ■ of the signal line Ym. It has a big impact on the quality of the image. FIG. 4 is a timing chart of picture element potentials for explaining the influence of Csp on the upper and lower luminance difference of a displayed image. This figure is a general timing chart and driving method when driving a liquid crystal element having a thin film transistor array. In other words, since the liquid crystal needs to be driven with alternating current, the polarity of the signal line potential is reversed for each screen with respect to the common electrode. This figure shows the potential change of each pixel due to the difference in scanning line selection time when a constant voltage is applied as a signal. When considering Csp, as can be seen from the figure, when the polarity of the signal line potential is reversed for each screen, the picture element potential is changed by the amount calculated by the above-mentioned calculation formula in accordance with the change.
この変化は、常に液晶にかかる電圧を低下させる方向に
働く、また、図からも明らかなように信号線電位の反転
後すぐに選択される絵素(表示画面では上に当たる)と
、選択された後すぐに信号線電位の反転が起こる絵素(
表示画面では下に当たる)では、液晶にかかっている実
効電圧(′/&晶にかかっている電圧の2乗の時間平均
値)に差が生じる。これによって画面上下での輝度差が
発生することになる。また、信号線電位の変化によって
絵素電位が影響されるので、階調性も大きく低下させる
原因となる。This change always acts in the direction of lowering the voltage applied to the liquid crystal, and as is clear from the figure, the picture element that is selected immediately after the signal line potential is reversed (corresponding to the top on the display screen), and the selected pixel A picture element where the signal line potential is reversed immediately after (
(at the bottom of the display screen), there is a difference in the effective voltage applied to the liquid crystal ('/& the time average value of the square of the voltage applied to the crystal). This causes a difference in brightness between the top and bottom of the screen. Furthermore, since the pixel potential is affected by changes in the signal line potential, this causes a large reduction in gradation.
ところで、この信号線と絵素間容量は、トランジスタの
チャンネル部の形状や、特にa−3iを活性層としたト
ランジスタの光遮蔽層等によって発生し、完全にその容
量をなくする困難である。Incidentally, this capacitance between the signal line and the picture element is generated due to the shape of the channel portion of the transistor, especially the light shielding layer of the transistor with a-3i as the active layer, and it is difficult to completely eliminate this capacitance.
さらに、−絵素のサイズを細かくし高密度・高精細にし
た場合、液晶の容量Cnmが小さくなり等価的にCsp
/Cnmの値が大きくなり、結果として画質に大きく影
響するという問題がある。Furthermore, - When the size of picture elements is made finer to achieve high density and high definition, the capacitance Cnm of the liquid crystal decreases and equivalently Csp
There is a problem in that the value of /Cnm becomes large, and as a result, image quality is greatly affected.
発明が解決しようとする課題
本発明の課題は、アクティブマトリックス方式液晶表示
素子において、その問題点である信号線と絵素電極間容
量のもたらす画質低下を大きく低減し、高品質の表示が
可能となるアクティブマトリックスアレイを徒供するこ
とにある。Problems to be Solved by the Invention An object of the present invention is to significantly reduce the image quality deterioration caused by the capacitance between the signal line and the pixel electrode, which is a problem in active matrix type liquid crystal display elements, and to enable high-quality display. The purpose is to provide an active matrix array.
課題を解決するための手段
前記課題を解決するために本発明のアクティブマトリッ
クスアレイは、複数の走査線(ゲート線)と信号線(ソ
ース線)、各交差点に対応して設けた絵素電極、及び各
絵素電極に接続され、各絵素電極に接続された少なくと
も1つのスイッチング素子と、各絵素電極とそれに隣合
う2本の信号線間に発生する容量を等しく成るように構
成したものであり、かつ、互いに隣合う信号線の電圧の
極性を逆にして駆動する方式としたものである。Means for Solving the Problems In order to solve the above problems, the active matrix array of the present invention includes a plurality of scanning lines (gate lines) and signal lines (source lines), pixel electrodes provided corresponding to each intersection, and at least one switching element connected to each picture element electrode, configured to equalize the capacitance generated between each picture element electrode and two signal lines adjacent thereto. This is a method in which the polarities of the voltages of adjacent signal lines are reversed and driven.
作用
前述した構成のように、絵素電極とそれに隣合う2本の
信号線間に発生する寄生容量をほぼ同一になるようにし
、かつ、互いに隣合う信号線電位の極性を逆にして駆動
することによって、−画面走査時の信号線電位の反転方
向を隣合う信号線で逆とし画素電位の変動を相殺するも
のであり、輝度差のない高画質表示が可能となる。Function: As in the above-mentioned configuration, the parasitic capacitance generated between the picture element electrode and the two adjacent signal lines are made almost the same, and the polarities of the adjacent signal line potentials are reversed for driving. By doing this, the inversion direction of the signal line potential during screen scanning is reversed between adjacent signal lines to cancel out fluctuations in pixel potential, and high-quality display without brightness difference is possible.
実施例
第1図は本発明に関わる実施例のアクティブマトリック
スアレイの等価回路を示したものである。Embodiment FIG. 1 shows an equivalent circuit of an active matrix array according to an embodiment of the present invention.
第1図において、Tnmは薄膜トランジスタを示してい
る。Xn、Ymはそれぞれ走査線、信号線を示している
0本構成は、各絵素に対して1つの薄膜トランジスタを
形成し、同時に各絵素の隣接する第2の信号線間にトラ
ンジスタのソース・ドレイン間寄生容量とほぼ同じコン
デンサを形成したものである。具体的には、Tnmに対
応する同一のトランジスタのゲート電極及び半導体層を
取り除いた構成のものを隣接信号線と絵素間に作成して
いる。第2図は第1図の構成の薄膜トランジスタアレイ
を用いて1絵素10100(pピッチのサイズで、80
0X80Q絵素の液晶表示パネルを、本発明に記載の駆
動方式、つまり、一画面走査ごとに信号線の電位極性を
対向共通電位に対して反転すると共に、隣合う信号線同
志の電位は逆極性とする(以下信号線反転と呼ぶ)とい
う方法で駆動したときの画面上下での電圧−輝度特性を
示したものである0図から明らかなように、画面上下で
の特性差を発生していないことがわかる。In FIG. 1, Tnm indicates a thin film transistor. Xn and Ym indicate a scanning line and a signal line, respectively. In the 0-line configuration, one thin film transistor is formed for each picture element, and at the same time, the transistor's source and This is a capacitor that is approximately the same as the parasitic capacitance between the drains. Specifically, a configuration in which the gate electrode and semiconductor layer of the same transistor corresponding to Tnm are removed is created between the adjacent signal line and the picture element. FIG. 2 shows a thin film transistor array having the configuration shown in FIG.
A liquid crystal display panel with 0X80Q picture elements is driven by the driving method described in the present invention, that is, the potential polarity of the signal line is inverted with respect to the opposing common potential for each screen scan, and the potentials of adjacent signal lines are of opposite polarity. As is clear from Figure 0, which shows the voltage-luminance characteristics at the top and bottom of the screen when driven using the method of driving the screen using the method of driving the screen (hereinafter referred to as signal line inversion), there is no difference in characteristics between the top and bottom of the screen. I understand that.
これは、前述したように、トランジスタのソース・ドレ
イン間寄生容量の影響を、信号線反転駆動によって相殺
したことによるものである。This is because, as described above, the influence of the parasitic capacitance between the source and drain of the transistor is offset by the signal line inversion drive.
発明の効果
以上述べたように、本発明は、各絵素電極とそれに隣合
う2本の信号線間に発生する寄生容量をほぼ同一になる
ようにし、かつ、互いに隣合う信号線電位の極性を逆に
して駆動するこきによって、輝度差のない高画質表示を
可能とするものである。Effects of the Invention As described above, the present invention makes the parasitic capacitances generated between each picture element electrode and two adjacent signal lines almost the same, and also changes the polarity of the signal line potentials adjacent to each other. By reversing the drive direction, it is possible to display high-quality images with no difference in brightness.
第1図は本発明に関わる第1の実施例のアクティブマト
リックスアレイの回路構成の説明図、第2図は第1図の
回路構成で、本発明に関わる駆動方法で動作させたとき
の、液晶表示パネルの電圧輝度特性を示している。第3
図は従来のアクティブマトリックスアレイの典型例を示
す説明図、第4図はアクティブマトリックスアレイの典
型的な駆動方法の説明図である。
Xn・・・・・・走査線、Ym・・・・・・信号線、P
nm・・・・・・絵素電極。FIG. 1 is an explanatory diagram of the circuit configuration of an active matrix array according to a first embodiment of the present invention, and FIG. 2 shows the circuit configuration of FIG. It shows the voltage-luminance characteristics of the display panel. Third
The figure is an explanatory diagram showing a typical example of a conventional active matrix array, and FIG. 4 is an explanatory diagram of a typical driving method of the active matrix array. Xn...Scanning line, Ym...Signal line, P
nm...Picture element electrode.
Claims (2)
、各交差点に対応して設けた絵素電極、及び各絵素電極
に接続されたスイッチング素子より成り、各絵素電極と
、それに相隣合う2本の信号線間に発生する容量を等し
くし互いに隣合う信号線の電圧の極性を逆にして駆動す
ることを特徴とするアクティブマトリックスアレイ。(1) Multiple scanning lines (gate lines) and signal lines (source lines)
, consists of a picture element electrode provided corresponding to each intersection, and a switching element connected to each picture element electrode, and equalizes the capacitance generated between each picture element electrode and two adjacent signal lines. An active matrix array characterized by driving adjacent signal lines with opposite polarities of voltage.
記絵素電極間にはスイッチング素子を形成し、それに対
応する第2の信号線と前記絵素電極間には、前記スイッ
チング素子の形成によって絵素−信号線間に発生する寄
生容量と同一のコンデンサを形成したことを特徴とする
請求項1記載のアクティブマトリックスアレイ。(2) With respect to the picture element electrode, a switching element is formed between the adjacent first signal line and the picture element electrode, and a switching element is formed between the corresponding second signal line and the picture element electrode. 2. The active matrix array according to claim 1, wherein a capacitor is formed which is the same as a parasitic capacitance generated between the picture element and the signal line by forming the switching element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15336089A JPH0318817A (en) | 1989-06-15 | 1989-06-15 | Active matrix array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15336089A JPH0318817A (en) | 1989-06-15 | 1989-06-15 | Active matrix array |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0318817A true JPH0318817A (en) | 1991-01-28 |
Family
ID=15560753
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15336089A Pending JPH0318817A (en) | 1989-06-15 | 1989-06-15 | Active matrix array |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0318817A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0815670A (en) * | 1994-06-28 | 1996-01-19 | Nec Corp | Active matrix liquid crystal display device |
JPH0922023A (en) * | 1995-07-06 | 1997-01-21 | Toshiba Corp | Active matrix liquid crystal display device |
-
1989
- 1989-06-15 JP JP15336089A patent/JPH0318817A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0815670A (en) * | 1994-06-28 | 1996-01-19 | Nec Corp | Active matrix liquid crystal display device |
JPH0922023A (en) * | 1995-07-06 | 1997-01-21 | Toshiba Corp | Active matrix liquid crystal display device |
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