JPH03187248A - Semiconductor package structure - Google Patents
Semiconductor package structureInfo
- Publication number
- JPH03187248A JPH03187248A JP1326642A JP32664289A JPH03187248A JP H03187248 A JPH03187248 A JP H03187248A JP 1326642 A JP1326642 A JP 1326642A JP 32664289 A JP32664289 A JP 32664289A JP H03187248 A JPH03187248 A JP H03187248A
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- glass
- wiring
- semiconductor package
- glass plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000011521 glass Substances 0.000 claims abstract description 66
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 37
- 239000000919 ceramic Substances 0.000 abstract description 28
- 239000000853 adhesive Substances 0.000 abstract description 8
- 230000001070 adhesive effect Effects 0.000 abstract description 8
- 230000006866 deterioration Effects 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 abstract 1
- 239000005357 flat glass Substances 0.000 abstract 1
- 238000002844 melting Methods 0.000 description 10
- 230000008018 melting Effects 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 238000005219 brazing Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 239000011261 inert gas Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 2
- 241001508691 Martes zibellina Species 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Non-Volatile Memory (AREA)
- Light Receiving Elements (AREA)
- Liquid Crystal (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ガラスフタまたは、ガラス窓を有する半導
体パッケージの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor package having a glass lid or a glass window.
第4図は従来のガラス窓を有する半導体セラミックパッ
ケージの側断面図である。図において、il+は半導体
素子、(2)は半導体素子(1)をダイスパッド部(3
a)に固定するための半田等のロー材もしくは導電性接
着剤より成るグイボンド材、(3)はリードフレーム、
(3a)は半導体素子(1)を固定する場所であるダイ
スパッド部、(3b)はインナーリード部、(3c)は
この半導体パッケージを配線基板等に実装するための外
部リード、(4)は半導体素子(1)とインナーリード
部(3b)とを電気的接続を可能とするためのAuまた
はA1等より成る金属細線、(5)はリードフレーム(
3)を固定し、かつ、半導体素子(1)を保護するため
のセラミックベース、(6)はセラミックベース(5)
と同様に半導体素子(1)を保護するためのセラミック
フタ、αDはセラミックフタ(6)に低融点ガラスを用
いて組み込まれ、パッケージ内部に光を通すために設け
られたガラス窓、(8)はセラミックベース(5)とセ
ラミックフタ(6)とを接着し、かつ、パッケージ内部
を外界より保護し、内部に不活性ガス等を密封するため
の低融点ガラスである。FIG. 4 is a side sectional view of a conventional semiconductor ceramic package with a glass window. In the figure, il+ is the semiconductor element, (2) is the semiconductor element (1), and the die pad part (3) is the semiconductor element (2).
(3) is a lead frame; (3) is a lead frame;
(3a) is the die pad section where the semiconductor element (1) is fixed, (3b) is the inner lead section, (3c) is the external lead for mounting this semiconductor package on a wiring board, etc., and (4) is the die pad section where the semiconductor element (1) is fixed. A thin metal wire made of Au or A1, etc., to enable electrical connection between the semiconductor element (1) and the inner lead part (3b), (5) is a lead frame (
3) is a ceramic base for fixing and protecting the semiconductor element (1), (6) is a ceramic base (5)
Similarly, a ceramic lid for protecting the semiconductor element (1), αD, is incorporated into the ceramic lid (6) using low melting point glass, and a glass window (8) is provided to pass light into the package. is a low melting point glass used to bond the ceramic base (5) and the ceramic lid (6), protect the inside of the package from the outside world, and seal inert gas etc. inside.
次に動作について説明する。パターニングして形成され
たリードフレーム(3)を低融点ガラス(8)によって
セラミックベース(5)に接着する。この時ダイスパッ
ド部(3a)もセラミックベース(5)の凹部に接着さ
れる。次いで、半導体素子(1)をダイスパッド部(3
a)に例えば半田等ロー材ダイスボンド材(2)を溶融
・凝固により接着する。次いで、半導体素子(11上の
外部電極であるボンディングパッドトインナーリード部
(3b)とを金属細線(4)を用いて接続する。この時
接続は、金属細線(4)がAuより成るときは熱と超音
波併用型、また金属細線(4)がAIより戊るときは超
音波のみの2つの方式があり、どちらかの方法でボンデ
ィングとインナーリード部(3b)が金属細線(4)に
よって接着される。次いで、低融点ガラスによってガラ
ス窓αυが組み込まれているセラミックフタ(6)を、
低融点ガラス(8)を用いてセラミックベース(5)、
リードフレーム(3)と接着する。この時不活性ガス雰
囲気内で接着を行なうため、パッケージ内部は不活性ガ
ス雰囲気となり半導体素子(11、金属細線(4)の酸
化防止等の効果がある。Next, the operation will be explained. The patterned lead frame (3) is bonded to the ceramic base (5) with a low melting point glass (8). At this time, the die pad portion (3a) is also bonded to the recessed portion of the ceramic base (5). Next, the semiconductor element (1) is placed on the die pad portion (3).
A brazing die bonding material (2) such as solder is bonded to a) by melting and solidifying. Next, the bonding pad inner lead part (3b) which is an external electrode on the semiconductor element (11) is connected using a thin metal wire (4). At this time, when the thin metal wire (4) is made of Au, There are two methods: a combination of heat and ultrasonic waves, and only ultrasonic waves when the thin metal wire (4) is removed from the AI. Then, a ceramic lid (6) in which a glass window αυ is assembled with low melting point glass is attached.
Ceramic base (5) using low melting point glass (8),
Adhere to lead frame (3). At this time, since the bonding is performed in an inert gas atmosphere, the inside of the package becomes an inert gas atmosphere, which has the effect of preventing oxidation of the semiconductor element (11) and the thin metal wire (4).
ガラス窓が紫外線透過型で半導体素子のデータか紫外線
によって消去可能である半導体素子UPROM(Bra
sable Programable Read 0n
ly Memory)等を収めた従来の半導体パッケー
ジは以上のように構成されるので、消去したくないデー
タが記憶されている場合は、ガラス窓の上に紫外線を通
さないシールを貼り付けていたため、何回も消去、デー
タ記憶を繰り返すことによって接着剤の劣化、ガラス窓
に接着剤等の異物の付着による洗浄の必要性、消去不十
分等の問題点があった。A semiconductor device UPROM (Bra
sable Programmable Read 0n
Conventional semiconductor packages containing such things as lyMemory are constructed as described above, so if data that you do not want to erase is stored, a sticker that does not transmit ultraviolet rays is pasted on the glass window. There have been problems such as deterioration of the adhesive due to repeated erasing and data storage, the need for cleaning due to adhesion of foreign substances such as adhesive to the glass window, and insufficient erasing.
この発明は上記のような問題点を解消するためになされ
たもので、容易に紫外線もしくは光を入射・しゃ断でき
るとともに、接着剤等の異物付着を回避できる半導体パ
ッケージを得ることを目的とする。This invention was made to solve the above-mentioned problems, and aims to provide a semiconductor package that can easily inject and block ultraviolet rays or light and can avoid adhesion of foreign substances such as adhesives.
この発明に係る半導体パッケージは、ガラス窓の代わり
に液晶ガラス板を用い、電圧のON、 OFFにより光
の入射、しゃ断を可能にしたものである。The semiconductor package according to the present invention uses a liquid crystal glass plate instead of a glass window, and allows light to enter or shut off by turning on and off a voltage.
この発明における半導体パッケージはガラス窓に液晶ガ
ラス板を用いたことにより、半導体素子上への光の入射
、しゃ断を液晶ガラス板のON、 OFFにより可能と
した。The semiconductor package according to the present invention uses a liquid crystal glass plate for the glass window, so that light can be incident on or blocked from the semiconductor element by turning the liquid crystal glass plate ON or OFF.
以下、この発明の一実施例を図について説明する。第1
図は半導体パッケージ構造を示す側断面図である。図に
おいて、(1)〜(3)、(3a)〜(3c)、(4)
〜(6)、(8)は第4図の従来例に示したものと同等
であるので説明を省略する。(6a)はセラミックフタ
(6)の内側面に設けられた電気的導通の可能なセラミ
ック配線、(7)はセラミックフタ(6)に取り付けら
れた液晶ガラス板、(7a)は液晶ガラス板(7)の上
ガラス、(7b)は液晶ガラス板(7)の下ガラス、(
7C)は上ガラス(7b)上に設けられた上ガラス配線
、(7d)は下ガラス(7b)上に設けられた下ガラス
配線、(7e)は液晶、(9)は液晶ガラス板(7)を
ON、 OFFさせるために、液晶ガラス板(7)とリ
ードフレーム(3)とを電気的に接続可能とするための
接続リード、aωは接続リード(9)をリードフレーム
(3)またはセラミックフタ配線(6a)に固定させる
ために用いられる半田等より成るロー材である。第2図
および第3図は第1図の半導体パッケージ構造に示す液
晶ガラス板(7)について他の実施例を示すもので、第
2図はアレイ状パターンの場合、第3図はカラーフィル
ターを用いた場合を示す液晶ガラス板の上面図である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a side sectional view showing a semiconductor package structure. In the figure, (1) to (3), (3a) to (3c), (4)
Since steps (6) and (8) are the same as those shown in the conventional example shown in FIG. 4, their explanations will be omitted. (6a) is a ceramic wiring capable of electrical conduction provided on the inner surface of the ceramic lid (6), (7) is a liquid crystal glass plate attached to the ceramic lid (6), and (7a) is a liquid crystal glass plate ( 7) is the upper glass, (7b) is the lower glass of the liquid crystal glass plate (7), (
7C) is the upper glass wiring provided on the upper glass (7b), (7d) is the lower glass wiring provided on the lower glass (7b), (7e) is the liquid crystal, and (9) is the liquid crystal glass plate (7). ) is a connecting lead that enables electrical connection between the liquid crystal glass plate (7) and the lead frame (3), and aω is the connecting lead (9) connected to the lead frame (3) or ceramic This is a brazing material made of solder or the like used for fixing to the lid wiring (6a). Figures 2 and 3 show other embodiments of the liquid crystal glass plate (7) shown in the semiconductor package structure of Figure 1. Figure 2 shows an array pattern, and Figure 3 shows a color filter. It is a top view of the liquid crystal glass plate which shows the case where it is used.
図において(7a)、(7b)、(7e)は第1図に示
したものと同等である。(7f)は赤液晶、(7g)は
青液晶、(7h)は緑液晶である。In the figure, (7a), (7b), and (7e) are equivalent to those shown in FIG. (7f) is a red liquid crystal, (7g) is a blue liquid crystal, and (7h) is a green liquid crystal.
次に動作について説明する。パターニングして形成され
たリードフレーム(3)を低融点ガラス(8)によって
セラミックベース(5)に接着する。この時ダイスパッ
ド部(3a)もセラミックベース(5)の凹部に接着さ
れる。次いで、半導体素子(1)をダイスパッド部(3
a)に例えば半田等ロー材より成るグイボンド材(2)
を溶融・凝固により接着する。次いで、半導体素子(1
)上の外部電極であるポンディングパッドとインナーリ
ード部(3b)とを金属細線(4)を用いて接続する。Next, the operation will be explained. The patterned lead frame (3) is bonded to the ceramic base (5) with a low melting point glass (8). At this time, the die pad portion (3a) is also bonded to the recessed portion of the ceramic base (5). Next, the semiconductor element (1) is placed on the die pad portion (3).
Guibond material (2) made of brazing material such as solder in a)
Adhere by melting and solidifying. Next, the semiconductor element (1
) and the inner lead portion (3b) are connected using a thin metal wire (4).
この時、接続は金属細線(4ンがAuより成るときは熱
と超音波併用型、また金属細線(4)がAIより成ると
きは超音波のみの2つの方式(両方式とも荷重も条件の
1つ)があり、どちらかの方法で、ポンディングパッド
とインナーリード部(3a)が金属細線(4)によって
接続せれる。次いで、あらかじめ製作されている液晶ガ
ラス板(7)をセラミックフタ(6)に接着する。この
時、下ガラス配線(7d)とセラミックフタ配線(6a
)とは、決められた位置に接続され、正常に液晶が動作
する様にしなければならない。また、パッケージ内部の
信頼性は、液晶ガラス板(7)とセラミックフタ(6)
と接着する接着剤によって保たれる。次いで、セラミッ
クフタ配線(6a)の所定の位置にロー材0ωによって
接続リード(9)が接着される。この接続リード(9)
は、インナーリード部(3b)と接続されるため、所定
の位置に接着される。次いで、ロー材叫により接続リー
ド(9)とインナーリード部(3b)が接続され、低融
点ガラス(8)により、セラミックベース(5)とリー
ドフレーム(3)とが接着される。この時不活性ガス雰
囲気内で接着されるのは従来技術通りである。At this time, the connection can be made using two methods: a combination of heat and ultrasound when the thin metal wire (4) is made of Au, and only ultrasonic when the thin metal wire (4) is made of AI (both methods meet the load and conditions). In either method, the bonding pad and the inner lead part (3a) are connected by a thin metal wire (4).Next, the prefabricated liquid crystal glass plate (7) is attached to a ceramic lid ( 6).At this time, attach the lower glass wiring (7d) and the ceramic lid wiring (6a).
) must be connected to the specified position so that the liquid crystal can operate normally. In addition, the reliability of the inside of the package is determined by the liquid crystal glass plate (7) and ceramic lid (6).
It is held together by an adhesive. Next, the connection lead (9) is bonded to a predetermined position of the ceramic lid wiring (6a) using a brazing material 0ω. This connection lead (9)
is connected to the inner lead part (3b) and is therefore glued at a predetermined position. Next, the connection lead (9) and the inner lead part (3b) are connected with brazing material, and the ceramic base (5) and lead frame (3) are bonded with the low melting point glass (8). At this time, bonding is performed in an inert gas atmosphere as in the prior art.
以上のように構成されているので、半導体素子(1)よ
り出された信号により液晶ガラス板(7)が0N10F
Fの切換えが可能となることによって、毎回接着シール
をはがしたりすることなく、半導体素子(1)内の記憶
素子部の光消去可能な部分は、記憶した内容を消すこと
が可能となる。また、上記実施例では、特に消したい内
容の部分を特定しない場合について説明したが、第2図
に示す様に、液晶ガラス板(7)のON、 OFFでき
るパターンをアレイ状に並べることによって、特定部位
の記憶内容のみを消去可能としてもよい。With the above configuration, the liquid crystal glass plate (7) is set to 0N10F by the signal output from the semiconductor element (1).
By being able to switch F, the stored contents can be erased from the photo-erasable portion of the memory element section in the semiconductor element (1) without having to peel off the adhesive seal every time. Furthermore, in the above embodiment, a case was explained in which the part of the content to be erased is not specified, but as shown in FIG. It may also be possible to erase only the memory contents of a specific part.
また、フォトダイオードを用いたような半導体素子(1
1を用いたパッケージにおいて、第3図に示す様に液晶
ガラス板(7)にカラーフィルター(色の3元色)を用
いることによって、オートホワイトバランスのようなパ
ッケージも可能である。これによって、半導体素子(1
)の表面にカラーフィルターを形成する必要がなくなる
ため工程の簡素化、コストの低減等が計れる。In addition, semiconductor devices such as those using photodiodes (1
In a package using 1, as shown in FIG. 3, by using a color filter (three-dimensional color) on the liquid crystal glass plate (7), a package with automatic white balance is also possible. As a result, the semiconductor element (1
) Since it is no longer necessary to form a color filter on the surface of the film, the process can be simplified and costs can be reduced.
以上のようにこの発明によれば、ガラスフタ、または、
ガラス窓を有する半導体パッケージにおいて、ガラスに
液晶ガラス板を用いたことにより、電気的に液晶ガラス
板のON、 OFFを可能にし、光消去型半導体素子も
電気的に消去が可能となり、かつ、任意の部分のみを消
去することも可能となった。また、液晶ガラス板にカラ
ーフィルターを用いることによって、オートホワイトバ
ランスのような機能をもたせることも可能であり、工程
の簡略化及びコストの低減が可能となる。As described above, according to the present invention, the glass lid or
In a semiconductor package with a glass window, by using a liquid crystal glass plate as the glass, it is possible to electrically turn on and off the liquid crystal glass plate, and it is also possible to electrically erase a light-erasable semiconductor element, and it is also possible to erase it arbitrarily. It is now possible to erase only that part. Further, by using a color filter in the liquid crystal glass plate, it is possible to provide a function such as automatic white balance, which enables process simplification and cost reduction.
第1図はこの発明の一実施例による半導体パッケージ構
造を示す側断面図、第2図及び第3図は第1図の半導体
パッケージ構造の液晶ガラス板について他の実施例を示
すもので、第2図はアレイ状パターンの場合、第3図は
カラーフィルターを用いた場合を示す液晶ガラス板の上
面図、第4図は従来の半導体パッケージ構造を示す側断
面図である。図において、(1)は半導体素子、(2)
はグイボンド材、(3)はリードフレーム、(3a)は
ダイスパッド部、(3b)はインナーリード部、(3C
)は外部リード、(4)は金属細線、(5)はセラミッ
クベース、(6)はセラミックフタ、(6a)はセラミ
ックフタ配線、(7)は液晶ガラス板、(7a)は上ガ
ラス、(7b)は下ガラス、(7c)は上ガラス配線、
(7d)は下ガラス配線、(7e)は液晶、(8)は低
融点ガラス、(9)は接続リード、αωはロー材である
。なお、図中、同一符号は同−又は相当部分を示す。FIG. 1 is a side sectional view showing a semiconductor package structure according to one embodiment of the present invention, and FIGS. 2 and 3 show other embodiments of the liquid crystal glass plate of the semiconductor package structure of FIG. 2 is a top view of a liquid crystal glass plate showing an array pattern, FIG. 3 is a top view of a liquid crystal glass plate showing a case of using a color filter, and FIG. 4 is a side sectional view showing a conventional semiconductor package structure. In the figure, (1) is a semiconductor element, (2)
is Guibond material, (3) is lead frame, (3a) is die pad part, (3b) is inner lead part, (3C
) is an external lead, (4) is a thin metal wire, (5) is a ceramic base, (6) is a ceramic lid, (6a) is a ceramic lid wiring, (7) is a liquid crystal glass plate, (7a) is an upper glass, ( 7b) is the lower glass wiring, (7c) is the upper glass wiring,
(7d) is the lower glass wiring, (7e) is the liquid crystal, (8) is the low melting point glass, (9) is the connection lead, and αω is the brazing material. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ジにおいて、ガラス板に液晶ガラスを用い液晶をON、
OFFすることによって、光をパッケージ内部に通すか
、通さないかの切換えを可能にしたことを特徴とする半
導体パッケージ構造。In semiconductor packages with glass lids or glass windows, liquid crystal glass is used on the glass plate and the liquid crystal is turned on.
A semiconductor package structure characterized in that by turning OFF, it is possible to switch between passing light into the package or not.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1326642A JPH03187248A (en) | 1989-12-15 | 1989-12-15 | Semiconductor package structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1326642A JPH03187248A (en) | 1989-12-15 | 1989-12-15 | Semiconductor package structure |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03187248A true JPH03187248A (en) | 1991-08-15 |
Family
ID=18190066
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1326642A Pending JPH03187248A (en) | 1989-12-15 | 1989-12-15 | Semiconductor package structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03187248A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0648052U (en) * | 1992-12-02 | 1994-06-28 | 三菱樹脂株式会社 | IC memory card |
-
1989
- 1989-12-15 JP JP1326642A patent/JPH03187248A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0648052U (en) * | 1992-12-02 | 1994-06-28 | 三菱樹脂株式会社 | IC memory card |
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