JPH03179941A - Device which adapts itself to the practical use of it together with analog-to-digital converter in order to carry out communication from analog device to digital device - Google Patents

Abstract

PURPOSE: To save labor for engineering design and to attain the manufacturing of the device by providing the device with a digital signal processing circuit for decimating an incoming digital signal and constituting the digital signal processing circuit so as to allow a specified set of plural modules to repeat decimation for a specified number of times. CONSTITUTION: An analog/digital(A/D) circuit 14 converts an incoming analog signal received by a line 16 into a digital signal and transmits the digital signal to a decimation circuit 18. The circuit 18 applies decimation operation to the inputted digital signal and outpours a decimated digital signal. The circuit 18 consists of a decimator module 19 and an output circuit 92. An additional decimator module 19a may be added to execute decimation furthermore as necessity. The module 19 consists of a digital input circuit 66, a 1st digital cell circuit 68 and 2nd digital cell circuits 70, 72, 73. The 2nd digital cell circuits may be added to the decimator module 19 as necessity.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION The present invention is directed to a communications interface device that is adaptable for use with analog-to-digital conversion devices to provide communications between analog and digital devices. More particularly, in its preferred embodiment, the invention is used to communicate between a voice band device, such as a telephone, and a data processing device.

The invention receives digital signals from an analog-to-digital converter and decimates the incoming digital signals to produce a decimated incoming digital signal representative of the received incoming digital signal. The decimated incoming digital signal can be recognized by a data processing device.

In the manufacture of interface devices such as the present invention, alternative circuit designs are often utilized to effect different numbers of repetitions of decimation of the signal produced by the analog-to-digital conversion circuit. There is often overlap in engineering efforts to design such variously capable decimation circuits.

Such duplicative engineering effort essentially results in each newly designed digital signal processing circuit with the same amount of design effort and expense as an entirely new circuit.

The present invention is designed to overcome some of the cost of duplicating engineering efforts to design differently capable digital signal processing circuits.

SUMMARY OF THE INVENTION The present invention is an apparatus adaptable for use with an analog-to-digital converter to provide communications between analog and digital devices, the invention being an apparatus adapted for use with an analog-to-digital converter to provide communications between analog and digital devices; A digital signal processing circuit is included for decimating and providing the decimated incoming digital signal to the digital device.

The digital signal processing circuit is comprised of a plurality of modules configured such that a specified set of the plurality of modules performs a specified number of decimation iterations. The modules are further designed such that additional modules may be added to the specified set of modules to increase the decimation iterations.

It is therefore an object of the present invention to provide an apparatus that is modularly constructed and adaptable for use in communicating between analog and digital devices to facilitate sufficiently different system requirements. It is to provide.

It is a further object of the present invention to provide an apparatus whose manufacture can be accomplished with savings in engineering design effort and which is adaptable for use in providing communications between analog and digital devices.

It is a further object of the invention to provide an apparatus that is inexpensive to adapt to various system requirements and is adaptable for use in providing communications between analog and digital devices. .

Further objects and features of the invention will become apparent from the specification and appended claims when read in conjunction with the accompanying drawings, which illustrate preferred embodiments of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT The environment in which the preferred embodiment of the invention is used is illustrated in the schematic system block diagram of FIG.

In FIG. 1, an analog device 1 such as a telephone audio device
2 is connected to the analog-to-digital circuit 14. Typically, analog device 12 operates in the audio frequency range of approximately 300Hz to 3.4KHz. Analog-to-digital circuit 14 samples the incoming analog signal conveyed via line 16 from analog device 12.

The sample rate of analog-to-digital circuit 14 is approximately 2 MHz in the preferred embodiment.

Several benefits are received by high frequency sampling by analog-to-digital circuitry 14, for example, when the present invention is configured as an integrated circuit, i.e., silicon chip, higher frequencies of operation may result in higher frequencies of operation of the components of the present invention. Close spacing allows, and high frequency sampling also allows for a more accurate digital representation of the incoming analog signal.

Analog-to-digital circuit 14 converts the incoming analog signal received on line 16 to an incoming digital signal;
The incoming digital signal is communicated via line 20 to decimation circuit 18.

Decimation circuit 18 receives the incoming digital signal on line 20, performs a decimation operation on the signal, and outputs the decimated incoming digital signal on line 22. In the preferred embodiment, the incoming decimated digital signal occurs at a frequency of approximately 16 KHz, or even more so due to the high frequency close spacing of the components in the silicon chip structure and the digital representation of the incoming analog signal. Enables profit acquisition with high resolution. The incoming decimated digital signal is provided to digital device 24 via line 22. Digital device 24 is typically a device such as a data processing device or a computerized communications switching device.

An electrical schematic diagram of a preferred embodiment of the invention is shown in FIG.

For clarity in describing the preferred embodiments of this invention, like elements will be labeled with the same reference numerals throughout this description.

In FIG. 2, analog-to-digital circuit 14 receives an incoming analog signal at another input 16 from an analog device (not shown in FIG. 2). Additionally, analog-to-digital circuit 4 communicates the incoming digital signal to decimation circuit 18 via line 20a and line 20b.

The decimation circuit 18 preferably includes a digital input circuit 66, a first digital cell circuit 68, a second digital cell circuit 70, and a second digital cell circuit 72.
and an output circuit 92.

The first digital cell circuit 68 preferably receives an input from a multiplexer 74 and a 1-bit adder S
It consists of a shift register RO that provides an output to AI, a multiplexer 96, and a shift register RIB. The output of programmable logic array 78 is provided via line 100 to shift register RIB. multiplexer 9
The output of 6 is given to shift register RIA. The output of shift register RIA is fed back to multiplexer 96 as well as provided to multiplexer 104 . The output of shift register RIB is also provided to multiplexer 104. The output of multiplexer 104 is provided to multiplexer 84 in the same manner as it is provided to 1-bit adder SA1. 1st
The output of multiplexer 84, which is also the output of digital cell circuit 68, is applied to 1-bit adder SA2 of second digital cell circuit 70 in the same way as it is applied to shift register RO. Second digital cell circuit 70 further includes a multiplexer 106 that also receives the output of multiplexer 84. The output of shift register R2 is
It is fed back to multiplexer 108 as well as fed back to multiplexer 106, and is fed to 1-bit adder SA2.

The output of the 1-bit adder SA2 is also sent to the multiplexer 10.
given to 8. The output of multiplexer 108, which is also the output of second digital cell circuit 70, is applied to 1-bit adder SA3 of second digital cell circuit 72 and multiplexer 110. In the second digital cell circuit 72, the output of the 1-bit adder SA3 is further applied to the multiplexer 112, and the output of the multiplexer 110 is applied to the shift register R3. The output of shift register R3 is sent to multiplexer 112.1 bit adder SA3.
and to multiplexer 110. Multiplexer 1 which is also the output of the second digital cell circuit 72
12 outputs are given to an output circuit 92.

In particular, the output of multiplexer 112 is provided to a scaling subcircuit ↓(4) which provides the scaled output to shift register R4. The output of shift register R4 is provided to input bus 24 via line 22 via multiplexer 94.

The decimation circuit ↓8 sends the decimated incoming digital signal to the digital device (second
In the figure, only the input bus 24 of the digital device is shown).

The analog-to-digital circuit 14 includes a counter 44 and a digital-to-analog converter 4, as shown in FIG.
Contains 6.

5 Decimation circuit 18 receives the incoming digital signal from analog-to-digital circuit 14 via line 20a and line 20b and decimates the incoming digital signal in a manner described in greater detail below.

Digital input circuit 66 preferably consists of multiplexer 74, shift register 76, and programmable logic array 78. Analog-digital circuit↓
4 provides incoming digital signals on lines 20a and 20b, decimation circuit 18 is suitably clocked to decimate the incoming digital signal from analog-to-digital circuit 14.

Thus, each such subsequent digital pulse from analog-to-digital circuit 14 is provided to digital input circuit 66 at two points. The current count output of analog-to-digital circuit 14 is provided on line 20a to multiplexer 74, and shift register 76 receives and stores the history of pulse signals appearing on line 20b.

6 The structure of the digital input circuit 66 is specifically adapted to the step-up-down signal characteristics of the output of the first-order integrator, in that the step-up-down is a predetermined amount for each clock cycle. A preferred embodiment of the analog-to-digital circuit 14 is used. Such a structure saves hardware and allows the decimation-interpolator to operate at high speeds.

For purposes of illustration, the preferred embodiment of the invention shown in FIG. 2 performs the decimation by a factor of 16 implemented in a four-stage structure that implements the following transfer function:

1/256 (1+z-') 2 (1+z-2)
2(1+z-') 2(l+z-8) 2=HD
(z) (1) For example, for a sampling rate of 2.048 MHz analog-digital circuit ↓4, the decimator (
output will be 128KHz. For purposes of this illustrative example, it is assumed that analog-to-digital circuit 14 employs a 6-bit day-7 digital-to-analog converter and a first order sigma-delta modulator. Of course, the invention can also be utilized for larger digital-to-analog converters and higher order sigma-delta modulators.

The architecture of decimation circuit 18 is such that second digital cell circuit 72 connects all other parts of decimation circuit 18 (i.e., digital input circuit 66, first digital cell circuit 68, and The transfer function of equation (1) needs to be partitioned to be preceded by two digital cell circuits 70).

Ho (Z)=1/256 [H+ o (Z)*
H2.

(z) ko
(2) Here, H2D (z) is the second digital cell circuit 70 and the second digital cell circuit 72
That is, (1+z
-8) 2. The coefficient 1/256 is a scaling factor.

8 Therefore, converting equation (1) into equation (2) results in the following (3).

HD (z)=1/256 E (1+z-') 2
(1+z-2)2 (1+z-')2] (1+z
−8)(3) The terms in square brackets [] in equation (3) may be expanded to yield:

Ha (z)=1/256 [1+2z-' +3z
2+4z'-" +5z-4+6z-5+7z-6+8
z−7+7z−8+6z−9+5z−” +4z−11
+32-12 +22-13-1-z-14] (4) and H2o (z) = [1+22-8+z-''] (5) Note z -Ill indicates the value of 2 m time periods past.

With this partitioning method, HID(Z) is realized in the programmable logic array 78 and the first digital cell circuit 68, and H2C(Z) is
It will be implemented in a second digital cell circuit 70 and a second digital cell circuit 72.

The time-domain realization of equation (4) is the following equation (6).

V+ (n)=x (n)+2x (n-■)+3x
(n-2) +---+x (n-14) (6) Since the sigma-delta modulator uses the following mechanism, the difference between successive counter values, defined as dl, can be only ±1. , that is, x(n-1) can differ from x(n) by only ±1, and X(n-2) can differ from x(n-1)
may differ by only ±1, and so on.

Therefore, the time-domain realization of equation (6) is
7).

Y+ (n)=x (n)+2[x (n)-dB
] +3 [x (n) d 2 da
Ko +----+ [x (n) d, -d2-・
...-d, 4ko0 (7) Here, dl-±1 for i=1, 2, ..., ■4
It is.

Expanding equation (7) yields the following equation (8).

y+ (n)=64x (n)+63dl -61
d258d3 54d4-49d5 43ds
36dy -28da-21dg-15d+ o-10
d+ + 6d+ 2 3d+ 3 d+
4(8) Factor d+ represents the continuous output of analog-to-digital circuit 14 which also controls the incrementing or decrementing of counter 44. Output DI is continuously shifted into shift register 76 and utilized as an address to programmable logic array 78.

The address is Dl4...Dl, including a series of 1's and O's, '1' means count up (d+=+1), and '0' means count down (d+=1).

Here, all possible combinations (i.e., 213 combinations) of d14, ...d7, where d+=+11 or -1 for i=1, ..., ↓4, are expressed by the equation By substituting in (8), the contents of programmable logic array 78 could be determined. For example, for the next address, successive outputs to analog-to-digital circuit 14 are all O's, which causes counter 44 to decrement. Substituting d14,...d,=-1 into equation (8) yields the following equation (9).

y+ (n)=64x (n)+448 (9) Thus, for the preferred embodiment shown in FIG. will yield an output value of This result shows that y+(n) is x(n), the sum of the current sample (provided to shift register RO via multiplexer 74), plus the sum of all 14 previous samples.

Preferably, the output of digital input circuit 66 is divided by eight. As a result, programmable logic array 78
The loading of the counter 44 through the multiplexer 74 into the shift register RO follows every eight clocks of the shift register 76 holding the address, and six zeros are added to the product of 64 and x (n) (equation (8)). Term 1) is applied to the lowest end of the analog-to-digital circuit 14 output to produce Term 1). The remaining terms in equation (8) are calculated by programmable logic array 78.

The term in equation (8) is the first
The bit serial adder SA in the digital cell circuit 68 of
It can be added using I.

The time-domain realization of H2O(Z) is: (1% Formula % ) ) (10) In the time domain, H+o(Z) is the input utilized in calculating H2D3 (z). Thus, in effect, the time-domain output y2 (n) is the time-domain result of the total transfer function HD (Z).

The second digital cell circuit 70,72 has another ÷
resulting in a decimation of 2. The next consecutive formula for H2O(z) is the following formula (11).

y2 (n+1)=y, (n+2)+2y+ (n
+1)+y+ (n) (11) A comparison between equation (10) and equation (11) shows that successive samples (i.e., the input value to H2O(Z)) are clearly explains that it is shifted up by two digits to produce a decimation.

The first digital cell circuit 68, the second digital cell circuit 70 and the second digital cell circuit 72
The HD(Z) transfer function is realized as shown in the figure.

4 With reference to FIG. 3, the division of the matrix in the column direction is T
The lines olTl, T2, . . . are drawn to indicate successive time periods, each period being eight clock pulses in duration. The row-wise division is performed using various registers RO, RIA, RIBS in the decimation-interpolator 18.
Represents R2, R3 and R4 and their associated series adders SAI, SA2 and SA3.

Thus, each box in the matrix of FIG. 3 represents a function that is related by a particular register and a particular serial adder during a particular period of time.

As shown in FIG. 3, time periods T, -T.

Between, the quantity 64x(n) is loaded into register RO. Also, a first digital cell circuit 68, a second digital cell circuit 70, and a second digital cell circuit 72
is triggered, the output of programmable logic array 78 is loaded into register RIB, and the contents of register RO and register RIB are added to form the quantity y1 (n
) occurs.

5 Further time period T. −T1, while using the scaling function given at the appropriate timing, the amount y+
(n) is added to register R2 by bit adder SA2.
is added along with the content of the quantity y1(n)+2y+ (
n 1). Further, during the time period T, -T, the quantity y+ (n) +2y+ (n-1) is shifted into the second digital cell circuit 72 and stored in register R3 using one-bit adder SA3. The result is y+ (n)+2y+ (n
-1)+V+(n-2). The quantity y+ (n) remains in register R2. Finally, in period To 1,
Quantity y1(n)+2yl (n-1)+y+ (n-
2) is shifted into register R4 of output circuit 92 in scaled format, i.e. ÷256° second
During the eight clock pulse periods T, -T2 of the quantity 64
x(n) is again loaded into register RO, the first digital cell circuit 68 is triggered and its output is loaded into register R2, and the contents of register R2 are transferred to register R3.
loaded into.

6 Programmable logic array 78 contents are register RI
B and the quantity y+ (n+1) is added by the serial bit adder SAI to the contents of register RO and register R
Calculated by combining the contents of IB. Thus, register R2 now contains y+ (n+1) and register R3 now contains y+ (n).

During a third eight clock pulse period, T 2 T 3 , first digital cell circuit 68 , second digital cell circuit 70 , and second digital cell circuit 72 are triggered and the programmable logic array 78 is activated. The output is combined with the 64x(n) information simultaneously loaded into register RO to yield the quantity y+(n+2). The serial adder SA2 has the quantity y+ (n+2)+2y+
(n+1) and register R2 stores the quantity y+ (
n+2) is held in the storage device. The serial adder SA3 has the quantity y+ (n+2) +2y+ (n+1)+y+
Calculate (n).

The output of serial adder SA3 is then loaded into register R4 for a time period T. -T, the output previously loaded into register 7 R4 is transmitted via line 22 to input bus 24.

Thus, between the time periods To-T, Equation (10)
The first value of H2C(z) in the form is stored in register R
4, which is y+ (n)
+2y+ (n-↑)+y+(R2). During the time period T2-T3, the next consecutive equation of H2C(Z) in the form of equation (11), namely V+ (n
+2)+2y+(n+1)+y+ (n) is loaded into register R4 and the first value of H2C(Z) is clocked into input bus 24 via line 22 via multiplexer 94 of output circuit 92.

Referring to FIG. 4, a schematic block diagram illustrating the modular design of a preferred embodiment of the invention is depicted. In FIG. 4, analog device 12 sends an incoming analog signal over line 16 to analog-to-digital circuit 14. In FIG. Analog-to-digital circuit 14 passes the incoming digital signal via line 20 to decimation circuit 18.

8 Decimation 18 consists of a decimator module 19. Additional decimator modules may be added to provide further decimation as desired, and any such additional decimator modules are shown in FIG. expressed by an expression. The decimator module 19 includes a digital input circuit 66, a first digital cell circuit 68 and a second digital cell circuit 70.72.73.
Consisting of A second digital cell circuit within a given decimator module 19 may be added to provide a greater degree of decimation as desired, as shown by second digital cell circuits 72 and 73. good. The additional decimator module 19a will necessarily include a second digital cell circuit 70a and 72a, but the second digital cell circuit 70a, 72a
The number of different decimator modules 19.19a
need not be the same between the two.

The last of the second digital cell circuits 73 in the decimator module 19 provides input to the second digital cell circuit 70a of the next decimator module 19a.

The last second digital cell circuit 72a of the last decimator module 19a provides an output to the output circuit 92;
From there, the decimated incoming digital signal is passed via line 22 to digital device 24.

Although the detailed drawings and specific examples given illustrate preferred embodiments of the invention, they are for purposes of illustration only and the apparatus of the invention is limited to the precise details and conditions disclosed. Rather, it should be understood that various changes may be made without departing from the spirit of the invention as defined by the following claims.

[Brief explanation of drawings]

FIG. 1 is a schematic system block diagram of an environment in which the present invention is preferably used. FIG. 2 is an electrical zero schematic diagram of a preferred embodiment of the invention. FIG. 3 is a space-time domain matrix representation of the decimation circuit of the present invention for the implementation of the decimation transfer function. FIG. 4 is a schematic block diagram illustrating the modular design of the preferred embodiment of the invention. In the figure, 12 is an analog device, 14 is an analog-digital circuit, 18 is a decimation circuit, 24 is a digital device, 66 is a digital input circuit, 68 is the ↓-th digital cell circuit, 70, 72 and 73 are the second digital 92 is an output circuit, and 19 is a decimator module.

Claims (9)

[Claims] (1) A device that is adaptable for use with an analog-to-digital converter to provide communications from an analog device to a digital device, the analog-to-digital converter being operable to communicate with the analog device and the adaptable device. the device is adapted to convert an incoming analog signal received from said analog device into an incoming digital signal representative of said incoming analog signal; decimator means for decimating a signal and providing a decimated incoming digital signal representative of the incoming digital signal to the digital device; a meter module and an output means for providing a digital output from said decimator means, said first decimator module having a digital input circuit, a first digital cell circuit and at least one second digital cell circuit. and the at least one second digital cell circuit is arranged in series, whereby the at least one second digital cell circuit
each said at least one second digital cell circuit following the first one of said at least one second digital cell circuit has as its respective input the output of the nearest preceding one of said at least one second digital cell circuit; the digital input circuit receives the incoming digital signal from the analog-to-digital converter and produces an incoming clocked input to the first digital cell circuit; a digital cell circuit responsive to receiving the incoming clocked digital signal to produce a first repeating decimated digital signal to the at least one second digital cell circuit; said first one of said at least one second digital cell circuits generates a second repetitively decimated digital signal in response to receiving said first repetitively decimated digital signal; Each subsequent one of the second digital cell circuits receives the (n+
1), the result of the last of said at least one second digital cell circuit being the output of said first decimator module; Apparatus, wherein said last of the digital cell circuits are connected to provide respective outputs to said output means, said output means providing said decimated incoming digital signal to said digital device. (2) the decimator means further comprises at least one second decimator module, each of the at least one second decimator module comprising at least one secondary digital cell circuit; At least one second decimator module is arranged in series, whereby a first of said at least one second decimator module receives as its input said output of said first decimator module. each of said at least one second decimator module receiving and following said first of said at least one second decimator module receives said at least one second decimator module as a respective input. An analog device according to claim 1, wherein the output of the nearest predecessor of a second decimator module is received and the result of the last one of the at least one second decimator module is connected to the output means. Apparatus adapted for use with an analog-to-digital conversion device to provide communication between the device and a digital device. (3) The digital input circuit provides communication between an analog device and a digital device according to claim 1, wherein the digital input circuit includes shift register/programmable logic means for producing the incoming clocked input. Apparatus adapted for use with analog-to-digital conversion equipment for purposes. (4) The digital input circuit provides communication between an analog device and a digital device according to claim 2, wherein the digital input circuit includes shift register/programmable logic means for producing the incoming clocked input. Apparatus adapted for use with analog-to-digital conversion equipment for purposes. (5) The combination of an analog device and a digital device according to claim 2, wherein the at least one secondary digital cell circuit is substantially the same as the at least one second digital cell circuit. apparatus adapted for use with analog-to-digital conversion equipment for communicating between (6) The combination of an analog device and a digital device according to claim 4, wherein the at least one secondary digital cell circuit is substantially the same as the at least one second digital cell circuit. apparatus adapted for use with analog-to-digital conversion equipment for communicating between (7) Claim 1, wherein the at least one second digital cell circuit is two second digital cell circuits.
Apparatus adapted for use with an analog-to-digital converter for communicating between analog and digital devices as described in . (8) An apparatus adapted for use with an analog-to-digital converter to provide communications between analog and digital devices, the apparatus comprising: decimating the incoming digital signal; and digital signal processing means for providing a decimated incoming digital signal to the digital device, the digital signal processing means including a plurality of modules, the plurality of modules being configured to define a specified set of the plurality of modules. an apparatus configured to perform a specified number of decimation iterations. 9. The analog device of claim 8, wherein additional modules of the plurality of modules may be added to the identified set to substantially increase the iterations of the decimation. Apparatus adapted for use with an analog-to-digital converter for communicating with a digital device.