JPH03169063A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To control the capacitance and to enable adjustment to realize target characteristics of a semiconductor integrated circuit device by varying the voltage at which a diffusion resistance is isolated. CONSTITUTION:A P-type semiconductor layer 31 is made a diffusion resistance and has a resistance between those of an electrode 26 and an electrode 27. A voltage not lower than that applied to the electrodes 26, 27 is applied to an electrode 28. A reverse bias is made to be applied to a p-n junction between a P-type semiconductor layer 31 and an N-type semiconductor layer 32. Thereby, a diffusion resistance of the semiconductor layer 31 is isolated from others. Furthermore, at this time, a depletion layer 33 enlarges simultaneously and the diffusion resistance of the P-type semiconductor layer 31 has a capacitance with respect to the earth. The thickness (d) of the depletion layer 33 depends on a voltage applied to the electrode 28; if the voltage is high (low), the thickness (d) of the depletion layer 33 increases (decrease). Therefore, a capacitance is variable in accordance with a voltage applied to the electrode 28 and the diffusion resistor 31 has a resistance value and a variable capacitance value simultaneously. Thereby, adjustment is possible to realize target characteristics of an integrated circuit device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a diffused resistance.

[Prior Art] Conventionally, in this type of semiconductor integrated device, when it is desired to have a capacitance in parallel with a resistor, Metal Insulat is used.
or Semiconductor structure (hereinafter referred to as M
A capacitor such as IS structure was connected.

[Problems to be Solved by the Invention] Since the conventional semiconductor integrated circuit device described above uses a capacitor such as an MIS structure, it takes up a large area in order to form a capacitor with a desired capacitance value. However, there is a drawback that the degree of integration of the semiconductor integrated circuit device cannot be increased.

Furthermore, there is a drawback that the capacitance value of a capacitor such as an MIS structure is affected by process variations.

[Differences between the invention and the prior art] The present invention differs from the conventional semiconductor integrated circuit device described above in that the diffused resistor itself has a capacitance by forming a depletion layer, and a capacitor such as a MIS structure is not specially connected. The difference is that the capacitance value can be adjusted externally by adjusting the thickness of the depletion layer.

[Means for Solving the Problems] A semiconductor integrated circuit device of the present invention includes a depletion layer that insulates and separates the diffused resistor from the surroundings in a semiconductor integrated circuit device having a diffused resistor and a capacitor connected in parallel with each other. and the capacitance value that the depletion layer has with respect to ground is used as the capacitor.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an equivalent circuit of a semiconductor integrated circuit device according to a first embodiment of the present invention, and 1, 3, 7, 8,
9, 13, 14, 1B are diffused resistors, 4, l8 are capacitors, 2, 5, 6, 10, 11, 1
2, 15, and 17 are transistors. FIG. 2 is a plan view showing a portion 19 or 20 in which the diffused resistor and capacitor shown in FIG. 1 are connected in parallel. Figure 3 is the second
It is a sectional view of Figure ■1■.

As shown in FIG. 1, in the portion 19, a resistor 3 and a capacitor 4 are connected in parallel, and a point B is connected to ground. Similarly, in the portion 20, a resistor 16 and a capacitor 18 are connected in parallel, and point D is connected to ground. In this embodiment, as shown in FIG. 3, the P-type semiconductor layer 31 is used as a diffused resistor, and has a resistance value between the electrode 26 and the electrode 27. A voltage higher than the voltage applied to the electrodes 26 and 27 is applied to the electrode 28 to remove the P of the P-type semiconductor layer 31 and the N-type semiconductor layer 32.
By applying a reverse bias to the N junction, the diffused resistance of the P type semiconductor layer 31 is insulated from others. Furthermore, at the same time, the depletion N33 expands and the diffused resistance of the P-type semiconductor layer 31 has a capacitance with respect to the ground.

The capacitance C at this time is shown in the following equation (1).

ε8◆ εS◆ S C= ・・・・・・・・・・・・
・・・・・・・・・(1)d However, ε is the dielectric constant in vacuum, and εS is the N-type semiconductor layer 3
2, d is the thickness of the depletion N33, and S is the second
It is the product of W and L in the figure. Calculated under general conditions,
From equation (1), the capacitance value per 1 μm 2 is approximately 0.3 fF. The thickness d of the depletion layer 33 is determined by the voltage applied to the electrode 28; if the voltage is high, the thickness d of the depletion layer 33 becomes large, and if the voltage is low, the thickness d of the depletion layer 33 becomes small. Therefore, from equation (1), the capacitance can be varied by changing the voltage applied to the electrode 28, and can be varied by about 0.1 fF per 1 μm2. Therefore, the diffused resistor shown in FIG. 2 has a resistance value and a variable capacitance value at the same time.

Note that 29. in FIGS. 2 and 3. 30. 36
is an insulating film, 34 is an N-type semiconductor layer, and 35 is a P-type semiconductor layer.

FIG. 4 is a plan view of a diffused resistor according to a second embodiment of the present invention, showing portions corresponding to portions 19 and 20 in FIG. As in the previous embodiment, in the portion shown in FIG. 4, a resistor and a capacitor are connected in parallel, and one end is connected to ground.

This embodiment is characterized by a pair of diffused resistors 3 with a length of 2L and a width of W.
9.40 are connected in parallel at both ends with electrodes 48.47, and the rest is the same as in the previous embodiment. The diffused resistance value is determined by the ratio of the length of the diffused resistor to the width W; when L is large, the diffused resistance value becomes large, and when W is large, the diffused resistance value becomes small. The capacitance value of the diffused resistor is given by equation (1), and is determined by the area S of the resistor, that is, the product of W and L.

Therefore, in this embodiment, since the diffused resistors are connected in parallel, there is an advantage that only the capacitance value can be increased by about 4 times without changing the diffused resistance value.

[Effects of the Invention] As explained above, the present invention enables a semiconductor integrated circuit device having a diffused resistance to have a capacitance without externally connecting a capacitor such as an MIS structure, and improves the integration of the semiconductor integrated circuit device. by increasing the degree of accuracy and reducing the chip area.
This has the effect of increasing production numbers.

In addition, the capacitance of a capacitor such as an MIS structure varies depending on the process, but the present invention can control the capacitance value by changing the voltage for insulating and separating the diffused resistor, so that the semiconductor integrated circuit device has the target characteristics. There is an effect that can be adjusted.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a plan view showing the main parts in FIG. 1, and FIG. The sectional view and FIG. 4 are plan views of essential parts of a semiconductor integrated circuit device according to a second embodiment of the present invention. 1, 3, 7, 8, 9, 13,
14, 16, 31, 39.40... Diffusion resistance, 4
, 1 8 ・Capacitor, 2, 5, 6, 10, 1 1, 12,
15.17...Transistor, 26, 2
7. 28, 46.47... a electrode, 32, 34, N-type semiconductor layer, 29, 30.36... insulating film, 31, 35...
......P-type semiconductor layer, 33...
...depletion layer.

Claims (1)

[Claims] In a semiconductor integrated circuit device having a diffused resistor and a capacitor connected in parallel to each other, a depletion layer is formed to insulate and separate the diffused resistor from the surroundings, and a capacitance value that the depletion layer has with respect to ground is used as the capacitor. A semiconductor integrated circuit device characterized by: