JPH03167838A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To improve dielectric breakdown strength of an insulating film covering a groove by selectively implanting reverse conductivity type impurity ions to a first impurity region on a substrate, by compensating a concentration distribution of the implanted ions and by forming a groove without a corner part in an upper edge part through selective anisotropic etching. CONSTITUTION:An n<+>-type first impurity region 14 and an SiO2 film 13 are laminated on an n-type Si semiconductor substrate 12; impurities such as boron ions of reverse conductivity type are selectively implanted to a region 14 through a resist film 16; and a concentration distribution of boron ions is compensated by required heat treatment; thereby, a second impurity region 14a is formed and a remaining region 14 is formed to a required shape. Then, if a groove is formed by etching the region 14 using a PSG film, etc., as a resist, an upper edge path 20a is formed to a shape which enlarges gradually without a corner. Therefore, a corner part is not formed also in an SiO2 film 21 of an insulating film which is applied to a groove part; development of field concentration is prevented; and dielectric breakdown strength of an insulating film covering a groove is improve. Thereby, a semiconductor device of high properties can be manufactured.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Prior Art (Fig. 4, Fig. 5, Fig. 6) Problems to be Solved by the Invention Examples of Means and Effects for Solving the Problems (Fig. 1, Fig. 2, Fig. 3) Effects of the invention [Summary] Regarding a semiconductor device and its manufacturing method, more specifically, a semiconductor device having a groove for element isolation etc. in a semiconductor substrate and its manufacturing method. The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same that can improve the dielectric breakdown strength of the insulation layer covering the trench and improve the characteristics of the semiconductor device. A first impurity having a first conductivity type impurity concentration uniformly formed by introducing an impurity! ! A region, and a trench formed by selectively removing the first impurity region so that the first impurity region is exposed at the bottom, and the upper edge of the trench is removed in a curved manner; An oxide film deposited and shaped on the inner wall of the trench, and an oxide film formed inside the semiconductor substrate and in a region sandwiching the trench so as to be in contact with the oxide film, and having a higher concentration of impurity of one conductivity type than the first one conductivity type. The second impurity region has a lower impurity concentration of one conductivity type, and the polysilicon film is formed to fill the trench.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having grooves for element isolation etc. in a semiconductor substrate and a method for manufacturing the same.

[Conventional technology]

FIGS. 4(a) and 4(b) are cross-sectional views illustrating a method of forming trenches for element isolation in a conventional St substrate.

First, as shown in FIG. 2(a), a resist film 2 is uniformly formed on a Si substrate 1, and then selectively patterned and opened through a normal photolithography process to form a mask. evt and use the above mask to perform R I E (Reacttve Ion Etchi
ng) method to anisotropically etch the Si substrate 1 to selectively form grooves 3. Subsequently, an insulating oxide film 4 is formed inside the trench 3 by thermal oxidation.

After that, grooves for element isolation are created through the usual process (Figure 6).
).

FIG. 6 is a top view of the semiconductor device fabricated in this manner, and FIG. 5(a) is a cross-sectional view taken along the line A--A shown by the dashed line in FIG. FIG. 5(b) is a cross-sectional view taken along the line BB shown by the dashed line in FIG.

Figure 5(a). In (b) and FIG. 6, 5 is a polysilicon material embedded in the trench 3, 6 is a gate oxide film, 7 is a gate electrode, and 8a and 8b are Si-based films between the gate electrode 7 and the trench 3. Formed source train (S/D)
8N area, 9 is an insulating film covering the polysilicon material 5, IO
is an insulating film covering the gate electrode 7, lla and Ilb are S
/ D eJl area 8a. 8b, and 30 is a channel region between S/D regions 8a and 8b where a channel is formed when a voltage is applied to the gate electrode 7. By the way, as shown in Fig. 4(a), when RIE is performed,
The shape of the corner of the upper edge 3a of the groove 3 is approximately a right angle. Furthermore, as shown in FIG. 3(b), when the inside and outside of the groove 3 is thermally oxidized, due to the nature of thermal oxidation, the oxidation does not proceed at the corner of the upper edge 3a of the groove 3 compared to other parts. sio211!4
becomes thinner. Therefore, the Si at the corner of the upper edge 3a of the groove 3
The shape of base 1 becomes beak-like. Therefore, as shown in FIG. 6, the manufactured semiconductor device has this beak-shaped portion along the boundary between the channel region 30 and the trench 3 for element isolation (the upper part 3a in FIG. 6). ,
When a gate voltage is applied to the gate electrode 7 in FIG. 5(b) during normal operation, the electric field is concentrated on this upper edge 3a between the gate electrode 7 and the channel nodule region 30. Therefore, the dark value voltage is different between the channel region 30 near the upper part 3a and the inner channel region 30, and as a result, a bend occurs in the drain current (■4)-gate voltage (V,) characteristics of the semiconductor device. There is a problem. Furthermore, in addition to the electric field concentration due to deterioration in the shape of the Si substrate l at the corner of the upper edge 3a of the groove 3, which becomes beak-like, the SiOz film 4 at the corner is reduced as shown in FIG. 4(b). Because it is thin, in the worst case scenario, dielectric breakdown may occur in this area, causing the semiconductor device to malfunction. Such a problem occurs even when the groove 3 is formed by an isotropic etching method using a chemical reaction.

The present invention has been made in view of these conventional problems, and provides a semiconductor device and its manufacture that can improve the dielectric breakdown strength of the insulating film covering the trench and improve the characteristics of the semiconductor device. The purpose is to provide a method. [Means for Solving the Problems] The above problems firstly solve the above problems, as shown in FIGS. selectively introducing opposite conductivity type impurities into the substrate 12 by ion implantation, and leaving a first impurity region 14 in which the opposite conductivity type impurities are not introduced between the regions into which the opposite conductivity type impurities are introduced; By redistributing the opposite conductivity type impurity and compensating the concentration, a second impurity region 14a of one conductivity type with a second concentration lower than the first concentration is formed, and the second impurity region 14a is a step of leaving a first impurity region 14 with a first concentration whose upper end portion gradually expands from the inside of the semiconductor substrate 12 toward the surface; and anisotropic anisotropy of the remaining first impurity region 14. forming a region 20 in which the first impurity region 14 remains at the corner of the upper edge 20a of m20 by selectively etching using an etching method, and etching at different etching rates in accordance with the difference in impurity concentration; The groove 20 is etched by an isotropic etching method using an etching material.
The first impurity region 14 remaining at the corner of the upper edge 20a of
The present invention is solved by a method for manufacturing a semiconductor device, which is characterized by a step of forming the upper edge 20a of the groove 20 into a shape that gradually widens from the inside of the groove 20 to the surface. 2, as shown in FIGS. 2(a) and 2(b), a first conductivity type impurity is uniformly formed by introducing one conductivity type impurity into the surface of the semiconductor substrate 12. The first impurity region 14 is formed by selectively removing the first impurity region 14 so that the first impurity region 14 is exposed at the bottom, and the upper edge 20a of the groove 20 is curved. The groove 20 that has been removed, the oxide film 21 that is adhered and formed on the inner wall of the groove 20, and the inside of the semiconductor substrate 12 and the region sandwiching the groove 20, so as to be in contact with the oxide film 21. a second impurity region 14a that is formed and has an impurity concentration of one conductivity type lower than the first impurity concentration of one conductivity type;
The problem is solved by a semiconductor device characterized by having a polysilicon film 22 formed so as to fill the trench 20.

[Effect]

According to the method of manufacturing a semiconductor device of the present invention, FIG.
As shown in FIG.
Since the groove 20 has a shape that gradually widens from the inside to the surface, the corners do not have an acute angle shape as in the conventional case.
The corners are removed, creating a shape with a gentle slope. Therefore, in the case of a structure in which an electric field is applied to the groove 20, unlike the conventional case, the electric field does not concentrate at the upper edge 20a of the groove 20, so that the insulation of the insulating film formed covering the groove 20 is reduced. It is possible to improve the breaking strength.

In addition, since the thickness of the insulating film formed by thermal oxidation becomes uniform at the upper edge 20a of the groove 20, in addition to the effect of alleviating electric field concentration by improving the shape of the upper edge 20a of the groove 20, dielectric breakdown Further improvement in strength can be achieved.

According to the semiconductor device of the present invention, as shown in FIGS. 2(a) and 2(b), the shape of the upper edge 20a of the groove 20 gradually widens from the inside to the surface.

Therefore, the corners of the upper edge 20a of the groove 20 are removed and the groove 20 has a shape with a gentle slope.
It is possible to prevent the electric field from concentrating on the upper edge 20a. For this reason, even if a part of the channel is formed at the upper edge 20a of the groove 20, the channel in this part can be prevented from concentrating on the inner channel. It has the same dark value voltage as , and is formed as follows.
Transfer characteristics and the like of the semiconductor device are improved.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(f) are cross-sectional views illustrating a method of manufacturing a semiconductor device having trenches for element isolation according to an embodiment of the present invention. First, as shown in Figure (a), in order to protect the surface by ion implantation, approximately 300 SiOz films 13 were formed on an n-type Si substrate (semiconductor substrate) 12 by thermal oxidation.
In order to make the surface layer of the n-type Si substrate 12 n-type, phosphorus ions as an n-type impurity were implanted at an acceleration voltage of 1.4 MeV and an implantation amount of I.
The phosphorus ions are implanted under the conditions of " As shown, a resist B.15 with a film thickness of about 3 μm and a width of about 2 μm was formed by patterning as a mask for selectively implanting boron, and then using this as a mask, an acceleration voltage of 700 keV and an implantation amount of 1× were applied. Tephorone ions are implanted under the conditions of 101SC1''.
As a result, boron is absorbed into the Si substrate 1 on both sides of the resist film 15.
A first impurity region 14 into which boron ions are not introduced remains directly under the resist film 15.

At this time, the concentration of the implanted boron has a distribution such that the impurity concentration reaches its maximum value inside the Si substrate 12, as shown in the concentration distribution diagram on the right side of FIG. However, it is layered.

Next, after removing the resist film l5, the temperature was set to 100°C.
Heat treatment is performed for about 30 minutes under the following conditions. As a result, since boron diffuses isotropically, the boron at the corner (E) of the densely concentrated layer spreads radially around the corner (E). What is the boron diffusion region that is formed? Part (E) becomes fan-shaped with center. Further, in the region in which boron is diffused and activated by the above heat treatment, the n-type first impurity region 14 is compensated for by boron, which is a p-type impurity, so that the n-type first impurity region 14 is to n-type second impurity region 1
Changed to 4a. Therefore, the n0 type first impurity region 14 remaining directly under the area where the resist film 15 was present
In the vicinity of the surface of the Si substrate 12, the cross-sectional shape gradually widens continuously from the inside toward the surface. Note that the cross-sectional shape is also similar to that of the Si substrate 12 near the boundary between the internal n-type Si base temporary 12 and the n3-type first impurity region 14.
The shape is similar to the shape near the surface ((C) in the same figure).

Next, a SiO2 film 17. Film thickness approx. 1
000 pieces of Si3N. After sequentially growing M 1 8 and a PSG film 19 with a thickness of about 5000 as an etching mask, the first impurity wI region 14 on the surface of the Si-based Fi 12 is grown.
The width of these three layers of films 17, 18, and 19 is about 1μ inside the
An opening 19a of m is formed. After that, S.F. The Si substrate 12 is etched by an anisotropic etching method using a gas such as, for example, a groove 20 having a depth of approximately 3 μm. At this time, the first impurity region 14 remains at the corner of the upper edge 20a of the formed groove 20 (FIG. 2(d)). Next, SF. which is one of the isotropic etching methods. or CF
．． The remaining first impurity region 14 at the corner of the upper green portion 20a of the groove 20 is etched by a downflow etching method using a gas such as . At this time, SF. or CF. In the isotropic etching method using gases such as s+. It is known that the etching rate of one substrate is several times higher than the etching rate of a Si substrate with a low n0 type impurity concentration, and therefore only the n0 type first impurity region 14 is removed. As a result, groove 2
The shape of the upper edge 20a of the groove 20 is such that the corners are removed and it gradually widens from the inside of the groove 20 toward the surface of the groove 20 (FIG. 2(e)). Subsequently, after forming a Sing film 21 with a thickness of about 1,000 layers for insulation on the Si substrate 12 inside the trench 20 by thermal oxidation, polysilicon I! Embed 22 in the groove? The same figure (f
)).

Thereafter, a semiconductor device having an element isolation trench surrounding the element formation region is completed through normal steps (Fig. 2(a), (b), and Fig. 3). As described above, according to the method of manufacturing a semiconductor device of the present invention, as shown in FIG. 1(e), the corner of the upper edge 20a of the groove 20 is removed and Since the shape gradually widens, the corners are not as sharp as in the conventional case, but the corners are removed and the shape is improved to a gentle slope. Therefore, it is possible to prevent the electric field from concentrating on the upper edge 20a of the groove 20, thereby improving the dielectric breakdown strength of the SiO film 21 formed covering the upper edge 20a of the groove 20. It is possible to In addition, since the thickness of the SiO2 film 21 formed by thermal oxidation is uniform at the upper edge 20a of the groove 20, in addition to the effect of alleviating electric field concentration by improving the shape of the upper edge 20a of the groove 20, It is possible to further improve dielectric breakdown strength. Also, are Figures 2 (a), (b) and 3 above? FIG. 3 is a top view of the semiconductor device, and FIG. 2(a) is a dashed-dotted line in FIG. 3. 2(b) is a sectional view taken along the line CC shown in FIG. 3, and FIG. 2(b) is a sectional view taken along the line DD shown in FIG. 2(a), (b) and FIG. 3, reference numeral 20 denotes a groove formed on the n-type Si substrate (semiconductor substrate) 12 by the above manufacturing method, and the bottom of the groove 20 has an
A first impurity nodule region 14 of .degree. type is formed, and a second impurity region 14a of n-type, which has a lower concentration than the first impurity region 14, is formed across the groove 20. Further, the shape of the upper edge 20a of the groove 20 is such that it gradually widens from the inside of the groove 20 toward the surface. Then, an SiO film (oxide film) 21 for insulation and a polysilicon film 22 for embedding are formed within the space 20, and the polysilicon film 22 is further grounded for surface stabilization. ．． 26 is an insulating film made of SiO1 film formed by oxidizing the polysilicon film 22, and 27 is an S covering the gate electrode 24.
An insulating film such as an iOz film, 23 a gate oxide film, 2
5a and 25b are source/drain (S/D) fin regions formed on the Si substrate 12 with the gate electrode 24 in between;
a, 26b are S/D extraction electrodes connected to the S/D 8N regions 25a, 25b, 29 are S/D regions 25a and 25
This is the channel region under the gate oxide film 23 where a channel is formed between the As described above, according to the semiconductor device of the embodiment of the present invention,
As shown in FIGS. 2(a) and 2(b), the upper edge 20 of the groove 20
The shape of a is such that the corners are removed and the shape gradually widens from the inside toward the surface. Therefore, it is possible to prevent electric field concentration from occurring at the upper edge 20a of this groove 20. For this reason,
As shown in FIG. 2(b), even if the upper edge 20a of the groove 20 is adjacent to the channel region 29, it is possible to prevent a channel from being locally formed there. This makes it possible to improve the drain current (■,)-gate voltage (V,) characteristics of the semiconductor device, that is, the transfer characteristics. In addition, although Si-based fabric 12 was used as the semiconductor substrate in the embodiment of the present invention, S○I
(Semiconductor OnInsulato
A semiconductor film on an insulating film having a structure r) can also be used.

Furthermore, although an n-type St-based material 12 is used as the semiconductor substrate, a p-type Si substrate or a semiconductor substrate made of other elements may also be used.

Furthermore, a down flow etching method, which is a dry etching method, is used as an isotropic etching method, but H F
/HNO3-based solution can also be used. [Effects of the Invention] As described above, according to the semiconductor device and the method for manufacturing the same of the present invention, since the corners of the upper edge of the groove are removed and tapered, voltage is not applied to this portion. In this case, electric field concentration can be prevented. Therefore, if this is used, for example, as a trench for isolation of an insulated gate field effect transistor,
Even if the channel region is adjacent to the upper edge of the groove, local formation of a channel there can be prevented. This makes it possible to improve the transfer characteristics of insulated gate field effect transistors. Furthermore, since the corners of the upper edge of the groove are removed, an insulating film having a uniform thickness can be formed covering the upper edge of the groove. Therefore, in addition to the effect of alleviating electric field concentration due to the improved shape of the groove by tapering the upper edge of the groove, the insulation between the semiconductor substrate and one of the spiritual electrodes, such as the gate electrode, which face each other with the insulating film in between, is Destruction resistance can be improved.

[Brief explanation of the drawing]

FIG. 1 shows a semiconductor '! of an embodiment of the first invention. FIG. 2 is a cross-sectional view of a semiconductor device having a groove according to an embodiment of the second invention; FIG. FIG. 4 is a cross-sectional view illustrating a method of manufacturing a conventional semiconductor device, FIG. 5 is a cross-sectional view of a conventional semiconductor device, and FIG. 6 is a conventional example. FIG. 2 is a top view of the semiconductor device of FIG. ? Explanation of symbols] 1...Si substrate, 2.15...resist film, 2a, 19a...opening, 3.20...groove, 3a, 20a...upper edge, 4,13 .17...SiO■ film, 5.22...Polysilicon film, 6,23...Gate oxide film, 7.24...Gate electrode, 8a, 8b, 25a, 25b...S /D? J area, 9
,10,26.27...! ! ! lamina, 11a, llb
．． 28a, 28b = S/D extraction electrode, 12...Si
Substrate (semiconductor substrate), 14... First impurity region, 14a... Second impurity region, 18... SiJ4 film, l9... PSG film, 2 1-Sinz film (oxide film), 29 30...Channel area. Cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the first invention (Part 1) Cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the first invention (Part 2) Cross-sectional view of a semiconductor device having a groove according to an embodiment of the second invention FIG. 2C-J Top view of a semiconductor device having a groove according to an embodiment of the second invention FIG. 3A Opening of a conventional semiconductor device FIG. 4 is a cross-sectional view of a conventional semiconductor device. FIG. 5 is a top view of a conventional semiconductor device.

Claims (2)

[Claims] (1) A first impurity region of one conductivity type with a first concentration (14
) is selectively introduced with an opposite conductivity type impurity into a semiconductor substrate (12) having an opposite conductivity type impurity by ion implantation, and a first impurity region ( 14) and redistributing the opposite conductivity type impurity to compensate for its concentration, forming a second impurity region (14a) of one conductivity type with a second concentration lower than the first concentration. The upper end portion is formed between the second impurity region (14a) and the semiconductor substrate (12).
) by leaving a first impurity region (14) with a first concentration that gradually spreads from the inside toward the surface; and selectively etching the semiconductor substrate (12) by an anisotropic etching method. The upper edge of the groove (20) (
20a) forming the groove (20) in which the first impurity region (14) remains at the corner of the groove; and an isotropic etching method using etching materials with different etching rates corresponding to the difference in impurity concentration. The groove (2)
0) to form the upper edge (20a) of the groove (20).
removing the first impurity region (14) remaining at the corner of the
A method for manufacturing a semiconductor device, comprising the step of shaping the upper edge (20a) of the groove (20) into a shape that gradually widens from the inside of the groove (20) toward the surface. (2) A first impurity region (14) having a first conductivity type impurity concentration uniformly formed by introducing one conductivity type impurity into the surface of the semiconductor substrate (12); The first impurity region (14) is selectively removed so that the impurity region (14) is exposed at the bottom, and the upper edge (20a) of the groove (20) is removed in a curved manner. The groove (20)
and an oxide film (21) deposited and formed on the inner wall of the groove (20).
and formed inside the semiconductor substrate (12) and in a region sandwiching the groove (20) so as to be in contact with the oxide film (21),
a second impurity region (14a) having an impurity concentration of one conductivity type lower than the first impurity concentration of one conductivity type, and a polysilicon film (22) formed so as to fill the groove (20). A semiconductor device characterized by: