JPH03164935A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To ensure the return to an arithmetic register without designating the address of the arithmetic register by providing a saving register which stores the register address as well as the value of the arithmetic register that is updated for each executing instruction. CONSTITUTION:When the contents of an arithmetic instruction part OP of an instruction code 11 show an instruction that writes data to an arithmetic register 13 with execution of an operation, a register address part 11a of the code 11 is inputted to an address decoder 12. At the same time, an address W of a register which is updated with execution of an instruction is stored in a saving register 15. Then the data on a selected arithmetic register 13 is inputted to a computing element 14 and at the same time the data on the register which is updated with execution of an instruction is stored in the register 15. Then the element 14 ends its operation and stores data in the register 13. Thus it is possible to save the unupdated data on a register to be updated without executing a special instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an arithmetic processing device that performs pipeline processing of arithmetic execution.

Conventional technology FIG. 3 shows a schematic configuration of a conventional arithmetic processing device.

1 is an instruction code, which stores an arithmetic instruction section OP, and a register address section la consisting of two register addresses W, which are updated by executing an instruction, and a register address S, which is not updated by executing an instruction. Reference numeral 2 denotes an address decoder which inputs the register address portion 1a of instruction code 1, decodes the register address, and selects a register. 3 is an arithmetic register which stores data necessary for arithmetic operations.

Reference numeral 4 denotes an arithmetic unit which performs arithmetic operations on two data from the arithmetic register 3 by manual pipeline processing and outputs one piece of data to the arithmetic register 3.

Next, the operation of the above conventional example will be explained. First, the register address part 1a of the instruction code is transferred to the address decoder 2.
By inputting , the address decoder 2 selects two registers in the arithmetic register 3. Next, the arithmetic unit 4 takes as input the data stored in the two selected registers, executes the arithmetic operation by the arithmetic instruction part OP of instruction code 1 by pipeline processing consisting of two stages, and after execution, one The output data is sent to the register of the arithmetic register 3 selected by the address decoder 2.
Store at address W.

Problems to be Solved by the Invention However, the conventional device described above has a problem in that data before update cannot be saved in a register whose data has been updated when an instruction is executed. Therefore, when the data before update is required, it is necessary to execute an instruction to copy the data of the register to be updated to another register in advance, resulting in a problem that the number of instructions increases.

In addition, instructions that are executed immediately after a conditional branch instruction regardless of whether the branch is executed are limited to non-executable instructions or usable arithmetic registers in order to save the contents of the register in consideration of the branch destination instruction after the branch instruction is executed. The problem was that it had to be taken as a given order.

The present invention solves these conventional problems, and makes it possible to save data in registers that are updated by executing an instruction, regardless of the execution of an instruction, and to restore data without considering the address of an arithmetic register. The first objective is to provide an arithmetic processing device.

A second object of the present invention is to provide arithmetic processing that does not limit the number of usable arithmetic registers for instructions that are executed regardless of the branch immediately after a conditional branch instruction, which always exists when instruction execution is pipelined. The goal is to provide equipment.

Means for Solving the Problems In order to achieve the above object, the present invention provides, in addition to the arithmetic register, one or more save registers that store the value and register address of the arithmetic register that are updated for each executed instruction. , a data selector that selects either the output of the calculation register or the value of the save register after execution of the instruction and outputs it to the calculation register, and the register address part of the instruction code and the register address part stored in the save register. and an address selector that selects one of the addresses and outputs it to the address decoder.

Further, in another embodiment according to the present invention, in addition to the above configuration, when executing a register restore instruction for writing data stored in a save register to an arithmetic register, it is determined whether or not a conditional branch instruction has been executed. The address selector and data selector are provided with conditional branch judgment means for selecting input from the save register.

Effects The present invention has the following effects due to the above configuration. That is, when saving data in an operation register, first the register address part of the instruction code is manually entered into the address decoder. At the same time, the register address of the register updated by the instruction execution is stored in the save register (.Next, the address decoder decodes the manually entered address, selects the operation register, and then The data in the registers that have been updated are input to the arithmetic unit, and the data in the registers updated by the execution of the instruction is stored in the save register.After that, the arithmetic unit finishes the operation and stores the data in the arithmetic register. , At this time, the data before updating of the updated register is stored in the save register together with the register address, and the data can be saved without executing a special instruction.

Also, when restoring data stored in the save register to the calculation register, the address selector selects the register address stored in the save register and inputs it to the address decoder. After selecting the arithmetic register, the data selector selects the data in the save register and stores it in the arithmetic register, so that the data is stored in the save register without specifying the register address of the arithmetic register to be restored. Data can be returned to the operation register.

Further, in another embodiment of the present invention, while always saving the registers as described above, when executing a conditional branch instruction, the conditional branch judgment means stores whether or not to execute the branch, and immediately after the conditional branch instruction When a branch is made after an instruction to be executed regardless of branching is executed, the above-mentioned save register is saved only when the conditional branch determination means remembers that the conditional branch has been executed as the branch destination instruction. Execute the save register restore instruction that performs the restore. As a result, it is possible to eliminate the limitation on usable arithmetic registers for instructions to be executed regardless of the branch immediately after a conditional branch instruction, which always exists in an arithmetic unit that performs pipeline processing of instruction execution.

Embodiment (Embodiment 1) FIG. 1 shows a schematic configuration of an arithmetic processing device in a first embodiment of the present invention. In FIG. 1, 11 is an instruction code, and a register address section 11a is stored, which consists of an arithmetic instruction section oP, a register address W that is updated by executing an instruction, and a register address S that is not updated by executing an instruction. has been done. 12 is an address decoder, and register address section 1 of instruction code 11
1a is used manually to decode register addresses and select registers. Reference numeral 13 is an arithmetic register that stores data necessary for the arithmetic operation. 14 is an arithmetic unit which inputs two data from the arithmetic register 13, performs arithmetic operations through pipeline processing consisting of two stages, and outputs two pieces of data. A save register 15 stores data having the same bit width as the data stored in the arithmetic register 13 and a register address W.

16 is a data selector which selects one from the output data of the arithmetic unit 14 and the data stored in the save register 15, and selects the register address W of the arithmetic register 13.
Write to. An address selector 17 selects one of the register address W of the instruction code 11 and the register address W stored in the save register 15, and outputs the address to the address decoder 2.

Next, the operation of the first embodiment will be explained. When the contents of the arithmetic instruction part OP of the instruction code 11 are instructions for writing data to the arithmetic register 13 by executing an operation, the register address part 11 of the instruction code 11
a is input to the address decoder 12. At the same time, the register address W of the register updated by the instruction execution is stored in the save register 15. Next, the address decoder 12 decodes the input address and selects the arithmetic register 13, and then inputs the data of the selected register to the arithmetic unit 14, and the data of the register that is updated by executing the instruction. is stored in the save register 15 (.Then, the arithmetic unit 14 finishes the operation and stores the data in the arithmetic register 13, so that the pre-update data of the updated register is saved in the save register 15 along with the register address W. , and the saving has been completed.Furthermore, when the contents of the operation instruction part OP of the instruction code 11 are instructions that do not cause data to be written to the operation register 13 by execution of the operation, the above-mentioned saving is not performed. do not have.

Next, when the content of the operation instruction part OP of the instruction code 11 is an instruction to restore the data saved in the save register 15, the address selector 17 selects the register address W stored in the save register 15. Address
selecting a register in the arithmetic register 13 by outputting it to the decoder 12, and the data selector 16 selecting data in the save register 15 and outputting it to the arithmetic register 13, and writing the data in the arithmetic register 13]; 0, the data restoration ends.

In this manner, according to the first embodiment, by providing the save register 15, data selector 16, and address selector 17 in addition to the arithmetic register, an instruction that writes to the arithmetic register 13 by executing an arithmetic operation can be written to the arithmetic register 13. In this case, the data before update is always saved, and when the instruction is to restore the data before update of the arithmetic register 13 that was last updated, the data is returned to the arithmetic register 13 without specifying the register address of the arithmetic register 13. can be done.

In this embodiment, only one piece of data can be stored in the save register 15, but a configuration may be adopted in which multiple pieces of data can be stored in the save register 15. In this case, the data in the save register 15 is always arranged in chronological order. All you need to do is add a means to arrange them.

(Embodiment 2) FIG. 2 shows a schematic configuration of an arithmetic processing device in a second embodiment of the present invention, and the same elements as in the embodiment shown in FIG. 1 are given the same reference numerals. .

In FIG. 2, 11 is an instruction code, which includes an arithmetic instruction section OP, a register address W that is updated by executing an instruction, and a register address S that is not updated by executing an instruction.
A register address field 113 consisting of two is stored. Reference numeral 912 denotes an address decoder, which manually decodes the register address using the register address section 11a of the instruction code 11 and selects a register. Reference numeral 13 is an arithmetic register that stores data necessary for the arithmetic operation. ↓ 4 is an arithmetic unit which manually performs arithmetic operations on two data from the arithmetic register 13 through pipeline processing consisting of two stages, and outputs one piece of data. A save register 15 stores data having the same bit width as the data stored in the arithmetic register 13 and a register address W. 16 is a data selector which selects the output data of the arithmetic unit 14 and the save register 1.
One of the data stored in 5 is selected and written to the register address W of the arithmetic register 13. 17 is an address selector, and instruction code 11
and the register address W stored in the save register 15, and outputs the address to the address decoder 2. Reference numeral 18 denotes a conditional branch determination means, which stores whether or not a branch has been executed when a conditional branch instruction is executed, and when a save register restoration instruction is executed, determines whether or not a branch has been taken and executes the branch. Address selector 17 and data
The selector 16 selects the input from the save register 15.

Next, the operation of the second embodiment described in -F will be explained. When the contents of the arithmetic instruction part OP of the instruction code 11 are instructions for writing data to the arithmetic register 13 by executing an operation, the register address part 1 of the instruction code 11 is
1a is input to address decoder 12. At the same time, registers of registers updated by instruction execution
The address W is stored in the save register 15. next,
After the address decoder 12 decodes the input address and selects the arithmetic register 13, the data of the selected register is input to the arithmetic unit 14, and
The data of the register updated by the execution of an instruction is stored in the save register 15. Thereafter, the arithmetic unit 14 finishes the arithmetic operation and stores the data in the arithmetic register 13, so that the pre-update data of the updated register is stored in the save register 15 along with the register address W.
Evacuation is complete. Furthermore, when the contents of the arithmetic instruction section OP of the instruction code 11 are instructions that do not cause data to be written to the arithmetic register 13 upon execution of an arithmetic operation, the above-mentioned saving is not performed. The branch determining means 18 stores the fact that the branch has been executed, and erases the memory after executing the branch destination l instruction after the branch.

Next, when the content of the arithmetic instruction part ○P of the instruction code 11 is a save register restoration instruction, the address selector 17 only when the conditional branch judgment means 18 stores that the branch has been executed. By selecting the register address W stored in the save register 15 and outputting it to the address decoder 12, the register of the arithmetic register 13 is selected, and the data selector 16 selects the data of the save register 15. Data restoration is completed by selecting and outputting to the calculation register 13 and writing the data to the calculation register 13.

As described above, according to the second embodiment, by providing the save register 15, the data selector 16, the address selector 17, and the conditional branch determination means 18 in addition to the arithmetic register, the arithmetic register 13 is When data is written to, the data before updating is always saved, and when the saved data is restored, only when a branch is executed by executing a conditional branch instruction, the last data is saved without specifying the register address of the arithmetic register 13. The pre-update data of the arithmetic register 13 that has been updated can be returned to the arithmetic register 13. As a result, the instruction that is executed regardless of the branch immediately after the conditional branch instruction, which always exists when executing pipeline processing of instruction execution, is executed as an instruction that updates the data in the calculation register 13 on the assumption that there will be no branch. Even when a branch is executed after a branch is executed, by adding a save register restore instruction to the branch destination instruction, the data in the arithmetic register 13 can be restored to the state before the branch execution before executing the instruction after the branch. can be done. Furthermore, when a save register return instruction is executed as a non-branch destination instruction, the conditional branch judgment means 18 does not execute the return, so the state of the arithmetic register 13 does not change, and the save register return instruction is completely different from a conditional branch instruction. Can be used as a pair.

Note that since this embodiment uses the arithmetic unit 14 that executes arithmetic operations by a two-stage pipeline process, only one instruction is executed regardless of the branch immediately after the conditional branch instruction, and the save register is The data that can be stored in the save register 15 is only -, but when using an arithmetic unit that executes operations by pipeline processing with a large number of stages, the save register 15 should be configured to store multiple pieces of data. What is necessary is to add a means for always arranging the data in 15 in chronological order. Even in this case, the number of data stored in the save register may be the same as the number of instructions to be executed regardless of the branch immediately after the conditional branch instruction.

As described in detail, according to the present invention, when data is written to an arithmetic register by execution of an arithmetic operation, the pre-update data is always saved, and the pre-update data of the last updated arithmetic register is restored. In some cases, it is possible to return to the arithmetic register without specifying the register address of the arithmetic register, thereby preventing an increase in the number of instructions.

According to the present invention, only when a branch is executed by executing a conditional branch instruction, the data before update of the last updated arithmetic register is returned to the arithmetic register without specifying the register address of the arithmetic register. Therefore, it is possible to place an instruction that updates data in an operation register as an instruction that is executed regardless of the branch immediately after the conditional branch instruction that always exists when executing instructions in a pipeline. Even if a branch is executed and it is necessary to restore the data in the arithmetic register to the state before execution of the branch instruction, the data can be restored by placing a save register restoration instruction in the branch destination instruction. For this reason, a normal arithmetic instruction with no restrictions on the usable arithmetic registers is placed at the position of the instruction that is executed regardless of the branch immediately after the conditional branch instruction, whereas conventionally a non-executable instruction was placed in most cases. This can significantly reduce the number of instructions even if the number of instructions for return is subtracted, especially if the instruction arrangement is such that conditional branch instructions do not branch most of the time and only occasionally branch. can be reduced,
The effect is great. Furthermore, even when automating instruction placement, it is possible to place arithmetic instructions consecutively without considering whether a conditional branch instruction will branch or not, making it easier to automate instruction placement. has.

[Brief explanation of the drawing]

8. FIG. 1 is a schematic block diagram of the arithmetic processing device in the first embodiment of the present invention, FIG. 2 is a schematic block diagram of the arithmetic processing device in the second embodiment of the present invention, and FIG. 3 is a schematic block diagram of the arithmetic processing device in the second embodiment of the present invention. FIG. 2 is a schematic block diagram of a processing device. DESCRIPTION OF SYMBOLS 11... Instruction code, lla... Register address part, 12... Address decoder, 13... Arithmetic register, 14... Arithmetic unit, 15... Save register, 16... Address・Selector, 17...Data・
Selector, 18... Conditional branch judgment means.

Claims (2)

[Claims] (1) An address decoder that receives the register address part of the instruction code as an input, one or more arithmetic registers selected by the address decoder, and pipeline processing of instruction execution using the values of the arithmetic registers as inputs. an arithmetic unit, one or more save registers that store the value of the arithmetic register and the register address that are updated for each executed instruction, and one or more of the output of the arithmetic unit and the value of the save register after the instruction is executed. a data selector that selects one and outputs it to the arithmetic register, and a data selector that selects one from the register address part of the instruction code and the register address stored in the save register and outputs it to the arithmetic register; An arithmetic processing unit equipped with an address selector that outputs to. (2) When executing a register restore instruction to write data stored in a save register to an arithmetic register, it is determined whether a conditional branch instruction has been executed or not, and the address selector and data selector input from the save register. 2. The arithmetic processing device according to claim 1, further comprising conditional branch determination means for selecting.