JPH0667879A - Pipeline processing computer - Google Patents

Abstract

(57) [Abstract] [Purpose] A pipeline processing computer that executes one instruction as multi-flow processing divided into a plurality of flows as necessary. It is possible to maintain the interdependence of data correctly by using a scoreboard. [Constitution] A final flow detecting means 10 for detecting a final flow of a plurality of flows in a multi-flow process, and a content stored in a scoreboard 12 corresponding to the above-described mutual dependency of data is updated in the detected final flow. And a scoreboard update control means 11 for controlling the scoreboard.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to checking data dependency between a preceding instruction executed and an instruction executed subsequent to the preceding instruction. The present invention relates to a pipeline processing computer equipped with a scoreboard.

In a computer that executes pipeline processing, data dependence between an instruction executed first and an instruction executed subsequent to the preceding instruction, for example, the result of the operation by the first instruction is If there is a relationship such that it is used as operation data in the instruction, it is necessary to perform processing that does not disturb the dependency. As a control method for managing the mutual dependency relationship of data used for the calculation, there is a method using a scoreboard.

In this method, a scoreboard is provided as a storage means for indicating whether the register is in use or not, corresponding to each general purpose register. When executing an instruction that requires writing to a general-purpose register, the bit on the scoreboard corresponding to that register number is set to indicate that writing to that register is performed. When the result is written to a general register by an instruction, the scoreboard bit corresponding to that register number is reset, indicating that the write is complete.

In the subsequent instruction, in order to confirm whether or not the register is rewritten by the instruction that is executed in advance, the scoreboard bit corresponding to the number of the register that stores the operation data is read out, If it is set, it means that the rewriting by the preceding executing instruction has not been completed.
It is necessary to wait for the start of calculation. If the scoreboard bit is reset, the preceding executing instruction does not rewrite the contents of the register, i.e., the succeeding instruction waits for the operation to start, resulting in the register executing the preceding executing instruction. Since the rewriting has been completed, the calculation of the subsequent instruction can be started.

The necessity of processing using the scoreboard will be described with reference to FIGS. 7 and 8. FIG. 7 shows that the mutual relationship of data may not be processed correctly when the completion of writing to the register by the preceding instruction is not waited. In the figure, the first multiplication instruction (multi)
Then, an instruction for multiplying the contents of the register 2 (gr2) and the contents of the register 3 (gr3) and storing the result in the register 4 is shown, and the addition instruction (ad
In d), the contents of the register 5 and the contents of the register 6 are added, and the instruction to store in the register 4 is shown. Also, in the addition instruction as the third instruction, which is a little distant, the addition as the second instruction is performed. The instruction to store the result of the instruction in the register 8 by adding the content of the register 4 and the content of the register 7 is shown. In this case, if the processing is executed without using the scoreboard, as shown in the figure, for example, in the multiplication instruction as the first instruction, the operation execution (E) stage has three stages.
Because of the stage, in the processing of the addition instruction as the third instruction, the contents of the register 4 in which the result of the multiplication instruction as the first instruction is stored is read and the addition is executed, which is incorrect. The result will be obtained.

FIG. 8 shows the processing when the subsequent instruction waits for the completion of data writing to the register by the preceding instruction.
In the figure, by setting the scoreboard bit for register 4 to "1" at the first execution (E) stage of the multiplication instruction as the first instruction, the result is written in register 4 and the scoreboard bit is set to "1". The execution of the second addition instruction is interlocked until it becomes 0 ′, that is, until it is reset, which indicates that the processing of reading the correct data is performed in the processing of the second addition instruction.

Setting a bit on the scoreboard means that the value of the register cannot be read (cannot be written). Many execution stages of basic instructions such as add instructions generally have only one stage, and the result generated in the execution stage by the bypass function can be read as data. There is no possibility that an instruction whose execution stage ends in one stage will be overtaken by a succeeding instruction to perform an erroneous operation, as shown in FIG. Therefore, basic instructions such as addition instructions, that is, instructions that can be executed in one flow and take only one stage and have the shortest execution time, prevent mutual interference of data without setting / resetting the scoreboard. You can

FIG. 9 is a block diagram of a conventional example of a pipeline computer using a scoreboard. In the figure, a pipeline computer includes an instruction decoder 1 for decoding an instruction code, a general purpose register (GR) 2 for storing operation data and an operation result, for example, an operation unit 3 as an adder,
For example, the operation unit 4 as a shifter, the operation data for the operation unit 3, that is, the operand registers 3a and 3b holding the operand, the operand registers 4a and 4b holding the operand for the operation unit 4, the scoreboard 5, and the pipeline operation are controlled. A pipeline controller 6, a pipeline tag register 7 for holding a pipeline tag under the control of the pipeline controller 6,
And an AND circuit 8.

In FIG. 9, the instruction code is decoded by the instruction decoder 1, the source register address 0 and the source register address 1 are obtained as the read register number, and the destination register address is obtained as the write register number. Read data 0 and read data 1 as source operands are input to the read register port of GR2 and held in the respective operand registers 3a, 3b, 4a, and 4b. The outputs of these operand registers are input to the arithmetic units 3 and 4, and the arithmetic results are input to the write data port of GR2 as write data. At the same time as this operation result, the destination register address as the write register number is input to the write register port of GR2 as the write register address with the timing adjusted by the pipeline tag register 7. The write control signal is also generated by the instruction decoder 1 and input to the GR 2 at a timing adjusted by the pipeline tag register 7, but this control signal is not shown.

The above is the operation when there is no mutual interference of data, but when there is mutual interference of data, the read register number and the write register number output from the instruction decoder 1 are the read registers of the scoreboard 5. It is input to the check port (RD0 CHK, RD1 CHK) and the write register check port (WR CHK), and these register numbers are used as selection signals for selecting the registers in the scoreboard 5 that indicate busy / unused. Used. Signals from selected registers SRC0 REG BUSY, SRC1 REG B
USY and WR REG BUSY are input to the pipeline controller 6 and are used to determine whether to interlock the decode stage as shown in FIG.

The above-mentioned 3 to the pipeline controller 6
If any one of the two signals indicates that the scoreboard bit is '1', the output of the D stage release signal, that is, the signal indicating that the decode stage may be completed and the execution stage may be performed is suppressed. To be done.

In the preceding instruction, for example, the writing to the register is completed, the register in the scoreboard 5 indicating the busy / unused state is reset, and the above-mentioned three signals to the pipeline controller 6 are all set. When the scoreboard bit comes to indicate that it is not set, the D stage signal is output to the four operand registers, and the signal is sent to the clock enable terminal of the D flip-flop in the pipeline tag register 7. To the AND circuit 8 in front of the scoreboard 5.

As a result, the execution stage processing for the subsequent instruction is performed. At this time, the destination register address from the instruction decoder 1 provided as the other input of the AND circuit 8 is input to the WR SET terminal of the scoreboard 5. The bit of the scoreboard that is given and corresponds to the write register number is set. Furthermore,
When the E-stage release signal output from the pipeline controller 6 is input to the pipeline tag register 7, the destination register address is used as a write register address of the scoreboard WR RE.
This write register address is applied to GR2 as described above while being applied to the S terminal to reset the corresponding scoreboard bit.

[0014]

Before describing the problems to be solved by the present invention, the multiflow processing and the use of the scoreboard at the time of parallel execution of instructions will be described first. The multi-flow process is also called a stage expansion process, and is a process in which one instruction is divided into a plurality of flows and executed as if it were a plurality of instructions.

For example, when executing an instruction to transfer the value of two 4-byte general purpose registers (GR) as a pair to an 8-byte floating point register (FR), only one port is used on the side of the general purpose registers. The multi-flow process is a process in which four bytes are read at a time and transferred to the floating point register twice. Figure 10
Is an example of this processing, and shows that the stored contents of the register pair indicated by r1 and r1 + 1 are transferred in two divided flows.

FIG. 11 shows an example of multiflow processing for a multiplication instruction. Generally, the multiplication instruction is executed less frequently, and even if the performance is lowered, the influence on the performance of the entire system is small. Therefore, in FIG. 11, two pieces of operation data for multiplication are transferred to the multiplier in two divided flows, whereby the bus width of the data bus for transferring the operation data is reduced.

However, FIG. 12 shows an example of a hang-up state when a scoreboard is set in a multiplication instruction for performing such multi-flow processing. FIG. 12 shows a state in which the content of register 2 is multiplied by the content of register 3 and the multiplication instruction for storing the result in register 3 is divided into two flows and executed. First, in the first flow, the contents of register 2 are sent to the multiplier, but in order to store the multiplication result in register 3, the scoreboard bit corresponding to register 3 is set in the execution stage of the first flow. . Therefore, even if an attempt is made to read the contents of the register 3 in the second flow, the bit cannot be read because the bit of the scoreboard is set, and the state becomes the interlock. This scoreboard bit is reset by writing to register 3, but it is not reset until the result of the execution stage of the second flow is obtained, and it is permanently set because the second flow is interlocked in the decode stage. It cannot be reset and will be in a hang-up state. Such a hang-up state is a hard failure state, which is also called a deadlock, and is a state in which it cannot be eliminated forever. On the other hand, in the interlock state shown in FIG. 8, the process is restarted by resetting the scoreboard bit.

Next, problems in parallel execution of instructions will be described. FIG. 13 is an explanatory diagram of the problem. In this example, the addition instruction and the multiplication instruction are executed in parallel. In the addition instruction, the contents of register 1 and the contents of register 2 are added and stored in register 3, and in the multiplication instruction, the contents of register 2 and register 3 are added. The contents of and are multiplied, and the result is stored in the register 3. Of these instructions, the add instruction finishes in the first three stages, while the multiply instruction is split into two flows, ie performed as a multi-flow process.

In order to avoid the problem described with reference to FIG.
For example, even if the scoreboard bit is set when reading the contents of the register 3 in the second flow of the multiplication instruction,
At this time, the result of the addition instruction is stored in the register 3, and the processing of the multiplication instruction is performed using this addition result. In this way, for parallel execution of instructions, the scoreboard bit is set in consideration of the interdependence of data, and the execution of the basic instruction as the instruction with the shortest execution time considers the interdependence of data. There is a problem that it is necessary to delay.

According to the present invention, when an instruction which requires multi-flow processing is executed, processing is performed while correctly maintaining the interdependence of data by the scoreboard, and an instruction and multi-flow processing which can be executed by a single flow. That is, it is possible to execute a correct process without impairing the interdependency of data in parallel execution with a required instruction.

[0021]

FIG. 1 is a block diagram showing the principle of the present invention. The figure includes a scoreboard that checks the data dependency between the instruction that is executed first and the instruction that is executed subsequently to that instruction, and divides one instruction into multiple flows. It is a principle block diagram of a pipeline processing computer that can be executed by.

In FIG. 1, the final flow detecting means 10
Is, for example, a multi-flow controller, which detects the final flow of the multi-flow process as a process in which one instruction is divided into a plurality of flows and executed. Further, the scoreboard update control means 12 is, for example, the scoreboard 1
The two AND circuits are provided on the input side of 1 to update the stored contents of the scoreboard 11 corresponding to the above-mentioned data dependency in the final flow of the multi-flow process.

[0023]

According to the present invention, the stored contents update processing of the scoreboard, that is, the set / reset processing is performed only in the processing for executing one instruction by dividing it into a plurality of flows, that is, in the final flow of the multiflow processing. The operation of the present invention will be described with reference to FIG.

As described with reference to FIG. 1, in the present invention, when the final flow detecting means 10 detects the final flow of the multiflow processing, for example, the score corresponding to the register in which the result of executing the instruction of the flow is written. The board bit is set. This setting is performed by the scoreboard update control means 12. In FIG. 2, the same instruction as in FIG. 12 is processed, but in FIG. 12, when it is found that the multiplication result is stored in the register 3 in the first flow, the scoreboard is executed in the execution stage of the first flow. Although the bit is set to "1", the scoreboard is set in the second flow in FIG. 21, that is, the first execution stage of the final flow.
As a result, the contents of the register 3 are transferred to the general-purpose register GR in the first execution stage of the second flow, and then the multiplication process is executed and the multiplication result is stored in the register 3, and the scoreboard bit is "0". Is reset to.

As described above, in the present invention, the scoreboard setting / setting is performed only in the final flow of the multiflow processing.
Reset processing is performed. As a result, processing that does not disturb the data dependency between the preceding instruction and the subsequent instruction is guaranteed by the processing including the pipeline interlock.

When an instruction that requires multi-flow processing and an instruction that does not need multi-flow processing are executed simultaneously, the set / reset processing of the scoreboard is performed in the final flow of the multi-flow processing, and the instruction that does not require multi-flow processing. Is also delayed until the final flow of the multiflow process.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a block diagram showing the overall configuration of a pipeline processing computer of the present invention. In the figure, the same parts as those in the conventional example of FIG. 3 is different from the conventional example of FIG. 9 in that a multiflow controller 20 for detecting the final flow in the multiflow processing is added, and an AND circuit 21 is provided on the input side of the scoreboard 5 instead of the AND circuit 8. , And AND circuit 22
Is provided.

To the multiflow controller 22, a two-flow operation signal indicating that the multiflow is divided into two flows or a threeflow operation signal indicating that the multiflow is divided into three flows is input from the instruction decoder 1. Further, a D stage release signal is input from the pipeline controller 6. The last flow detection signal from the multiflow controller 20 is input to the two AND circuits 21 and 22, and the flow counter signal is output to the instruction decoder 1. In addition to the last flow detection signal, the destination register address indicating the write register number and the D stage release signal are input to the AND circuit 21 as well as in FIG. Register set inputs are provided. Further, the AND circuit 22 is given the write register address from the pipeline tag register 7 together with the last flow detection signal, and when these signals are aligned, the write register reset signal is input to the scoreboard 5.

An outline of the processing of each stage in FIG. 3 will be described. First, in the decode (D) stage, an instruction is decoded to decode that it is a multi-flow instruction, the number of flows required to execute the instruction, and the instruction that requires updating of the scoreboard. The decoded result and the value of the multiflow counter are held in the pipeline tag and used in the subsequent stages.

The number of bits on the scoreboard corresponding to the write register number is checked, and if set, interlocked at the instruction decode stage. Check the number of bits on the scoreboard corresponding to the read register number,
If set, interlock at the instruction decode stage.

In the case of a multi-flow instruction, the output of the multi-flow counter, which indicates which flow is currently being processed, shows a value equivalent to the fact that the first flow is always executed when it is not a multi-flow instruction. ing. In order to detect the final flow, the value of the multiflow counter is compared with the number of flows required to execute the instruction. If it is not a multiflow instruction, the multiflow counter always shows a value equivalent to that of executing the first flow, so that it is detected that it is the final flow.

In the operation execution (E) stage, in addition to the operation execution, if the instruction executing the operation stage is an instruction that requires the update of the scoreboard and the final flow is being executed, it corresponds to the write register number. Set the scoreboard bit. Some instructions may read registers at this stage.

In the write (W) stage, in addition to processing such as writing the result obtained in the operation stage to the register, the instruction executing the write (W) stage is an instruction requiring updating of the scoreboard, and If the final flow has been executed, the bit on the scoreboard corresponding to the write register number is reset.

FIG. 4 is a block diagram of an embodiment of the multi-controller. In the figure, the multi-controller 2
0 is a two-flow operation from the instruction decoder 1,
An OR circuit 23 to which the three-flow operation signal is input, an inverter 24 to which the output of the OR circuit 23 is given, an AND circuit 25 to which the D stage release signal and the clock signal output from the pipeline controller 6 are input, and a flow counter 26. An AND circuit 27 to which the output of the flow counter 26 and the two-flow operation signal are input, an AND circuit 28 to which the output of the flow counter 26 and the three-flow operation signal are input, the outputs of the inverter 24, the AND circuits 27 and 28 are input. The OR circuit 29 and the inverter 30 that inverts the output of the OR circuit 29.

In FIG. 3, the instruction decoder decodes the number of flows of the instruction to be executed.
In case of multi-flow instruction, FLOW COUNTE
The flow number of the instruction currently being executed is taught by the value of R, and it is detected that it is the final flow (LAST
FLOW signal), if it is the final flow, update control of the program counter and selection of an instruction from the instruction buffer (kyu) are performed.

The instruction decoder is a FLOW COUNTER
Depending on the flow, the same instruction may be used to partially change the decoding result. For example, in the transfer from GR to FR described in FIG. 10, two register numbers are read by giving different read register numbers to the first flow and the second flow.

In FIG. 4, the two-flow operation and three-flow operation signals are not output from the instruction decoder 1 for an instruction processed by a single flow that is not a multi-flow processing, and the output of the OR circuit 23 is'. 0 ', the output of the inverter 24 becomes'1', and the output of the OR circuit 29 indicates that the flow is the last flow.

On the other hand, when the multi-flow processing consists of two flows, the two-flow operation signal is given from the instruction decoder 1 to the uppermost input terminal of the AND circuit 27. Therefore, the output of the AND circuit 27 becomes "1" when "1" is given to the second input terminal from the top and "0" is given to the third input terminal, and the output of the OR circuit 29 shows the last flow. become. That is, at this time, the output of the flow counter is "01". AND circuit 2
The D-stage release signal from the pipeline controller 6 is input to the signal 5 along with the clock signal, and the output of the flow counter 26 is incremented if the D-stage release signal is given at the rising edge of the clock signal. When the flow in the multi-flow process is "2", the output of the flow counter 26 is "0" for the first flow, and the D stage indicating that the D stage of the second flow is completed. When the release signal is input, the output of the flow counter 26 becomes "1". As a result, the OR circuit 29 outputs the last flow detection signal.

When the multi-flow processing consists of three flows, the three-flow operation signal is given to the uppermost input terminal of the AND circuit 28, and the AND circuit 28 is supplied.
Is "1" when the input to the second input terminal is "0" and the input to the third input terminal is "1". That is, the output of the flow counter 26 is "2", that is, "10" when the D stage release signal is input for the third flow, and at this time point, the OR circuit 29 outputs the last flow detection signal. .

Further, in FIG. 4, when the D stage release signal is "1" and the last flow detection signal is "1" at the rising of the clock signal, that is, after the last flow is detected, the first of the next multiflow processing is performed. Flow counter is reset when the D stage release signal is output for the flow of, and the flow counter is incremented when the D stage release signal is "1" and the last flow detection signal is "0" at the rising of the clock signal. It is shown that the output of the flow counter does not change when the D stage release signal is "0" at the rising edge of the clock signal. This operation is performed by the inverter 30.

FIG. 5 is a block diagram of a scoreboard according to an embodiment of the present invention. In the figure, the scoreboard is composed of two 4-input 16-output decoders 33, 34, 16 SR flip-flops 35, and 3 16-input 1-output selectors 36, 37 and 38.

In FIG. 5, the decoder 33 sets any of the 16 SR flip-flops 35 when the D stage write enable signal (D WE) is input according to the contents of the 4-bit WR SET signal from the AND circuit 21. The decoder 34 resets one of the SR flip-flops 35 when the W stage write enable signal (W WE) is input according to the contents of the 4-bit WR RES signal output from the AND circuit 22.

Next, the selector 36 outputs the read register number SRC REG AD output from the instruction decoder 1.
Input signal RD0 to the scoreboard read register check port as R0 signal RD0 SRC0 which provides any one output of 16 SR flip-flops 35 to the pipeline controller 6 according to the contents of 4 bits.
It is output as a REG BUSY signal. Similarly, the register 37 outputs one of the outputs of the 16 flip-flops SRC1 according to the contents of the input signal RD1 CHK4 bit to the read register check port.
The selector 38 outputs it to the pipeline controller 6 as a REG BUSY signal, and the selector 38 outputs one of the outputs of the 16 flip-flops 35 as a WR REG BUSY signal according to the contents of the input signal WR CHK 4 bits to the write register check port. It is output to the controller 6.

FIG. 6 is a block diagram showing the configuration of an embodiment of the pipeline controller. In FIG. 3, the pipeline controller 6 has three BUSs from the scoreboard 5.
The Y signal and the other interlock condition signals are provided, but the three BUSY signals and the other D stage interlock condition signals are input to the OR circuit 40. The AND circuit 41 receives the output of the OR circuit 40, a D stage valid signal, that is, a signal indicating that there is an instruction executing the D stage, and the output of an AND circuit 45 described later. The output of the AND circuit 41 is a D stage release signal indicating that the instruction executing the D stage is completed, and its value is the D stage valid signal being “1”, and the OR circuit 40 and the AND circuit 45 output the value. It becomes "1" when both outputs are "0". That is, even if the D stage valid signal is "1" and the D stage is valid, the OR circuit 40 outputs "1" and there is a D stage interlock condition, or the AND circuit 45 outputs "1". If the instruction being output is interlocked, the output of the AND circuit 41 is "1".
It does not become. This is because, for example, if an instruction executed in the D stage progresses to the E stage, for example, a register is overwritten without completing the interlocked instruction in the E stage. Interlock by board inspection is considered to be one of the D interlock conditions.

The D stage release signal as the output of the AND circuit 41 is an E stage valid signal via the flip-flop 42, that is, a signal indicating that there is an instruction executing the E stage by the end of the D stage. 43 and 45. The AND circuit 43 includes a pipeline controller 6 in FIG.
E as another interlock condition signal to
The stage interlock condition signal and the output of the AND circuit 48 described later are given, and these two signals are supplied to the AND circuit 45 via the OR circuit 44.
Is given to. That is, the output of the AND circuit 45 is
As described above, the instruction executed in the E stage is interlocked by the E stage interlock condition.

As for the output of the AND circuit 43, the E stage valid signal is "1" and both the E stage interlock condition signal and the output of the AND circuit 48 are "0".
When it is, it becomes '1'. The output of the AND circuit 43 indicates that the E stage release signal, that is, the instruction executing the E stage is completed. Even if the E stage is valid, the E stage interlock condition is generated as in the D stage release signal. There is or W
If the instruction to be executed at the stage is interlocked, its value will not be '1'. That is, if the instruction executed in the E stage advances to the W stage, the instruction interlocked in the W stage will be overwritten to the register, for example, without completing the instruction.

The output of the AND circuit 43, that is, the E stage release signal is given to the AND circuit 47 via the flip-flop 46 as a W stage valid signal indicating that there is an instruction executing the W stage. A W stage interlock condition signal is given to the AND circuit 47, and when the W stage valid signal is "1" and the W stage interlock condition signal is "0", the AND circuit 47 outputs the W stage release signal. , That is, a signal indicating that the instruction executing the W stage is completed is output. On the other hand, the W stage valid signal and the W stage interlock condition signal are input to the AND circuit 48,
When these are "1", the output of the AND circuit 48 becomes "1", and the output is the AND circuit 43 as described above.
And the OR circuit 44.

Next, an embodiment of the present invention when executing parallel instructions will be described. In order to solve the problem described in FIG. 13, in the case where an instruction that requires multi-flow processing and an instruction that requires only a single flow are executed in parallel, the scoreboard in the final flow of the multi-flow processing It is necessary to perform set / reset and delay execution of instructions for a single flow only until the point of its final flow.

Therefore, for example, when a load instruction (memory access instruction) and a multiply instruction are executed simultaneously, execution of the load instruction as a single flow and setting / resetting of the scoreboard are delayed until the final flow of the multiply instruction. This makes it possible to perform processing to prevent mutual interference of data.

In the embodiment described above, the number of data used for the calculation is two, and therefore the number of read registers is two.
Although the case where the number of the write registers is one and the number of the write registers is one has been described, it goes without saying that the numbers of these data and registers are not limited to this. In addition, these register numbers (addresses)
Is 4 bits, and therefore the number of flip-flops in the scoreboard in FIG. 5 is 16, but the number of bits and the number of flip-flops are not limited to this. Furthermore, the multiflow controller in FIG. 4 has been described with the number of multiflow flows being two or three, but the number of multiflow processing flows is not limited to this.

[0051]

As described in detail above, according to the present invention, the interdependence of data is destroyed by using the scoreboard even for multi-flow processing in which one instruction is divided into a plurality of flows and processed. It is possible to perform processing without using the scoreboard, and set / set the scoreboard for instructions that require multiflow processing even when the instructions are executed in parallel.
By performing the reset in the final flow and delaying the execution of an instruction that does not require multiflow processing until the final flow, mutual interference of data can be resolved.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing how a multiply instruction is executed in the present invention.

FIG. 3 is a block diagram showing a configuration of an embodiment of a pipeline processing computer according to the present invention.

FIG. 4 is a block diagram showing a configuration of an embodiment of a multi-flow controller.

FIG. 5 is a block diagram showing a configuration of an embodiment of a scoreboard.

FIG. 6 is a block diagram showing a configuration of an embodiment of a pipeline controller.

FIG. 7 is a diagram showing an operation when a subsequent instruction does not wait for completion of the preceding instruction.

FIG. 8 is a diagram showing an operation of processing using a scoreboard.

FIG. 9 is a block diagram showing a configuration of a conventional example of a pipeline processing computer.

FIG. 10 is a diagram illustrating an example of multiflow processing.

FIG. 11 is a diagram illustrating an example of multiflow processing of a multiplication instruction.

FIG. 12 is a diagram showing an example of a hang-up state of a multiplication instruction.

FIG. 13 is a diagram illustrating a problem in parallel execution of instructions.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 instruction decoder 2 general purpose register (GR) 3,4 arithmetic unit 5,11 scoreboard 6 pipeline controller 7 pipeline tag register 10 final flow detection means 12 scoreboard update control means 20 multiflow controller

Claims (2)

[Claims] 1. A scoreboard for checking a data dependency between a preceding instruction executed and an instruction executed subsequent to the preceding instruction, and one instruction is provided in a plurality of flows. In a pipeline processing computer that can be executed separately, a final flow detecting means (10) for detecting a final flow of the plurality of flows, and a scoreboard () corresponding to the dependency in the detected final flow ( A pipeline processing computer, comprising: a scoreboard update control means (11) for updating the stored contents of 12), and guaranteeing a process that does not disturb the dependency. 2. When the pipeline processing computer has at least one instruction to be executed in parallel in a plurality of flows among the instructions to be executed in parallel, , Updating the stored content of the scoreboard in the final flow of the plurality of flows, and executing the instruction and updating the stored content of the scoreboard for instructions that can be executed in a single flow. 2. The pipeline processing computer according to claim 1, wherein the pipeline processing computer delays until a final flow of an instruction to be executed divided into a plurality of flows.