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JPH03159118A - Method for thermally treating single-crystal gallium arsenide wafer - Google Patents

Method for thermally treating single-crystal gallium arsenide wafer

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Publication number
JPH03159118A
JPH03159118A JP29848289A JP29848289A JPH03159118A JP H03159118 A JPH03159118 A JP H03159118A JP 29848289 A JP29848289 A JP 29848289A JP 29848289 A JP29848289 A JP 29848289A JP H03159118 A JPH03159118 A JP H03159118A
Authority
JP
Japan
Prior art keywords
heat treatment
wafer
gallium arsenide
crystal
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29848289A
Other languages
Japanese (ja)
Inventor
Tomoki Inada
稲田 知己
Seiichi Okubo
誠一 大久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP29848289A priority Critical patent/JPH03159118A/en
Publication of JPH03159118A publication Critical patent/JPH03159118A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は不純物イオンを注入された砒化ガリウム単結晶
ウェハを熱処理する方法に係り、特に熱処理に要する経
済性と特性の均一性を改善したちの関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of heat treating a gallium arsenide single crystal wafer implanted with impurity ions, and particularly to a method for improving the economy and uniformity of properties required for heat treatment. Concerning.

[従来の技術] 砒化ガリウム半導体ウェハは、電子の高速性、磁電変換
特性及びそれらの特性が環境温度の変化に対して安定し
ていることなどの優れた特長を有している。このため、
FET(電界効果トランジスタ)、IC,LSIなどの
高周波、高速素子あるいはホール素子など工業的に極め
て重要な素子のための材料として使用される。それらの
素子では回路中の電流を流すためのチャネルを作る場合
に、キャリアとして電子を使う場合が多く、そのチャネ
ル層を作る方法として、イオン注入法が用いられる。
[Prior Art] Gallium arsenide semiconductor wafers have excellent features such as high electron speed, magnetoelectric conversion properties, and stability of these properties against changes in environmental temperature. For this reason,
It is used as a material for industrially extremely important devices such as FETs (field effect transistors), high frequency and high speed devices such as ICs and LSIs, and Hall devices. In these devices, electrons are often used as carriers when creating a channel for current to flow in the circuit, and ion implantation is used as a method for creating the channel layer.

ここでは、例として半絶縁性の砒化ガリウムウェハ表面
に不純物イオンであるSi、、”  イオンを打ち込む
ことによってチャネル層を作る場合について説明する。
Here, as an example, a case will be described in which a channel layer is formed by implanting impurity ions, such as Si ions, into the surface of a semi-insulating gallium arsenide wafer.

数十〜画数+KeVのエネルギに加速されたSi、、”
  イオンを半絶縁性砒化ガリウムウェハ表面に打ち込
み、そのウェノ\を700〜900℃で数十分加熱する
と、半絶縁性砒化ガリウムウェハ表面にn型導電性の層
が生じる。これをチャネルとして用い、フォトリングラ
フィ法により微細な回路を描画することにより素子が作
製できる。打ち込んだS I+t8イオンはGa位置を
占めることによりn型特性を示すが、打ち込んだままで
は置換位置を占めない。また結晶表面は打ち込んだイオ
ンにより損傷してアモルファス化している。打ち込んだ
後に熱処理を施す理由は、加熱することによりSi”、
、イオンが置換位置を占めるようにすることと、結晶の
乱れを緩和することにある。このとき、結晶ウェハ中に
アクセプタとなる不純物があると、打ち込んだイオンか
ら出される電子が補足され、見掛は上清性化しなくなる
。打ち込んだイオンに対する活性化されたイオンの割合
を活性化率と呼ぶが、活性化率は素子特性を左右する重
要なパラメータである。
Si accelerated to an energy of several tens to strokes + KeV.”
When ions are implanted into the surface of a semi-insulating gallium arsenide wafer and the wafer is heated at 700 to 900° C. for several minutes, an n-type conductive layer is formed on the surface of the semi-insulating gallium arsenide wafer. Using this as a channel, a device can be manufactured by drawing a fine circuit using photolithography. The implanted S I+t8 ions exhibit n-type characteristics by occupying Ga positions, but do not occupy substitution positions as they are implanted. Furthermore, the crystal surface is damaged by the implanted ions and becomes amorphous. The reason for heat treatment after implantation is that by heating, Si”,
, to allow ions to occupy substitution positions and to alleviate crystal disorder. At this time, if there are impurities that act as acceptors in the crystal wafer, the electrons emitted from the implanted ions are captured, and the crystal wafer does not appear to be a supernatant. The ratio of activated ions to implanted ions is called activation rate, and activation rate is an important parameter that influences device characteristics.

素子を集積化する場合には、個々の素子の活性化率が同
一でなければならない。また、個別素子の場合でも、特
性の揃った素子を再現性よく生産するためには、同一ウ
エバ内に作られる個々の素子の活性化率が揃う必要があ
る。
When integrating elements, the activation rate of each element must be the same. Furthermore, even in the case of individual elements, in order to produce elements with uniform characteristics with good reproducibility, it is necessary that the activation rates of the individual elements manufactured in the same web be the same.

しかし、結晶ウェハ中には結晶欠陥に基づくと考えられ
るアクセプタレベルやそれらの生成消失及び電気的な補
償に関与するドナーレベルが存在し、通常それらは不均
一に存在する。そのためウェハ面内で均一な活性化率を
得ることはむつかしく、その改善のため結晶そのものを
熱処理して均一性の改善を図ったり、イオンを打ち込む
前のウェハを熱処理することが行われる。
However, in a crystal wafer, there are acceptor levels that are considered to be based on crystal defects and donor levels that are involved in their generation/disappearance and electrical compensation, and these usually exist non-uniformly. Therefore, it is difficult to obtain a uniform activation rate within the wafer plane, and to improve this, the crystal itself is heat-treated to improve uniformity, or the wafer is heat-treated before ion implantation.

[発明が解決しようとする課題] 上述したように従来行われている、結晶そのものの熱処
理や、イオン打込み前のウェハの熱処理でも均一性はか
なり改善される(例えば特開昭62−226900号公
報)。
[Problems to be Solved by the Invention] As mentioned above, the uniformity can be considerably improved by the conventional heat treatment of the crystal itself or the heat treatment of the wafer before ion implantation (for example, as disclosed in Japanese Patent Laid-Open No. 62-226900). ).

しかし、この方法には次の2つの欠点がある。However, this method has the following two drawbacks.

第1は結晶やウェハを無処理で用いる場合に比ベニ程が
増える分の経済的デメリットが生じること、第2はイオ
ン打込み前に均一性が改善されても、打込み後のイオン
を活性化するための熱処理で再び不均一性が生じてしま
う場合があることである。
The first is that when crystals or wafers are used without any treatment, there is an economic disadvantage due to the increase in burr compared to the other, and the second is that even if the uniformity is improved before ion implantation, it is difficult to activate the ions after implantation. The problem is that non-uniformity may occur again during heat treatment.

第1点については、無処理結晶ウェハよりも特性の改善
がなされ、経済的効果が大きい点との取引となる。第2
点については、実際に活性化熱処理に用いられる700
〜900℃の温度では前出のアクセプタが生じやすく、
また不均一に分布しやすいということがわかっている。
Regarding the first point, the characteristics are improved compared to untreated crystal wafers, and the economic effect is large. Second
Regarding the point, 700, which is actually used for activation heat treatment,
At temperatures of ~900°C, the above-mentioned acceptor is likely to occur,
It is also known that it tends to be unevenly distributed.

この不均一分布はウェハ上にFETを作成したときのし
きい値電圧のバラツキとなって現れる。
This non-uniform distribution appears as variations in threshold voltage when FETs are fabricated on the wafer.

本発明の目的は、前記した従来技術の欠点を解消し、イ
オン注入法を用いて作られる砒化ガリウム半導体素子の
活性化率の均一性を向上でき、しかもこの均一性の向上
が経済的に図れる砒化ガリウム単結晶ウェハの熱処理方
法を提供することにある。
It is an object of the present invention to eliminate the drawbacks of the prior art described above, to improve the uniformity of the activation rate of gallium arsenide semiconductor devices manufactured using the ion implantation method, and to improve this uniformity economically. An object of the present invention is to provide a method for heat treating a gallium arsenide single crystal wafer.

[課題を解決するための手段] 本発明の砒化ガリウム単結晶ウェハの熱処理方法は、イ
オン注入後の砒化ガリウム単結晶ウェハの熱処理におい
て、従来とは極めて異なる特殊な熱処理を施すことにあ
り、それによって、注入イオンの活性化と、ウェハ特性
の均質化を同時に実現できる点にある。
[Means for Solving the Problems] The heat treatment method for gallium arsenide single crystal wafers of the present invention consists in performing a special heat treatment that is extremely different from conventional heat treatment in the heat treatment of gallium arsenide single crystal wafers after ion implantation. This allows activation of implanted ions and homogenization of wafer characteristics at the same time.

熱処理条件としては、第1図に示すように、砒化ガリウ
ム単結晶ウェハ表面に所望の不純物イオンを打ち込んだ
後、3段階のプロセスを要する。
As shown in FIG. 1, the heat treatment conditions require a three-step process after desired impurity ions are implanted into the surface of a gallium arsenide single crystal wafer.

まず、最初のプロセスで、イオン活性化と結晶欠陥分布
の均一化のために、砒化ガリウム単結晶ウェハを100
0℃以上の高温に加熱する。1000℃より低い温度で
は均一化は起こらない。
First, in the first process, 100% of gallium arsenide single crystal wafers were processed for ion activation and uniform crystal defect distribution.
Heat to a high temperature of 0°C or higher. Homogenization does not occur at temperatures below 1000°C.

次のプロセスとして、EL2と呼ばれるドナーレベルの
均一化のために600℃以下の温度にして再加熱する。
The next process is reheating to a temperature below 600° C. to uniformize the donor level, which is called EL2.

望ましくは400〜600℃の範囲内に入れることが好
ましい。tooo’cから600℃までの降温は、不均
一性要因を排除するため出来る限り短時間内に急冷する
The temperature is desirably within the range of 400 to 600°C. The temperature reduction from too'c to 600° C. is carried out rapidly within as short a time as possible in order to eliminate non-uniformity factors.

最後に、充分なドナーレベル濃度を生成するために80
0℃以上の高温で加熱する。800℃よりも低い温度で
はドナーレベルは発生しない。
Finally, to generate sufficient donor level concentration, 80
Heat at a high temperature of 0°C or higher. No donor levels are generated at temperatures below 800°C.

これらの熱処理中にはウェハ表面から砒素(AS)が解
離して特性を劣化させるため、それを防ぐ必要からAs
雰囲気とする。As雰囲気とする方法には、ウェハをア
ンプル中に入れその中に投じたAsの昇華したガスによ
るものや、アルシンガスによるものも、あるいはウニ八
表面に打ち込まれたAsイオンによるものなどが考えら
れる。
During these heat treatments, arsenic (AS) dissociates from the wafer surface and deteriorates the characteristics, so to prevent this, As
Create an atmosphere. Possible methods for creating an As atmosphere include placing the wafer in an ampoule and using sublimated As gas thrown into the ampoule, using arsine gas, or using As ions implanted into the surface of the wafer.

また、砒化ガリウム単結晶は無添加の半絶縁性砒化ガリ
ウム、または、Cr添加の半絶縁性砒化ガリウムである
ことが好ましい。
Further, the gallium arsenide single crystal is preferably doped-free semi-insulating gallium arsenide or Cr-added semi-insulating gallium arsenide.

[作用] 砒化ガリウム単結晶ウェハ表面に所望の不純物イオンを
打ち込んだ後に、砒化ガリウム単結晶ウェハを1000
℃以上の高温に加熱すると、これによって打ち込んだイ
オンの活性化が図られると同時に、結晶ウェハ内に存在
していた結晶欠陥分布が均一化する。このまま室温に冷
却すると半絶縁性のために必要なEL2と呼ばれるドナ
ーレベルが冷却条件によって消失したり、あるいは不均
一分布したりしてしまう。
[Operation] After implanting desired impurity ions into the surface of a gallium arsenide single crystal wafer, the gallium arsenide single crystal wafer is
When heated to a high temperature of .degree. C. or higher, the implanted ions are activated, and at the same time, the distribution of crystal defects existing in the crystal wafer is made uniform. If it is cooled to room temperature in this state, the donor level called EL2, which is necessary for semi-insulating properties, will disappear or become unevenly distributed depending on the cooling conditions.

このため、600℃以下の温度で再加熱する。For this reason, it is reheated at a temperature of 600° C. or lower.

この場合、600℃以下の温度に徐々に冷却していくと
、降温途中で不均一性を誘起するような現象が生じるが
、急冷した場合には、降温途中で不均一性を誘起するよ
うな現象が生じない。この600℃以下の温度で加熱す
ると、EL2の均一化のための核が均一に生成される。
In this case, if the temperature is gradually cooled to below 600°C, a phenomenon that induces non-uniformity will occur during the cooling process, but if the temperature is rapidly cooled, a phenomenon that will induce non-uniformity during the cooling process will occur. No phenomenon occurs. When heated at a temperature of 600° C. or lower, nuclei for uniformizing EL2 are uniformly generated.

600℃より高い温度では均一に生成されない。It is not produced uniformly at temperatures higher than 600°C.

最後に、800℃以上の高温で加熱すると、このときE
L2と呼ばれるドナーレベルが充分な濃度で生成される
。ドナーレベルの濃度分布はその前のプロセスで生じた
均一分布する核の分布に支配されるため極めて均一とな
ある。
Finally, when heated at a high temperature of 800°C or higher, the E
A donor level called L2 is generated in sufficient concentration. The concentration distribution of the donor level is extremely uniform because it is dominated by the distribution of uniformly distributed nuclei produced in the previous process.

上記したように、本発明方法によれば、イオン注入後の
活性化熱処理に3段階の特殊な熱処理を適用するこ゛と
で、イオンの活性化と均一化を同時に満たすので、結晶
そのものの熱処理プロセスや、イオン打込み前のウェハ
熱処理プロセスを必要としない。
As described above, according to the method of the present invention, by applying a special three-step heat treatment to the activation heat treatment after ion implantation, ion activation and uniformity can be achieved at the same time. , does not require a wafer heat treatment process before ion implantation.

[実施例] 以下、本発明の実施例を比較例と共に説明する。[Example] Examples of the present invention will be described below along with comparative examples.

(比較例1) 3インチ径の、引上げ法で作製された無添加半絶縁性G
aAs結晶を、熱的な処理をせずにウェハに加工した。
(Comparative Example 1) Additive-free semi-insulating G made by a pulling method with a diameter of 3 inches
The aAs crystal was processed into wafers without thermal treatment.

鏡面にしたウェハに75KeVのエネルギでS i”y
sイオンをドーズ量3X10”Ctrl”打ち込んだ。
Si”y on a mirror-finished wafer with 75KeV energy
S ions were implanted at a dose of 3×10"Ctrl".

このウェハをアルシンガス3%を含んだ水素ガス中で8
50℃,15分間の熱処理をした。このウェハ全面にF
ETを250ミクロン間隔で作製し、しきい値電圧vt
hを測定したところ、平均値が一〇、5■であり、また
全FETのしきい値電圧バラツキσvthは150mV
と大きかった。
This wafer was placed in hydrogen gas containing 3% arsine gas for 8 hours.
Heat treatment was performed at 50°C for 15 minutes. F on the entire surface of this wafer
ETs were fabricated at 250 micron intervals, and the threshold voltage vt
When h was measured, the average value was 10.5■, and the threshold voltage variation σvth of all FETs was 150 mV.
It was big.

(実施例1) 比較例1と同じ3インチ無添加結晶より切り出したウェ
ハに同一条件でイオンを打込み、アルシンガス3%を含
んだ水素ガス中で熱処理した。条件は1100℃2分間
その後約3分間で600゜Cまで下げ、15分間保持し
、さらに850℃5分間熱処理した。同じ(FETを作
製し、しきい値vthを測定したところ−0,9Vとな
り、比較例よりも大幅に活性化率が向上したことがわか
った。また、しきい値バラツキσvthは3mVと一桁
以上改善できた。このとき、比較のため熱処理雰囲気を
Arガス中で行った試料を作り評価したところ、活性化
率を示すvthが一〇、2Vと低く、σvthも100
mVと大きく、熱処理雰囲気をAsガスにする必要を認
めた。
(Example 1) A wafer cut from the same 3-inch additive-free crystal as in Comparative Example 1 was implanted with ions under the same conditions and heat-treated in hydrogen gas containing 3% arsine gas. The conditions were 1100°C for 2 minutes, then lowered to 600°C for about 3 minutes, held for 15 minutes, and then heat-treated at 850°C for 5 minutes. When the same FET was fabricated and the threshold value vth was measured, it was found to be -0.9V, indicating that the activation rate was significantly improved compared to the comparative example.Also, the threshold variation σvth was 3 mV, which was a single digit At this time, for comparison, we made a sample in which the heat treatment was performed in an Ar gas atmosphere and evaluated it, and found that vth, which indicates the activation rate, was as low as 10.2 V, and σvth was also 100.
mV, which was large, and it was recognized that it was necessary to use As gas as the heat treatment atmosphere.

(比較例2) 実施例1.比較例1と同じ結晶をウェハに切り出す前に
、As雰囲気で1150℃で24h。
(Comparative Example 2) Example 1. Before cutting the same crystal as Comparative Example 1 into a wafer, it was heated at 1150° C. for 24 hours in an As atmosphere.

600℃で30h、950℃で24h熱処理し、以下同
じプロセスでイオンを打込み、FETを作った。打ち込
んだ後の活性化処理は850℃115分間である。この
ときウェハを石英アンプルに入れ、Asガスが20 t
orrになるよう固体のASを一緒に封入した。vth
=−o、6V、  σVth=7mVであった。事前の
熱処理により均一性は比較例1よりも改善されているが
、活性化率がやや悪い。これは活性化熱処理時にアクセ
プタレベルを持つ固有欠陥が発生したためと考えられる
Heat treatment was performed at 600° C. for 30 hours and at 950° C. for 24 hours, and ions were implanted using the same process thereafter to produce an FET. Activation treatment after implantation was performed at 850° C. for 115 minutes. At this time, the wafer was placed in a quartz ampoule, and 20 t of As gas was added.
Solid AS was encapsulated together so that orr. vth
= -o, 6V, σVth = 7mV. Although the uniformity was improved compared to Comparative Example 1 due to the prior heat treatment, the activation rate was somewhat poor. This is thought to be due to the generation of inherent defects with acceptor levels during the activation heat treatment.

(実施例2) 比較例2と同じ条件でFETを作った。ただし、打込み
後の活性化熱処理条件のみを変えた。ウェハを石英アン
プルに入れ、比較例2と同−As圧になるようにし、温
度条件を1100℃,3分間、その後約5分間で550
℃まで下げ30分間保持し、さらに850℃115分間
熱処理した。Vth=−0,9V、 σVth=2mV
と活性化率、均一性ともに良好であった。このことは、
事前の熱処理、即ち結晶そのものの熱処理やイオン打込
み前のウェハ熱処理は、これらを行っても行わなくても
関係な(、省略できることを意味する。
(Example 2) An FET was manufactured under the same conditions as Comparative Example 2. However, only the activation heat treatment conditions after implantation were changed. The wafer was placed in a quartz ampoule, the As pressure was the same as in Comparative Example 2, and the temperature conditions were 1100°C for 3 minutes, then 550°C for about 5 minutes.
The temperature was lowered to 850°C, held for 30 minutes, and further heat-treated at 850°C for 115 minutes. Vth=-0.9V, σVth=2mV
Both the activation rate and uniformity were good. This means that
Preliminary heat treatment, that is, heat treatment of the crystal itself and wafer heat treatment before ion implantation, does not matter whether or not they are performed (this means that they can be omitted).

(実施例3) 引上げ法で作製された4インチのCrドープ半絶縁性G
aAs結晶を作製した。Cr濃度は結晶中で0.Ol=
0.O5ppm、炭素濃度は3〜3 x l Q l 
4 c m −3である。以下、実施例2と同じ条件で
FETを作ったところ、Vth=−Q、  85■、σ
V th= 2 m Vと活性化率、均一性ともに良好
であった。
(Example 3) 4-inch Cr-doped semi-insulating G manufactured by pulling method
An aAs crystal was produced. The Cr concentration in the crystal is 0. Ol =
0. O5ppm, carbon concentration is 3~3 x l Q l
4 cm −3. Below, when an FET was made under the same conditions as in Example 2, Vth=-Q, 85■, σ
V th = 2 mV, both the activation rate and uniformity were good.

[発明の効果] 本発明によれば、イオン打込み後の活性化熱処理を3段
階の熱処理としたので、従来にない良好な活性化率と均
一性を同時に得ることができる。
[Effects of the Invention] According to the present invention, since the activation heat treatment after ion implantation is a three-step heat treatment, it is possible to simultaneously obtain an unprecedentedly good activation rate and uniformity.

また、注入イオンの活性化とウェハ特性の均一化を同時
に実現するようにしたので、従来行われている結晶の均
一化のための熱処理と、イオン打込み後の結晶ウェハの
熱処理を一回で済ますことができ、経済性に優れる。
In addition, since the implanted ions are activated and the wafer properties are made uniform at the same time, the conventional heat treatment for crystal uniformity and the heat treatment of the crystal wafer after ion implantation can be done in one go. It is highly economical.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による砒化ガリウム単結晶ウェハの熱処
理方法の一実施例を示す工程図である。
FIG. 1 is a process diagram showing an embodiment of the heat treatment method for a gallium arsenide single crystal wafer according to the present invention.

Claims (1)

【特許請求の範囲】 砒化ガリウム単結晶ウェハ表面に所望の不純物イオンを
打ち込んだ後に、注入不純物イオンを半導体結晶格子の
置換位置に入れて電気的に活性なものとするための熱処
理に際して、 上記単結晶ウェハを1000℃以上の温度に加熱し、 その後急冷して600℃以下の温度で再加熱し、 さらに800℃以上の温度で最終の熱処理をする ことを特徴とする砒化ガリウム単結晶ウェハの熱処理方
法。
[Claims] After implanting desired impurity ions into the surface of a gallium arsenide single crystal wafer, the implanted impurity ions are placed in replacement positions in the semiconductor crystal lattice during heat treatment to make them electrically active. Heat treatment of gallium arsenide single crystal wafers, characterized by heating the crystal wafer to a temperature of 1000°C or higher, then rapidly cooling it, reheating it to a temperature of 600°C or lower, and then performing a final heat treatment at a temperature of 800°C or higher. Method.
JP29848289A 1989-11-16 1989-11-16 Method for thermally treating single-crystal gallium arsenide wafer Pending JPH03159118A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29848289A JPH03159118A (en) 1989-11-16 1989-11-16 Method for thermally treating single-crystal gallium arsenide wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29848289A JPH03159118A (en) 1989-11-16 1989-11-16 Method for thermally treating single-crystal gallium arsenide wafer

Publications (1)

Publication Number Publication Date
JPH03159118A true JPH03159118A (en) 1991-07-09

Family

ID=17860274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29848289A Pending JPH03159118A (en) 1989-11-16 1989-11-16 Method for thermally treating single-crystal gallium arsenide wafer

Country Status (1)

Country Link
JP (1) JPH03159118A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100562438B1 (en) * 1997-10-30 2006-07-06 신에쯔 한도타이 가부시키가이샤 Heat Treatment Method of Silicon Wafer and Silicon Wafer Heat Treated thereby

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100562438B1 (en) * 1997-10-30 2006-07-06 신에쯔 한도타이 가부시키가이샤 Heat Treatment Method of Silicon Wafer and Silicon Wafer Heat Treated thereby

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